From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH 1/3] i40e: enable extended tag Date: Fri, 22 Jan 2016 11:26:31 +0100 Message-ID: <3789056.EpDHogkSc1@xps13> References: <1450665486-8335-1-git-send-email-helin.zhang@intel.com> <1450665486-8335-2-git-send-email-helin.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev@dpdk.org To: Helin Zhang Return-path: Received: from mail-wm0-f53.google.com (mail-wm0-f53.google.com [74.125.82.53]) by dpdk.org (Postfix) with ESMTP id 64CBD8EA1 for ; Fri, 22 Jan 2016 11:27:32 +0100 (CET) Received: by mail-wm0-f53.google.com with SMTP id l65so254998394wmf.1 for ; Fri, 22 Jan 2016 02:27:32 -0800 (PST) In-Reply-To: <1450665486-8335-2-git-send-email-helin.zhang@intel.com> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 2015-12-21 10:38, Helin Zhang: > PCIe feature of 'Extended Tag' is important for 40G performance. > It adds its enabling during each port initialization, to ensure > the high performance. If it's so important, why the values are not documented? Please start to fill a file doc/guides/nics/i40e.rst to explain how the device works. Thanks