From mboxrd@z Thu Jan 1 00:00:00 1970 From: Roman Dementiev Subject: Re: RTM instruction compile failure for XABORT when AVX is active Date: Mon, 29 Jun 2015 12:11:37 +0200 Message-ID: <386858255.20150629121137@intel.com> References: <1A87AD2E-38CD-4C61-A9FD-C52608FF9DAC@mhcomputing.net> <038E8439-A99C-40BB-9A77-B20024E4111F@mhcomputing.net> <39879033.dIVnPGkh8l@xps13> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: dev@dpdk.org To: Thomas Monjalon , Matthew Hall Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id A618CC498 for ; Mon, 29 Jun 2015 12:11:40 +0200 (CEST) In-Reply-To: <39879033.dIVnPGkh8l@xps13> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hello Thomas, Sunday, June 28, 2015, 9:38:14 PM, you wrote: > 2015-06-28 10:59, Matthew Hall: >> It would appear there is some bug in the new lock elision patches that is preventing it from compiling with clang. Any suggestions? > It builds with clang. > My suggestion is to add the patch author in recipient's list ;) >> On Jun 28, 2015, at 10:16 AM, Matthew Hall wrote: >> >> > Hi all, >> > >> > I am getting a strange error compiling some RTM instructions when I upgraded my VM environment from VirtualBox 4 to VirtualBox 5 and AVX instructions from the host CPU became available. However when I am reading the opcode description for XABORT it supposedly allows an immediate operand for the argument so I can't understand why this code would not compile. Any advice? >> > >> > CC test_hash_scaling.o >> > In file included from /vagrant/external/dpdk/app/test/test_hash_scaling.c:37: >> > In file included from /vagrant/external/dpdk/build/include/rte_spinlock.h:42: >> > /vagrant/external/dpdk/build/include/rte_rtm.h:56:15: error: invalid operand for inline asm constraint 'i' >> > asm volatile(".byte 0xc6,0xf8,%P0" :: "i" (status) : "memory"); >> > >> > Matthew. >> It looks like a compiler bug for me. In the meantime Clang should have native TSX intrinsics (but most compilers fail to implement them correctly on a first attempt allowing instruction reordering). Could you try this workaround: diff --git a/lib/librte_eal/common/include/arch/x86/rte_rtm.h b/lib/librte_eal/common/include/arch/x86/rte_rtm.h index d935641..ee73dd4 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_rtm.h +++ b/lib/librte_eal/common/include/arch/x86/rte_rtm.h @@ -50,10 +50,14 @@ void rte_xend(void) asm volatile(".byte 0x0f,0x01,0xd5" ::: "memory"); } +#include + static __attribute__((__always_inline__)) inline void rte_xabort(const unsigned int status) { - asm volatile(".byte 0xc6,0xf8,%P0" :: "i" (status) : "memory"); + asm volatile(::: "memory"); + _xabort(status); + asm volatile(::: "memory"); } static __attribute__((__always_inline__)) inline -- Best regards, Roman mailto:roman.dementiev@intel.com Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052