From: Raslan Darawsheh <rasland@nvidia.com>
To: Gregory Etelson <getelson@nvidia.com>, dev@dpdk.org
Cc: mkashani@nvidia.com, stable@dpdk.org,
Dariusz Sosnowski <dsosnowski@nvidia.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
Bing Zhao <bingz@nvidia.com>, Ori Kam <orika@nvidia.com>,
Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Subject: Re: [PATCH] net/mlx5: fix register selection for metadata between E-Switch and VM
Date: Wed, 4 Feb 2026 17:10:21 +0200 [thread overview]
Message-ID: <49e01eee-513a-49ca-ac6a-8466ba2203c6@nvidia.com> (raw)
In-Reply-To: <20251201173628.266032-1-getelson@nvidia.com>
Hi,
On 01/12/2025 7:36 PM, Gregory Etelson wrote:
> The PMD relied on a flow domain type in register selection for
> modify header action that assigned metadata value.
>
> In the HWS code, the PMD uses the MLX5DR_TABLE_TYPE_MAX instead of
> the exact domain type for flows in group 0.
> As a result, the register selection was wrong.
>
> This patch fixes the register selection logic when flow metadata
> sharing between E-Switch and VM is enabled.
> In this case REG_C_1 will always be used.
>
> Fixes: a78425ba3793 ("net/mlx5: support flow metadata between E-Switch and VM")
> Cc: stable@dpdk.org
>
> Signed-off-by: Gregory Etelson <getelson@nvidia.com>
> Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Patch applied to next-net-mlx,
Kindest regards
Raslan Darawsheh
prev parent reply other threads:[~2026-02-04 15:10 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-01 17:36 [PATCH] net/mlx5: fix register selection for metadata between E-Switch and VM Gregory Etelson
2026-02-04 15:10 ` Raslan Darawsheh [this message]
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