From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ferruh Yigit <ferruh.yigit@intel.com>
Subject: Re: [PATCH v3 17/29] net/bnx2x: use eal I/O device
 memory read/write API
Date: Thu, 12 Jan 2017 19:11:18 +0000
Message-ID: <53b0ad99-4b69-41ef-4630-881d9797e6e8@intel.com>
References: <1482832175-27199-1-git-send-email-jerin.jacob@caviumnetworks.com>
 <1484212646-10338-1-git-send-email-jerin.jacob@caviumnetworks.com>
 <1484212646-10338-18-git-send-email-jerin.jacob@caviumnetworks.com>
Mime-Version: 1.0
Content-Type: text/plain; charset=windows-1252
Content-Transfer-Encoding: 8bit
Cc: konstantin.ananyev@intel.com, thomas.monjalon@6wind.com,
 bruce.richardson@intel.com, jianbo.liu@linaro.org, viktorin@rehivetech.com,
 santosh.shukla@caviumnetworks.com, Harish Patil <harish.patil@cavium.com>,
 Rasesh Mody <rasesh.mody@cavium.com>
To: Jerin Jacob <jerin.jacob@caviumnetworks.com>, dev@dpdk.org
Return-path: <dev-bounces@dpdk.org>
Received: from mga01.intel.com (mga01.intel.com [192.55.52.88])
 by dpdk.org (Postfix) with ESMTP id 370015A44
 for <dev@dpdk.org>; Thu, 12 Jan 2017 20:11:23 +0100 (CET)
In-Reply-To: <1484212646-10338-18-git-send-email-jerin.jacob@caviumnetworks.com>
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

On 1/12/2017 9:17 AM, Jerin Jacob wrote:
<...>
>  
> @@ -1560,11 +1556,9 @@ bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
>  #define DPM_TRIGGER_TYPE 0x40
>  
>  /* Doorbell macro */
> -#define BNX2X_DB_WRITE(db_bar, val) \
> -	*((volatile uint32_t *)(db_bar)) = (val)
> +#define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar))

What is the rule to use relaxed version or not?

I don't know about memory barrier requirements, if it is easy, would you
mind explaining? Because I have same question for many different parts
of this patchset.

Thanks,
ferruh