From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gyumin Subject: Relationship between H/W ring and S/W ring Date: Thu, 30 Oct 2014 16:32:16 +0900 Message-ID: <5451E980.2060707@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit To: dev-VfR2kkLFssw@public.gmane.org Return-path: List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" Hi I`m reading the ixgbe code especially about H/W ring and S/W ring. Is the relationship between H/W ring and S/W ring one-to-one mapping? As far as I know, H/W ring size is determined in the code(hard coded) while S/W ring size is determined in port configuration time. In the ixgbe_rx_alloc_bufs function, H/W ring header address and packet address indicate the DMA address of S/W ring's mbuf. I understand it means that the relationship between the H/W ring and S/W ring is one-to-one mapping. For example, if the size of H/W ring is greater than the size of S/W ring then some portion of H/W ring is unused. Is it correct? Thanks