From mboxrd@z Thu Jan 1 00:00:00 1970 From: GyuminHwang Subject: Re: Relationship between H/W ring and S/W ring Date: Sat, 01 Nov 2014 22:52:56 +0900 Message-ID: <5454E5B8.4030809@gmail.com> References: <5451E980.2060707@gmail.com> <20141030095522.GA4460@bricha3-MOBL3> <5452DD2C.8030402@gmail.com> <20141031100817.GA4948@bricha3-MOBL3> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Cc: dev-VfR2kkLFssw@public.gmane.org To: Bruce Richardson Return-path: In-Reply-To: <20141031100817.GA4948@bricha3-MOBL3> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" Now I understand. Thanks Bruce. 2014=EB=85=84 10=EC=9B=94 31=EC=9D=BC 19:08=EC=97=90 Bruce Richardson =EC= =9D=B4(=EA=B0=80) =EC=93=B4 =EA=B8=80: > On Fri, Oct 31, 2014 at 09:51:56AM +0900, Gyumin wrote: >> Thanks Bruce. >> >> I also agree with that the size of the S/W ring depends on the configu= ration >> parameters because the size of the S/W ring is /sizeof(struct igb_rx_e= ntry) >> * len/ in the ixgbe_dev_rx_queue_setup function. H/W ring is also allo= cated >> in the same function by using the ring_dma_zone_reserve function, and = its >> size is RX_RING_SZ. I don't think the RX_RING_SZ is configurable but i= t is >> fixed value. Is there any other code configuring the size of H/W ring? >> > Indeed you are right, my mistake. The comment indicates that we always = reserve > the memory to be the maximum size so that we can resize the rings easie= r later > on. > In terms of runtime usage, though, if you look a the RX functions, you = can see > that the two rings are always kept in sync. For example, looking at > ixgbe_rxq_rearm in ixgbe_rxtx_vec.c, you will see that rxdp and rxep va= lues > both start at offset "rxq->rxrearm_start" at the top of the function, a= nd that > in the main rearm loop, both are incremented twice each iteration (rxep= +=3D 2 in > the for statment itself, and two rxdp++'s are used in the last two line= s of the > loop body). > > Regards, > /Bruce > >> 2014-10-30 =EC=98=A4=ED=9B=84 6:55=EC=97=90 Bruce Richardson =EC=9D=B4= (=EA=B0=80) =EC=93=B4 =EA=B8=80: >>> On Thu, Oct 30, 2014 at 04:32:16PM +0900, Gyumin wrote: >>>> Hi >>>> >>>> I`m reading the ixgbe code especially about H/W ring and S/W ring. I= s the >>>> relationship between H/W ring and S/W ring one-to-one mapping? >>>> As far as I know, H/W ring size is determined in the code(hard coded= ) while >>>> S/W ring size is determined in port configuration time. >>>> In the ixgbe_rx_alloc_bufs function, H/W ring header address and pac= ket >>>> address indicate the DMA address of S/W ring's mbuf. I understand it= means >>>> that the relationship between the H/W ring and S/W ring is one-to-on= e >>>> mapping. For example, if the size of H/W ring is greater than the si= ze of >>>> S/W ring then some portion of H/W ring is unused. Is it correct? >>>> >>>> Thanks >>> Hi, >>> >>> Yes, there is a 1:1 mapping between the hardware and software ring en= tries, and both are sized depending on the configuration parameters passe= d to the ring setup APIs. As you state, the HW ring contains the DMA addr= esses of the packet buffers, while the sw_ring contains the pointers to t= he original mbufs. The two rings are always kept in sync in the code. >>> >>> /Bruce >>>