From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vlad Zolotarov Subject: Re: [PATCH v4 1/6] ixgbe: Code cleanup Date: Sun, 04 Jan 2015 10:22:13 +0200 Message-ID: <54A8F835.3010400@cloudius-systems.com> References: <1419398584-19520-1-git-send-email-changchun.ouyang@intel.com> <1420355937-18484-1-git-send-email-changchun.ouyang@intel.com> <1420355937-18484-2-git-send-email-changchun.ouyang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit To: Ouyang Changchun , dev-VfR2kkLFssw@public.gmane.org Return-path: In-Reply-To: <1420355937-18484-2-git-send-email-changchun.ouyang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" On 01/04/15 09:18, Ouyang Changchun wrote: > Put global register configuring out of loop for queue; also fix typo and indent; > Also fix typo and indent. > > Signed-off-by: Changchun Ouyang Reviewed-by: Vlad Zolotarov > --- > lib/librte_pmd_ixgbe/ixgbe_rxtx.c | 35 ++++++++++++++++++----------------- > 1 file changed, 18 insertions(+), 17 deletions(-) > > diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c > index 5c36bff..f69abda 100644 > --- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c > +++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c > @@ -3548,9 +3548,9 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev) > IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype); > } > srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size << > - IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & > - IXGBE_SRRCTL_BSIZEHDR_MASK); > - srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; > + IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & > + IXGBE_SRRCTL_BSIZEHDR_MASK); > + srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; > } else > #endif > srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; > @@ -3985,7 +3985,7 @@ ixgbevf_dev_rx_init(struct rte_eth_dev *dev) > struct igb_rx_queue *rxq; > struct rte_pktmbuf_pool_private *mbp_priv; > uint64_t bus_addr; > - uint32_t srrctl; > + uint32_t srrctl, psrtype = 0; > uint16_t buf_size; > uint16_t i; > int ret; > @@ -4039,20 +4039,10 @@ ixgbevf_dev_rx_init(struct rte_eth_dev *dev) > * Configure Header Split > */ > if (dev->data->dev_conf.rxmode.header_split) { > - > - /* Must setup the PSRTYPE register */ > - uint32_t psrtype; > - psrtype = IXGBE_PSRTYPE_TCPHDR | > - IXGBE_PSRTYPE_UDPHDR | > - IXGBE_PSRTYPE_IPV4HDR | > - IXGBE_PSRTYPE_IPV6HDR; > - > - IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype); > - > srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size << > - IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & > - IXGBE_SRRCTL_BSIZEHDR_MASK); > - srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; > + IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & > + IXGBE_SRRCTL_BSIZEHDR_MASK); > + srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; > } else > #endif > srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; > @@ -4095,6 +4085,17 @@ ixgbevf_dev_rx_init(struct rte_eth_dev *dev) > } > } > > +#ifdef RTE_HEADER_SPLIT_ENABLE > + if (dev->data->dev_conf.rxmode.header_split) > + /* Must setup the PSRTYPE register */ > + psrtype = IXGBE_PSRTYPE_TCPHDR | > + IXGBE_PSRTYPE_UDPHDR | > + IXGBE_PSRTYPE_IPV4HDR | > + IXGBE_PSRTYPE_IPV6HDR; > +#endif > + > + IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype); > + > if (dev->data->dev_conf.rxmode.enable_scatter) { > if (!dev->data->scattered_rx) > PMD_INIT_LOG(DEBUG, "forcing scatter mode");