From mboxrd@z Thu Jan 1 00:00:00 1970 From: Olivier MATZ Subject: Re: [PATCH v3 0/3] enhance TX checksum command and csum forwarding engine Date: Wed, 21 Jan 2015 10:10:57 +0100 Message-ID: <54BF6D21.3010506@6wind.com> References: <1418173403-30202-1-git-send-email-jijiang.liu@intel.com> <1ED644BD7E0A5F4091CF203DAFB8E4CC01DA7CC5@SHSMSX101.ccr.corp.intel.com> <2601191342CEEE43887BDE71AB977258213D3897@irsmsx105.ger.corp.intel.com> <54AFB13E.2080200@6wind.com> <1ED644BD7E0A5F4091CF203DAFB8E4CC01DA85A1@SHSMSX101.ccr.corp.intel.com> <54B3B35A.5030803@6wind.com> <1ED644BD7E0A5F4091CF203DAFB8E4CC01DA8E36@SHSMSX101.ccr.corp.intel.com> <54B4EB92.40209@6wind.com> <1ED644BD7E0A5F4091CF203DAFB8E4CC01DB0789@SHSMSX101.ccr.corp.intel.com> <2601191342CEEE43887BDE71AB977258213D4FCF@irsmsx105.ger.corp.intel.com> <54B94A18.5030700@6wind.com> <2601191342CEEE43887BDE71AB977258213DCD25@irsmsx105.ger.corp.intel.com> <54BD16F1.6050409@6wind.com> <2601191342CEEE43887BDE71AB977258213DDF46@irsmsx105.ger.corp.intel.com> <54BE4C70.7050406@6wind.com> <2601191342CEEE43887BDE71AB977258213DE5FB@irsmsx105.ger.corp.intel.com> <54BE9B56.7050108@6wind.com> <1ED644BD7E0A5F4091CF203DAFB8E4CC01DB56B3@SHSMSX101.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Cc: "dev-VfR2kkLFssw@public.gmane.org" To: "Liu, Jijiang" Return-path: In-Reply-To: <1ED644BD7E0A5F4091CF203DAFB8E4CC01DB56B3-0J0gbvR4kThpB2pF5aRoyrfspsVTdybXVpNB7YpNyf8@public.gmane.org> List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" Hi Jijiang, On 01/21/2015 09:01 AM, Liu, Jijiang wrote: >>> I still don't understand why you are so eager to 'forbid' it. >>> Yes we support it for FVL, but no one forces you to use it. >> >> Well, how would you describe this 2 ways of doing the same thing in the >> offload API? Would you talk about the i40e registers? It's not because i40e >> has 2 ways to do the same operation that the DPDK should do the same. >> >> How will you explain to a user how to choose between these 2 cases? > > Talk about B method in http://dpdk.org/ml/archives/dev/2014-December/009213.html again. > > DPDK Never supports a NIC that can recognize tunneling packet for TX side before 1.8, right? When you say "recognize tunnel", if you mean offlading checksum of tunnel headers, I agree. If you mean recognizing a tunnel packet in rx, I also agree it's new to dpdk-1.8, but I think it's unrelated to what we are talking about, which is tx checksum. A DPDK application is able to generate tunnel packets by itself and offload the checksums to the NIC. > So when we need to support TX checksum offload for tunneling packet, and we have to choose B.2. I don't see why we should choose either B.1 or B.2 (I guess you want to say B.1 here, right?). The m->lX_len are not filled in rx today. If one day they are, it won't prevent the application to configure the lX_len fields and offload flags according to the API. > After introducing i40e(FVL), FVL is able to recognize tunneling packet and support outer IP, or inner IP or outer IP and inner IP TX checksum for tunneling packet. > And you agree on "outer and inner at the same time", why do you object "only inner"? > > Actually, B.2 method is a software workaround using L2 length when NIC can't recognize tunneling packet. > When NIC is able to recognize tunneling packet, I think you shouldn't take B.2 as a standard to 'forbid' other method. Again, I'm not sure there is a link between "recognizing tunneling packets" and tx checksum offload of tunnels. Regards, Olivier