From mboxrd@z Thu Jan  1 00:00:00 1970
From: Thomas Monjalon <thomas@monjalon.net>
Subject: Re: [PATCH v2] doc: add known issue for i40e VF
	performance
Date: Mon, 10 Jul 2017 00:49:46 +0200
Message-ID: <5809031.eT3YHgoUoZ@xps>
References: <20170703035754.4622-1-qi.z.zhang@intel.com>
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Cc: dev@dpdk.org, john.mcnamara@intel.com, jingjing.wu@intel.com,
 helin.zhang@intel.com
To: Qi Zhang <qi.z.zhang@intel.com>
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Hi,

Few typos spotted

03/07/2017 05:57, Qi Zhang:
> --- a/doc/guides/nics/i40e.rst
> +++ b/doc/guides/nics/i40e.rst
> @@ -447,3 +447,30 @@ It means if APP has set the max bandwidth for that TC, it comes to no
>  effect.
>  It's suggested to set the strict priority mode for a TC that is latency
>  sensitive but no consuming much bandwidth.
> +
> +VF performance is impacted by PCI extended tag setting
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +To reach maximum NIC performance in the VF the PCI extended tag must be
> +enabled. The DPDK I40E PF drvier will set this feature during initialization,

drvier -> driver

> +but the kernel PF driver does not. So when running traffic on a VF which is
> +managed by the kernel PF driver, a significent NIC performance downgrade has

significent -> significant

> +been observed (for 64 byte packets, there is about 25% linerate downgrade for
> +a 25G device and about 35% for a 40G device).
> +
> +For kernel version >= 4.11, the kernel's PCI driver will enable the extended
> +tag if it detects that the device supports it. So by default, this is not an
> +issue. For kernels <= 4.11 or When the PCI extended tag is disabled it can be

When -> when

> +enabled using the steps below.
> +
> +#. Get the current value of the PCI configure register::
> +
> +      setpci -s <XX:XX.X> a8.w
> +
> +#. Set bit 8::
> +
> +      value = value | 0x100
> +
> +#. Set the PCI configure register with new value::
> +
> +      setpci -s <XX:XX.X> a8.w=<value>