From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ferruh Yigit Subject: Re: [PATCH] kni: fix kni rx fifo producer synchronization Date: Thu, 9 Aug 2018 12:30:57 +0100 Message-ID: <5debc6df-9bed-597a-03e2-510372b849e0@intel.com> References: <1533810233-7706-1-git-send-email-kkokkilagadda@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Cc: dev@dpdk.org, Jerin Jacob , Konstantin Ananyev , Bruce Richardson , Santosh Shukla To: Kiran Kumar Return-path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id BF6B625D9 for ; Thu, 9 Aug 2018 13:31:02 +0200 (CEST) In-Reply-To: <1533810233-7706-1-git-send-email-kkokkilagadda@caviumnetworks.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 8/9/2018 11:23 AM, Kiran Kumar wrote: > With existing code in kni_fifo_put, rx_q values are not being updated > before updating fifo_write. While reading rx_q in kni_net_rx_normal, > This is causing the sync issue on other core. So adding a write > barrier to make sure the values being synced before updating fifo_write. > > Fixes: 3fc5ca2f6352 ("kni: initial import") > > Signed-off-by: Kiran Kumar > --- > lib/librte_kni/rte_kni_fifo.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/lib/librte_kni/rte_kni_fifo.h b/lib/librte_kni/rte_kni_fifo.h > index ac26a8c..4d6b33e 100644 > --- a/lib/librte_kni/rte_kni_fifo.h > +++ b/lib/librte_kni/rte_kni_fifo.h > @@ -39,6 +39,7 @@ kni_fifo_put(struct rte_kni_fifo *fifo, void **data, unsigned num) > fifo->buffer[fifo_write] = data[i]; > fifo_write = new_write; > } > + rte_smp_wmb(); > fifo->write = fifo_write; > return i; For Intel this is just a compiler barrier so no issue but not sure if a memory barrier is required here, Related code block is: |- for (i = 0; i < num; i++) { || new_write = (new_write + 1) & (fifo->len - 1); || || if (new_write == fifo_read) || break; || fifo->buffer[fifo_write] = data[i]; || fifo_write = new_write; || } | fifo->write = fifo_write; "fifo_write" is updated in the loop, so there is a dependency to it for "fifo->write". Can memory writes be reordered when there is a dependency? Cc'ed a few more people for comment.