From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gowrishankar Subject: [PATCH v2 2/5] eal/ppc64: define architecture specific rdtsc hz Date: Fri, 22 Sep 2017 13:55:34 +0530 Message-ID: <60996b50e628207157f1b7b6dab704b8224f3cae.1506058385.git.gowrishankar.m@linux.vnet.ibm.com> References: Cc: Chao Zhu , Bruce Richardson , Konstantin Ananyev , Jerin Jacob , viktorin@rehivetech.com, jianbo.liu@linaro.org To: dev@dpdk.org Return-path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by dpdk.org (Postfix) with ESMTP id D90CE199A9 for ; Fri, 22 Sep 2017 10:25:52 +0200 (CEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v8M8NqRJ044222 for ; Fri, 22 Sep 2017 04:25:52 -0400 Received: from e23smtp06.au.ibm.com (e23smtp06.au.ibm.com [202.81.31.148]) by mx0b-001b2d01.pphosted.com with ESMTP id 2d4x3ejkxr-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 22 Sep 2017 04:25:51 -0400 Received: from localhost by e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 22 Sep 2017 18:25:49 +1000 Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v8M8PlAq40894576 for ; Fri, 22 Sep 2017 18:25:47 +1000 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v8M8PdeG009618 for ; Fri, 22 Sep 2017 18:25:39 +1000 In-Reply-To: In-Reply-To: References: List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob In ppc_64, rte_rdtsc() returns timebase register value which increments at independent timebase frequency and hence not related to lcore cpu frequency to derive TSC hz. Hence, we stick with master lcore frequency. CC: Chao Zhu Signed-off-by: Jerin Jacob Signed-off-by: Gowrishankar Muthukrishnan --- v2: * add ppc_64 specific implementation .../common/include/arch/ppc_64/rte_cycles.h | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h b/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h index 8fa6fc6..1b36587 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h @@ -38,9 +38,13 @@ #endif #include "generic/rte_cycles.h" +#include "../../lib/librte_eal/common/eal_filesystem.h" #include #include +#include + +static const char sys_cpu_dir[] = "/sys/devices/system/cpu"; /** * Read the time base register. @@ -79,6 +83,26 @@ return tsc.tsc_64; } +/** + * Get the number of rdtsc cycles in one second. + * + * @return + * The number of rdtsc cycles in one second. + */ +static inline uint64_t +rte_rdtsc_arch_hz(void) +{ + unsigned long cpu_hz; + char path[PATH_MAX]; + + snprintf(path, sizeof(path), "%s/cpu%d/cpufreq/cpuinfo_cur_freq", + sys_cpu_dir, rte_get_master_lcore()); + if (eal_parse_sysfs_value(path, &cpu_hz) < 0) + RTE_LOG(WARNING, EAL, "Unable to parse %s\n", path); + + return cpu_hz*1000; +} + static inline uint64_t rte_rdtsc_precise(void) { -- 1.9.1