From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jia He Subject: About pmu cycle counter usage in armv8 Date: Mon, 11 Dec 2017 13:38:25 +0800 Message-ID: <676baa87-777b-ca6e-41c9-7233f90740b6@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 7bit To: Jerin Jacob , "dev@dpdk.org" Return-path: Received: from mail-pf0-f174.google.com (mail-pf0-f174.google.com [209.85.192.174]) by dpdk.org (Postfix) with ESMTP id EABF3239 for ; Mon, 11 Dec 2017 06:38:35 +0100 (CET) Received: by mail-pf0-f174.google.com with SMTP id u19so10762074pfa.12 for ; Sun, 10 Dec 2017 21:38:35 -0800 (PST) List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Jerin In [1], I met a pmu cycle counter problem (all return value is 0) occasionally. And then I submited a patch to kernel maillist, but was rejected by maintainer at last [2]. He said: "We only intend for the in-kernel perf infrastructure to access pmccntr_el0; nothing else should touch it." So maybe it is not proper for dpdk to use pmu cycle counter? [1] http://dpdk.org/ml/archives/dev/2017-November/080998.html [2]https://lkml.org/lkml/2017/11/16/22 -- Cheers, Jia