[PATCH 01/18] common/cnxk: fix engine capabilities fetch logic

[PATCH 01/18] common/cnxk: fix engine capabilities fetch logic

[Rahul Bhansali]

From: Rakesh Kudurumalla <rkudurumalla@marvell.com>

While retrieving engine capabilities for CN9K we are
checking wrong for status LOADFVC instruction resulting
in loop.This patch fixes the same.

Fixes: 7c67c489d466 ("common/cnxk: fetch engine capabilities")

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
 drivers/common/cnxk/cnxk_security.c | 4 ++--
 drivers/common/cnxk/roc_nix_inl.c   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index 600098ae1c..14d29e605a 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -1397,7 +1397,7 @@ ow_ipsec_sa_common_param_fill(union roc_ow_ipsec_sa_word2 *w2, uint8_t *cipher_k
 			plt_err("Expiry tracking with both packets & bytes is not supported");
 			return -EINVAL;
 		}
-		w2->s.life_unit = ROC_IE_OT_SA_LIFE_UNIT_PKTS;
+		w2->s.life_unit = ROC_IE_OW_SA_LIFE_UNIT_PKTS;
 	}
 
 	if (ipsec_xfrm->life.bytes_soft_limit != 0 || ipsec_xfrm->life.bytes_hard_limit != 0) {
@@ -1406,7 +1406,7 @@ ow_ipsec_sa_common_param_fill(union roc_ow_ipsec_sa_word2 *w2, uint8_t *cipher_k
 			plt_err("Expiry tracking with both packets & bytes is not supported");
 			return -EINVAL;
 		}
-		w2->s.life_unit = ROC_IE_OT_SA_LIFE_UNIT_OCTETS;
+		w2->s.life_unit = ROC_IE_OW_SA_LIFE_UNIT_OCTETS;
 	}
 
 	return 0;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index f8be98efd5..683a9cc7ce 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1228,7 +1228,7 @@ nix_inl_eng_caps_get(struct nix *nix)
 		do {
 			roc_lmt_mov_seg((void *)lmt_base, &inst, 4);
 			lmt_status = roc_lmt_submit_ldeor(lf->io_addr);
-		} while (lmt_status != 0);
+		} while (lmt_status == 0);
 
 		/* Wait until CPT instruction completes */
 		do {
-- 
2.34.1

[PATCH 02/18] common/cnxk: remove dependency on cryptodev for RXC

[Rahul Bhansali]

Removes dependency on probe of cryptodev for reassembly
configuration and included RXC queue config for cn20k
platform.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.c | 15 ++++++++-------
 drivers/common/cnxk/roc_nix_inl.h |  2 ++
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 683a9cc7ce..86bafd5c33 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -968,12 +968,6 @@ roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t max_
 	if (!idev)
 		return -EFAULT;
 
-	roc_cpt = idev->cpt;
-	if (!roc_cpt) {
-		plt_err("Cannot support inline inbound, cryptodev not probed");
-		return -ENOTSUP;
-	}
-
 	cfg.step = req_cfg->step ? req_cfg->step :
 				   (max_wait_time * 1000 / ROC_NIX_INL_REAS_ACTIVE_LIMIT);
 	cfg.zombie_limit =
@@ -985,8 +979,14 @@ roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t max_
 	cfg.active_thres =
 		req_cfg->active_thres ? req_cfg->active_thres : ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;
 
-	if (roc_model_is_cn10k())
+	if (roc_model_is_cn10k()) {
+		roc_cpt = idev->cpt;
+		if (!roc_cpt) {
+			plt_err("Cryptodev not probed");
+			return -ENOTSUP;
+		}
 		return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
+	}
 
 	inl_dev = idev->nix_inl_dev;
 	if (!inl_dev) {
@@ -1009,6 +1009,7 @@ roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t max_
 	req->zombie_thres = cfg.zombie_thres;
 	req->active_limit = cfg.active_limit;
 	req->active_thres = cfg.active_thres;
+	req->cpt_af_rxc_que_cfg = ROC_NIX_INL_RXC_QUE_BLK_THR << 32;
 
 	rc = mbox_process(mbox);
 exit:
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index 7970ac2258..68f395438c 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -41,6 +41,8 @@
 #define ROC_NIX_INL_REAS_ZOMBIE_LIMIT	  0xFFF
 #define ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD 10
 
+#define ROC_NIX_INL_RXC_QUE_BLK_THR 0x40UL
+
 enum nix_inl_event_type {
 	NIX_INL_CPT_CQ = 1,
 	NIX_INL_SSO,
-- 
2.34.1

[PATCH 03/18] common/cnxk: support inbound pdb configuration

[Rahul Bhansali]

Mbox cpt_rx_inl_queue_cfg is extended to enable/disable PDB
for inline inbound IPsec path.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h        | 4 +++-
 drivers/common/cnxk/roc_nix_inl_dev.c | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 3e913fa13c..7871613d9c 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -2423,7 +2423,9 @@ struct cpt_rx_inline_qcfg_req {
 	uint8_t __io pf_func_ctx;
 	uint8_t __io inflight_limit;
 	uint8_t __io queue_pri;
-	uint8_t __io rsvd[32]; /* For future extensions */
+	uint8_t __io cq_remap;
+	uint8_t __io pdb_ena;
+	uint8_t __io rsvd[30]; /* For future extensions */
 };
 
 #define CPT_INLINE_INBOUND  0
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 1eb96f913a..fcbe9314a1 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -212,6 +212,7 @@ nix_inl_inb_queue_setup(struct nix_inl_dev *inl_dev, uint8_t slot_id)
 	cpt_req->slot = slot_id;
 	cpt_req->rx_queue_id = qid;
 	cpt_req->eng_grpmsk = inl_dev->eng_grpmask;
+	cpt_req->pdb_ena = 1;
 	rc = mbox_process(mbox);
 	if (rc) {
 		plt_err("Failed to configure CPT LF for inline processing, rc=%d", rc);
-- 
2.34.1

[PATCH 04/18] common/cnxk: update CPT RXC structures

[Rahul Bhansali]

Updates CPT RXC SGs and frag info structures for
cn20k platforms.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/hw/cpt.h        | 143 +++++++++++++++++++---------
 drivers/common/cnxk/roc_cpt_debug.c |   2 +-
 2 files changed, 101 insertions(+), 44 deletions(-)

diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index 727cee07b4..6e577b6277 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -549,30 +549,60 @@ union cpt_frag_info {
 	};
 };
 
-struct cpt_frag_info_s {
-	/* WORD 0 */
-	union {
-		uint64_t u64;
-		struct {
-			/* CPT HW swaps each 8B word implicitly */
-			union cpt_frag_info f0;
-			union cpt_frag_info f1;
-			union cpt_frag_info f2;
-			union cpt_frag_info f3;
-		};
-	} w0;
+union cpt_rxc_frag_info_u {
+	struct cpt_frag_info_s {
+		/* WORD 0 */
+		union {
+			uint64_t u64;
+			struct {
+				/* CPT HW swaps each 8B word implicitly */
+				union cpt_frag_info f3;
+				union cpt_frag_info f2;
+				union cpt_frag_info f1;
+				union cpt_frag_info f0;
+			};
+		} w0;
 
-	/* WORD 1 */
-	union {
-		uint64_t u64;
-		struct {
-			/* CPT HW swaps each 8B word implicitly */
-			uint16_t frag_size0;
-			uint16_t frag_size1;
-			uint16_t frag_size2;
-			uint16_t frag_size3;
-		};
-	} w1;
+		/* WORD 1 */
+		union {
+			uint64_t u64;
+			struct {
+				/* CPT HW swaps each 8B word implicitly */
+				uint16_t frag_size3;
+				uint16_t frag_size2;
+				uint16_t frag_size1;
+				uint16_t frag_size0;
+			};
+		} w1;
+	} s;
+
+	struct cpt_cn10k_frag_info_s {
+		/* WORD 0 */
+		union {
+			uint64_t u64;
+			struct {
+				/* CPT HW swaps each 8B word implicitly */
+				union cpt_frag_info f0;
+				union cpt_frag_info f1;
+				union cpt_frag_info f2;
+				union cpt_frag_info f3;
+			};
+		} w0;
+
+		/* WORD 1 */
+		union {
+			uint64_t u64;
+			struct {
+				/* CPT HW swaps each 8B word implicitly */
+				uint16_t frag_size0;
+				uint16_t frag_size1;
+				uint16_t frag_size2;
+				uint16_t frag_size3;
+			};
+		} w1;
+	} cn10k;
+
+	uint64_t u64[2];
 };
 
 /* CPT rxc pointer info structure */
@@ -591,29 +621,56 @@ struct cpt_rxc_ptr_info_s {
 };
 
 /* CPT rxc scatter/gather subdescriptor structure */
-struct cpt_rxc_sg_s {
-	/* WORD 0 */
-	union {
-		uint64_t u64;
-		struct {
-			uint16_t seg1_size;
-			uint16_t seg2_size;
-			uint16_t seg3_size;
-			uint16_t segs : 2;
-			uint16_t nxt_fst_frag : 3;
-			uint16_t blk_sz : 4;
-			uint16_t rsvd_63_57 : 7;
-		};
-	} w0;
+union cpt_rxc_sg_u {
+	struct cpt_rxc_sg_s {
+		/* WORD 0 */
+		union {
+			uint64_t u64;
+			struct {
+				uint16_t rsvd_63_57 : 7;
+				uint16_t blk_sz : 4;
+				uint16_t nxt_fst_frag : 3;
+				uint16_t segs : 2;
+				uint16_t seg3_size;
+				uint16_t seg2_size;
+				uint16_t seg1_size;
+			};
+		} w0;
 
-	/* WORD 1 */
-	uint64_t seg1_ptr;
+		/* WORD 1 */
+		uint64_t seg1_ptr;
 
-	/* WORD 2 */
-	uint64_t seg2_ptr;
+		/* WORD 2 */
+		uint64_t seg2_ptr;
+
+		/* WORD 3 */
+		uint64_t seg3_ptr;
+	} s;
+
+	struct cpt_cn10k_rxc_sg_s {
+		/* WORD 0 */
+		union {
+			uint64_t u64;
+			struct {
+				uint16_t seg1_size;
+				uint16_t seg2_size;
+				uint16_t seg3_size;
+				uint16_t segs : 2;
+				uint16_t rsvd_63_50 : 14;
+			};
+		} w0;
+
+		/* WORD 1 */
+		uint64_t seg1_ptr;
+
+		/* WORD 2 */
+		uint64_t seg2_ptr;
+
+		/* WORD 3 */
+		uint64_t seg3_ptr;
+	} cn10k;
 
-	/* WORD 3 */
-	uint64_t seg3_ptr;
+	uint64_t u64[4];
 };
 
 union cpt_fc_write_s {
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index 28aedf088e..3b3e678c20 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -125,7 +125,7 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
 static inline void
 cpt_cn10k_parse_hdr_dump(FILE *file, const struct cpt_cn10k_parse_hdr_s *cpth)
 {
-	struct cpt_frag_info_s *frag_info;
+	struct cpt_cn10k_frag_info_s *frag_info;
 	uint32_t offset;
 	uint64_t *slot;
 
-- 
2.34.1

[PATCH 05/18] common/cnxk: update inline profile ID for cn20k

[Rahul Bhansali]

Update inline IPsec profile ID in nix_spi_to_sa_add mbox
as required by ROC_NPC_SEC_ACTION_ALG4 for cn20k.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/roc_npc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 56e0e05b63..7846913417 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -491,6 +491,7 @@ npc_parse_spi_to_sa_action(struct roc_npc *roc_npc, const struct roc_npc_action
 			   struct roc_npc_flow *flow, uint8_t *has_spi_to_sa_action)
 {
 	const struct roc_npc_sec_action *sec_action;
+	struct roc_nix *roc_nix = roc_npc->roc_nix;
 	struct nix_spi_to_sa_add_req *req;
 	struct nix_spi_to_sa_add_rsp *rsp;
 	struct nix_inl_dev *inl_dev;
@@ -546,6 +547,9 @@ npc_parse_spi_to_sa_action(struct roc_npc *roc_npc, const struct roc_npc_action
 		req->spi_index = plt_be_to_cpu_32(flow->spi_to_sa_info.spi);
 		req->match_id = flow->match_id;
 		req->valid = true;
+		if (roc_model_is_cn20k())
+			req->inline_profile_id =
+				roc_nix_inl_inb_ipsec_profile_id_get(roc_nix, true);
 		rc = mbox_process_msg(mbox, (void *)&rsp);
 		if (rc)
 			return rc;
-- 
2.34.1

[PATCH 06/18] common/cnxk: update inline RQ mask

[Rahul Bhansali]

Inline IPsec RQ mask configuration is modified as per
updates in nix_lf_inline_rq_cfg mbox.
Also adds support of default RQ first skip bytes for
local meta aura case.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h    |  4 +-
 drivers/common/cnxk/roc_nix.h     |  1 +
 drivers/common/cnxk/roc_nix_inl.c | 82 +++++++++++++------------------
 3 files changed, 37 insertions(+), 50 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 7871613d9c..3da85b4d12 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1844,12 +1844,12 @@ struct nix_rq_cpt_field_mask_cfg_req {
 		uint64_t __io rq_ctx_word_mask[RQ_CTX_MASK_MAX];
 		__io struct nix_cn10k_rq_ctx_s rq_mask;
 	};
-	struct nix_lf_rx_ipec_cfg1_req {
+	struct nix_lf_rx_ipsec_cfg1_inline_replay_req {
 		uint32_t __io spb_cpt_aura;
 		uint8_t __io rq_mask_enable;
 		uint8_t __io spb_cpt_sizem1;
 		uint8_t __io spb_cpt_enable;
-	} ipsec_cfg1;
+	} ipsec_cfg1_inline_replay;
 };
 
 struct nix_lso_format_cfg {
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 326decde2b..58f71c10e8 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -590,6 +590,7 @@ struct roc_nix {
 	bool force_tail_drop;
 	bool dis_xqe_drop;
 	bool sq_resize_ena;
+	uint8_t def_first_skip;
 	/* End of input parameters */
 	/* LMT line base for "Per Core Tx LMT line" mode*/
 	uintptr_t lmt_base;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 86bafd5c33..917c2c669a 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -101,10 +101,12 @@ nix_inl_meta_aura_create(struct idev_cfg *idev, struct roc_nix *roc_nix, uint16_
 			nb_bufs += roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);
 
 		/* Override meta buf size from NIX devargs if present */
-		if (roc_nix->meta_buf_sz)
+		if (roc_nix->meta_buf_sz) {
 			buf_sz = roc_nix->meta_buf_sz;
-		else
-			buf_sz = first_skip + NIX_INL_META_SIZE;
+		} else {
+			buf_sz = NIX_INL_META_SIZE;
+			buf_sz += roc_nix->def_first_skip ? roc_nix->def_first_skip : first_skip;
+		}
 
 		/* Create Metapool name */
 		snprintf(mempool_name, sizeof(mempool_name), "NIX_INL_META_POOL_%d",
@@ -304,10 +306,14 @@ nix_inl_global_meta_buffer_validate(struct idev_cfg *idev, struct roc_nix_rq *rq
 static int
 nix_inl_local_meta_buffer_validate(struct roc_nix *roc_nix, struct roc_nix_rq *rq)
 {
+	uint32_t buf_sz = NIX_INL_META_SIZE;
+
+	buf_sz += roc_nix->def_first_skip ? roc_nix->def_first_skip : rq->first_skip;
+
 	/* Validate if we have enough space for meta buffer */
-	if (roc_nix->buf_sz && (rq->first_skip + NIX_INL_META_SIZE > roc_nix->buf_sz)) {
-		plt_err("Meta buffer size %u not sufficient to meet RQ first skip %u",
-			roc_nix->buf_sz, rq->first_skip);
+	if (roc_nix->buf_sz && (buf_sz > roc_nix->buf_sz)) {
+		plt_err("Meta buffer size %u is not sufficient to meet minimum required %u",
+			roc_nix->buf_sz, buf_sz);
 		return -EIO;
 	}
 
@@ -1018,7 +1024,7 @@ roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t max_
 }
 
 static void
-nix_inl_rq_mask_init(struct nix_rq_cpt_field_mask_cfg_req *msk_req)
+nix_inl_rq_mask_init(struct nix_rq_cpt_field_mask_cfg_req *msk_req, uint8_t first_skip)
 {
 	int i;
 
@@ -1041,6 +1047,8 @@ nix_inl_rq_mask_init(struct nix_rq_cpt_field_mask_cfg_req *msk_req)
 	msk_req->rq_set.spb_drop_ena = 0;
 	msk_req->rq_set.xqe_drop_ena = 0;
 	msk_req->rq_set.spb_ena = 1;
+	if (first_skip)
+		msk_req->rq_set.first_skip = first_skip;
 
 	if (!roc_feature_nix_has_second_pass_drop()) {
 		msk_req->rq_set.ena = 1;
@@ -1065,6 +1073,8 @@ nix_inl_rq_mask_init(struct nix_rq_cpt_field_mask_cfg_req *msk_req)
 	msk_req->rq_mask.spb_drop_ena = 0;
 	msk_req->rq_mask.xqe_drop_ena = 0;
 	msk_req->rq_mask.spb_ena = 0;
+	if (first_skip)
+		msk_req->rq_mask.first_skip = 0;
 }
 
 static int
@@ -1087,7 +1097,7 @@ nix_inl_legacy_rq_mask_setup(struct roc_nix *roc_nix, bool enable)
 	if (msk_req == NULL)
 		goto exit;
 
-	nix_inl_rq_mask_init(msk_req);
+	nix_inl_rq_mask_init(msk_req, 0);
 	if (roc_nix->local_meta_aura_ena) {
 		aura_handle = roc_nix->meta_aura_handle;
 		buf_sz = roc_nix->buf_sz;
@@ -1100,10 +1110,10 @@ nix_inl_legacy_rq_mask_setup(struct roc_nix *roc_nix, bool enable)
 		buf_sz = inl_cfg->buf_sz;
 	}
 
-	msk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle);
-	msk_req->ipsec_cfg1.rq_mask_enable = enable;
-	msk_req->ipsec_cfg1.spb_cpt_sizem1 = (buf_sz >> 7) - 1;
-	msk_req->ipsec_cfg1.spb_cpt_enable = enable;
+	msk_req->ipsec_cfg1_inline_replay.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle);
+	msk_req->ipsec_cfg1_inline_replay.rq_mask_enable = enable;
+	msk_req->ipsec_cfg1_inline_replay.spb_cpt_sizem1 = (buf_sz >> 7) - 1;
+	msk_req->ipsec_cfg1_inline_replay.spb_cpt_enable = enable;
 
 	rc = mbox_process(mbox);
 exit:
@@ -1116,10 +1126,8 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
 {
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct nix_rq_cpt_field_mask_cfg_req *msk_req;
-	struct idev_cfg *idev = idev_get_cfg();
-	struct nix_rx_inl_lf_cfg_req *lf_cfg;
-	struct idev_nix_inl_cfg *inl_cfg;
 	uint64_t aura_handle;
+	uint8_t first_skip;
 	struct mbox *mbox;
 	int rc = -ENOSPC;
 	uint64_t buf_sz;
@@ -1133,21 +1141,8 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
 	if (msk_req == NULL)
 		goto exit;
 
-	nix_inl_rq_mask_init(msk_req);
-	rc = mbox_process(mbox);
-	if (rc) {
-		plt_err("Failed to setup NIX Inline RQ mask, rc=%d", rc);
-		goto exit;
-	}
-
-	/* SPB setup */
-	if (!roc_nix->local_meta_aura_ena && !roc_nix->custom_meta_aura_ena)
-		goto exit;
-
-	if (!idev)
-		return -ENOENT;
-
-	inl_cfg = &idev->inl_cfg;
+	first_skip = roc_nix->def_first_skip ? (roc_nix->def_first_skip / 8) : 0;
+	nix_inl_rq_mask_init(msk_req, first_skip);
 
 	if (roc_nix->local_meta_aura_ena) {
 		aura_handle = roc_nix->meta_aura_handle;
@@ -1157,28 +1152,19 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
 			rc = -EINVAL;
 			goto exit;
 		}
-	} else {
-		aura_handle = roc_npa_zero_aura_handle();
-		buf_sz = inl_cfg->buf_sz;
-	}
 
-	/* SPB setup */
-	lf_cfg = mbox_alloc_msg_nix_rx_inl_lf_cfg(mbox);
-	if (lf_cfg == NULL) {
-		rc = -ENOSPC;
-		goto exit;
+		/* SPB setup */
+		msk_req->ipsec_cfg1_inline_replay.spb_cpt_aura =
+			roc_npa_aura_handle_to_aura(aura_handle);
+		msk_req->ipsec_cfg1_inline_replay.rq_mask_enable = enable;
+		msk_req->ipsec_cfg1_inline_replay.spb_cpt_sizem1 = (buf_sz >> 7) - 1;
+		msk_req->ipsec_cfg1_inline_replay.spb_cpt_enable = enable;
 	}
 
-	lf_cfg->rx_inline_sa_base = (uintptr_t)nix->inb_sa_base;
-	lf_cfg->rx_inline_cfg0 = nix->rx_inline_cfg0;
-	lf_cfg->profile_id = nix->ipsec_prof_id;
-	if (enable)
-		lf_cfg->rx_inline_cfg1 =
-			(nix->rx_inline_cfg1 | BIT_ULL(37) | ((buf_sz >> 7) - 1) << 38 |
-			 roc_npa_aura_handle_to_aura(aura_handle) << 44);
-	else
-		lf_cfg->rx_inline_cfg1 = nix->rx_inline_cfg1;
 	rc = mbox_process(mbox);
+	if (rc)
+		plt_err("Failed to setup NIX Inline RQ mask, rc=%d", rc);
+
 exit:
 	mbox_put(mbox);
 	return rc;
-- 
2.34.1

[PATCH 07/18] net/cnxk: avoid security flag for custom inbound SA

[Rahul Bhansali]

Avoid NIX_RX_OFFLOAD_SECURITY_F fast path flag for custom_inb_sa
config.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/net/cnxk/cn20k_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index a7ef1dd386..20be35c0e0 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -35,7 +35,7 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
 	if (!dev->ptype_disable)
 		flags |= NIX_RX_OFFLOAD_PTYPE_F;
 
-	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
+	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && !dev->nix.custom_inb_sa)
 		flags |= NIX_RX_OFFLOAD_SECURITY_F;
 
 	return flags;
-- 
2.34.1

[PATCH 08/18] net/cnxk: add CPT code check for soft expiry

[Rahul Bhansali]

Add CPT ucode 0xF2 check as well for soft expiry handling.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/net/cnxk/cn20k_ethdev_sec.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index baa3423e28..bddc02eb3b 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -464,6 +464,7 @@ cn20k_eth_sec_post_event(struct rte_eth_dev *eth_dev, struct roc_ow_ipsec_outb_s
 			desc.subtype = RTE_ETH_EVENT_IPSEC_SA_BYTE_HARD_EXPIRY;
 		break;
 	case ROC_IE_OW_UCC_SUCCESS_SA_SOFTEXP_FIRST:
+	case ROC_IE_OW_UCC_SUCCESS_SA_SOFTEXP_AGAIN:
 		if (sa->w2.s.life_unit == ROC_IE_OW_SA_LIFE_UNIT_PKTS)
 			desc.subtype = RTE_ETH_EVENT_IPSEC_SA_PKT_EXPIRY;
 		else
-- 
2.34.1

[PATCH 09/18] net/cnxk: skip write SA for cn20k

[Rahul Bhansali]

Skip write SA for cn20k platform.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/net/cnxk/cn20k_ethdev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index 20be35c0e0..7e9e32f80b 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -948,8 +948,8 @@ cn20k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 	/* Register up msg callbacks for PTP information */
 	roc_nix_ptp_info_cb_register(&dev->nix, cn20k_nix_ptp_info_update_cb);
 
-	/* Use WRITE SA for inline IPsec */
-	dev->nix.use_write_sa = true;
+	/* Skip WRITE SA for inline IPsec */
+	dev->nix.use_write_sa = false;
 
 	return 0;
 }
-- 
2.34.1

[PATCH 10/18] net/cnxk: update NIX reassembly fast path

[Rahul Bhansali]

Update NIX reassembly fastpath for cn20k based on
CPT CSR change.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/net/cnxk/cn20k_rx.h | 80 +++++++++++++++++++++++++++++--------
 1 file changed, 64 insertions(+), 16 deletions(-)

diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index 1944e507b0..ea8675be00 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -191,15 +191,13 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const rte_iova_t *iova_li
 	}
 
 	/* Remove the frag header by moving header 8 bytes forward */
-	ipv6_hdr->payload_len = rte_cpu_to_be_16(rlen - 8 - sizeof(struct rte_ipv6_hdr));
+	ipv6_hdr->payload_len = rte_cpu_to_be_16(rlen - sizeof(struct rte_ipv6_hdr));
 
 	/* tot_len is sum of all IP header's length before fragment header */
 	rte_memcpy(rte_pktmbuf_mtod_offset(head, void *, 8), rte_pktmbuf_mtod(head, void *),
 		   lc_off + tot_len);
 
-	head->data_len -= 8;
 	head->data_off += 8;
-	head->pkt_len -= 8;
 }
 
 static __rte_always_inline uint64_t
@@ -300,6 +298,7 @@ nix_update_match_id(const uint16_t match_id, uint64_t ol_flags, struct rte_mbuf
 	return ol_flags;
 }
 
+#if defined(RTE_ARCH_ARM64)
 static __rte_always_inline void
 nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint64_t rearm,
 		    uintptr_t cpth, uintptr_t sa_base, const uint64_t buf_sz, const uint16_t flags)
@@ -314,6 +313,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 	uint16_t rlen = hdr->w3.rlen;
 	const rte_iova_t *iova_list;
 	uint8_t sg_cnt = 1, nb_segs;
+	uint16x4_t fsz, sg_swap;
 	uint16_t later_skip = 0;
 	bool reas_fail = false;
 	const rte_iova_t *eol;
@@ -321,6 +321,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 	uint8_t ts_rx_off;
 	int dyn_off = 0;
 	uint16_t sg_len;
+	uint16_t l4_off;
 	int64_t len;
 	uintptr_t p;
 
@@ -341,7 +342,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		finfo = (const struct cpt_frag_info_s *)sg_base;
 		sg_base += num_frags ? (num_frags > 4 ? 32 : 16) : 0;
 		sg = *(uint64_t *)sg_base;
-		nb_segs = (sg >> 48) & 0x3;
+		nb_segs = (sg >> 14) & 0x3;
 		iova_list = (rte_iova_t *)(sg_base);
 		eol = iova_list + (hdr->w4.gthr_size << 2);
 		iova_list += 2;
@@ -357,11 +358,22 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 			if (hdr->w0.reas_sts ||
 			    (hdr->w0.err_sum && !roc_ie_ow_ucc_is_success(hdr->w3.uc_ccode))) {
 				reas_fail = true;
-				nxt_frag = (sg >> 51) & 0x3;
-				fsz_w1 = finfo->w1.u64 >> 16;
+				nxt_frag = (sg >> 11) & 0x3;
+				nxt_frag = ((nxt_frag << 1) | (nxt_frag >> 1)) & 0x3;
+
+				/* Reverse the order of fragment sizes */
+				fsz = vreinterpret_u16_u64(vdup_n_u64(finfo->w1.u64));
+				fsz = vrev64_u16(fsz);
+				fsz_w1 = vget_lane_u64(vreinterpret_u64_u16(fsz), 0) >> 16;
 				finfo++;
+				l4_off = ((cq_w5 >> 24) & 0xFF) - (cq_w5 & 0xFF);
 			}
 		}
+
+		/* sg byte swap */
+		sg_swap = vreinterpret_u16_u64(vdup_n_u64(sg));
+		sg_swap = vrev64_u16(sg_swap);
+		sg = vget_lane_u64(vreinterpret_u64_u16(sg_swap), 0);
 	} else {
 		sg = *(const uint64_t *)(rx + 1);
 		nb_segs = (sg >> 48) & 0x3;
@@ -376,8 +388,10 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		iova_list = ((const rte_iova_t *)(rx + 1)) + 2;
 	}
 
-	/* Update data len as per the segment size */
 	sg_len = sg & 0xFFFF;
+	sg = sg >> 16;
+
+	/* Update data len as per the segment size */
 	mbuf->data_len = sg_len;
 	mbuf->nb_segs = nb_segs;
 	head = mbuf;
@@ -387,7 +401,6 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		nix_sec_reass_first_frag_update(mbuf, iova_list - 1, cpth, cq_w1, cq_w5, rlen);
 
 	len -= sg_len;
-	sg = sg >> 16;
 	nb_segs--;
 
 	later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf;
@@ -404,6 +417,9 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 
 		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 
+		sg_len = sg & 0xFFFF;
+		sg = sg >> 16;
+
 		/* Process reassembly failure case */
 		if ((flags & NIX_RX_REAS_F) && unlikely(reas_fail && (nxt_frag & 1))) {
 			head->ol_flags |=
@@ -419,20 +435,25 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 			last_mbuf->next = NULL;
 			head = mbuf;
 			len = fsz_w1 & 0xFFFF;
-			head->pkt_len = len - ts_rx_off;
+			head->pkt_len = l4_off + len - ts_rx_off;
 			head->nb_segs = sg_cnt;
+			/* later frag size update*/
+			sg_len += l4_off;
 			data_off = rearm & 0xFFFF;
 			sg_cnt = 0;
 			nxt_frag = nxt_frag >> 1;
 			fsz_w1 = fsz_w1 >> 16;
-			if (--num_frags == 4)
-				fsz_w1 = finfo->w1.u64;
+			if (--num_frags == 4) {
+				/* Reverse the order of fragment sizes */
+				fsz = vreinterpret_u16_u64(vdup_n_u64(finfo->w1.u64));
+				fsz = vrev64_u16(fsz);
+				fsz_w1 = vget_lane_u64(vreinterpret_u64_u16(fsz), 0);
+			}
 		}
 
 		if ((flags & NIX_RX_REAS_F) && num_frags && !reas_fail)
 			data_off = *iova_list - (uint64_t)mbuf->buf_addr;
 
-		sg_len = sg & 0xFFFF;
 		if ((flags & NIX_RX_OFFLOAD_SECURITY_F) && !(flags & NIX_RX_REAS_F)) {
 			/* Adjust last mbuf data length with negative offset for
 			 * security pkts if needed.
@@ -443,7 +464,6 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		}
 
 		mbuf->data_len = sg_len;
-		sg = sg >> 16;
 		p = (uintptr_t)&mbuf->rearm_data;
 		*(uint64_t *)p = (rearm & ~0xFFFF) | data_off;
 
@@ -454,11 +474,25 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 
 		if (!nb_segs && (iova_list + 1 < eol)) {
 			sg = *(const uint64_t *)(iova_list);
-			nb_segs = (sg >> 48) & 0x3;
+
+			if ((flags & NIX_RX_SEC_REASSEMBLY_F) && (cq_w1 & BIT(11))) {
+				nb_segs = (sg >> 14) & 0x3;
+
+				if (unlikely(reas_fail)) {
+					nxt_frag = (sg >> 11) & 7;
+					nxt_frag = ((nxt_frag << 2) | (nxt_frag & 2) |
+						    (nxt_frag >> 2)) & 0x7;
+				}
+
+				sg_swap = vreinterpret_u16_u64(vdup_n_u64(sg));
+				sg_swap = vrev64_u16(sg_swap);
+				sg = vget_lane_u64(vreinterpret_u64_u16(sg_swap), 0);
+			} else {
+				nb_segs = (sg >> 48) & 0x3;
+			}
+
 			iova_list++;
 			head->nb_segs += nb_segs;
-			if ((flags & NIX_RX_REAS_F) && reas_fail)
-				nxt_frag = (sg >> 50) & 0x7;
 		}
 	}
 
@@ -468,6 +502,20 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		cnxk_ip_reassembly_dynfield(head, dyn_off)->nb_frags = 0;
 	}
 }
+#else
+static __rte_always_inline void
+nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint64_t rearm,
+		    uintptr_t cpth, uintptr_t sa_base, const uint64_t buf_sz, const uint16_t flags)
+{
+	RTE_SET_USED(rx);
+	RTE_SET_USED(mbuf);
+	RTE_SET_USED(rearm);
+	RTE_SET_USED(cpth);
+	RTE_SET_USED(sa_base);
+	RTE_SET_USED(buf_sz);
+	RTE_SET_USED(flags);
+}
+#endif
 
 static __rte_always_inline void
 cn20k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, struct rte_mbuf *mbuf,
-- 
2.34.1

[PATCH 11/18] net/cnxk: update aura batch free

[Rahul Bhansali]

From: Nithin Dabilpuram <ndabilpuram@marvell.com>

Update aura batch free for cn20k fastpath

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn20k_rx.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index ea8675be00..eed8d59a14 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -112,7 +112,7 @@ nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff, uintptr_t aur
 
 	/* Update aura handle */
 	*(uint64_t *)laddr =
-		(((uint64_t)(loff & 0x1) << 32) | roc_npa_aura_handle_to_aura(aura_handle));
+		(((uint64_t)(loff & 0x3) << 32) | roc_npa_aura_handle_to_aura(aura_handle));
 
 	pa |= ((uint64_t)(loff >> 1) << 4);
 	roc_lmt_submit_steorl(lmt_id, pa);
@@ -1561,7 +1561,7 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 			/* Check if lmtline border is crossed and adjust lnum */
 			if (loff > 15) {
 				/* Update aura handle */
-				*(uint64_t *)(laddr - 8) = (((uint64_t)(15 & 0x1) << 32) |
+				*(uint64_t *)(laddr - 8) = (((uint64_t)(15 & 0x3) << 32) |
 							    roc_npa_aura_handle_to_aura(meta_aura));
 				loff = loff - 15;
 				shft += 3;
@@ -1582,7 +1582,7 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				uint64_t data = BIT_ULL(48) - 1;
 
 				/* Update aura handle */
-				*(uint64_t *)(laddr - 8) = (((uint64_t)(loff & 0x1) << 32) |
+				*(uint64_t *)(laddr - 8) = (((uint64_t)(loff & 0x3) << 32) |
 							    roc_npa_aura_handle_to_aura(meta_aura));
 
 				data = (data & ~(0x7UL << shft)) | (((uint64_t)loff >> 1) << shft);
@@ -1605,7 +1605,7 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 
 		/* Update aura handle */
 		*(uint64_t *)(laddr - 8) =
-			(((uint64_t)(loff & 0x1) << 32) | roc_npa_aura_handle_to_aura(meta_aura));
+			(((uint64_t)(loff & 0x3) << 32) | roc_npa_aura_handle_to_aura(meta_aura));
 
 		data = (data & ~(0x7UL << shft)) | (((uint64_t)loff >> 1) << shft);
 
-- 
2.34.1

[PATCH 12/18] net/cnxk: update fastpath function for OOP

[Rahul Bhansali]

Update fastpath functions to support non inplace (OOP).

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/net/cnxk/cn20k_ethdev_sec.c |  22 +++--
 drivers/net/cnxk/cn20k_rx.h         | 119 ++++++++++++++++++++++++----
 2 files changed, 118 insertions(+), 23 deletions(-)

diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index bddc02eb3b..c6a51f99f5 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -9,6 +9,7 @@
 #include <rte_security_driver.h>
 
 #include <cn20k_ethdev.h>
+#include <cn20k_rx.h>
 #include <cnxk_security.h>
 #include <roc_priv.h>
 
@@ -810,10 +811,6 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
 			inb_sa_dptr->w0.s.count_mib_pkts = 1;
 		}
 
-		/* Enable out-of-place processing */
-		if (ipsec->options.ingress_oop)
-			inb_sa_dptr->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_FULL;
-
 		/* Prepare session priv */
 		sess_priv.inb_sa = 1;
 		sess_priv.sa_idx = ipsec->spi & spi_mask;
@@ -843,6 +840,13 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
 		if (ipsec->options.ingress_oop)
 			dev->inb.nb_oop++;
 
+		/* Update function pointer to handle OOP sessions */
+		if (dev->inb.nb_oop && !(dev->rx_offload_flags & NIX_RX_REAS_F)) {
+			dev->rx_offload_flags |= NIX_RX_REAS_F;
+			cn20k_eth_set_rx_function(eth_dev);
+			if (cnxk_ethdev_rx_offload_cb)
+				cnxk_ethdev_rx_offload_cb(eth_dev->data->port_id, NIX_RX_REAS_F);
+		}
 	} else {
 		struct roc_ow_ipsec_outb_sa *outb_sa, *outb_sa_dptr;
 		struct cn20k_outb_priv_data *outb_priv;
@@ -986,6 +990,12 @@ cn20k_eth_sec_session_destroy(void *device, struct rte_security_session *sess)
 		if (eth_sec->inb_oop)
 			dev->inb.nb_oop--;
 
+		/* Clear offload flags if was used by OOP */
+		if (!dev->inb.nb_oop && !dev->inb.reass_en &&
+		    dev->rx_offload_flags & NIX_RX_REAS_F) {
+			dev->rx_offload_flags &= ~NIX_RX_REAS_F;
+			cn20k_eth_set_rx_function(eth_dev);
+		}
 	} else {
 		/* Disable SA */
 		sa_dptr = dev->outb.sa_dptr;
@@ -1064,10 +1074,6 @@ cn20k_eth_sec_session_update(void *device, struct rte_security_session *sess,
 			inb_sa_dptr->w0.s.count_mib_pkts = 1;
 		}
 
-		/* Enable out-of-place processing */
-		if (ipsec->options.ingress_oop)
-			inb_sa_dptr->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_FULL;
-
 		rc = roc_nix_inl_ctx_write(&dev->nix, inb_sa_dptr, eth_sec->sa, eth_sec->inb,
 					   sizeof(struct roc_ow_ipsec_inb_sa));
 		if (rc)
diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index eed8d59a14..83c222c53c 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -200,6 +200,38 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const rte_iova_t *iova_li
 	head->data_off += 8;
 }
 
+static __rte_always_inline struct rte_mbuf *
+nix_sec_oop_process(uintptr_t cpth, uint64_t buf_sz)
+{
+	const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)cpth;
+	uint32_t offset = hdr->w2.ptr_offset;
+	struct rte_mbuf *inner, *mbuf;
+	union nix_rx_parse_u *rx;
+	rte_iova_t *iova_list;
+	uint64_t addr;
+
+	iova_list = (rte_iova_t *)(cpth + (offset ? (offset << 5) : 256)) + 1;
+	addr = *iova_list;
+	offset = addr % (buf_sz & 0xFFFFFFFF);
+	mbuf = (struct rte_mbuf *)(addr - offset + (buf_sz >> 32));
+
+	rx = (union nix_rx_parse_u *)(((uintptr_t)(mbuf + 1)) + 8);
+	mbuf->pkt_len = rx->pkt_lenm1 + 1;
+	mbuf->data_len = rx->pkt_lenm1 + 1;
+	mbuf->data_off = addr - (uint64_t)mbuf->buf_addr;
+
+	/* Pointers will be alternate encrypted-decrypted in gather list */
+	iova_list++;
+	addr = *iova_list;
+	inner = (struct rte_mbuf *)(addr - offset + (buf_sz >> 32));
+
+	/* Mark original mbuf as get */
+	RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&mbuf, 1, 1);
+
+	*rte_security_oop_dynfield(inner) = mbuf;
+	return inner;
+}
+
 static __rte_always_inline uint64_t
 nix_sec_meta_to_mbuf_sc(uint64_t cq_w5, uint64_t cpth, const uint64_t sa_base,
 			struct rte_mbuf *mbuf, uint16_t *len, uint64_t *mbuf_init,
@@ -318,10 +350,11 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 	bool reas_fail = false;
 	const rte_iova_t *eol;
 	uint16_t data_off = 0;
+	bool is_oop = false;
+	uint16_t l4_off = 0;
 	uint8_t ts_rx_off;
 	int dyn_off = 0;
 	uint16_t sg_len;
-	uint16_t l4_off;
 	int64_t len;
 	uintptr_t p;
 
@@ -332,7 +365,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		uint64_t sg_base;
 
 		/* Check if there are no SG's */
-		if (!hdr->w4.gthr_size && ((flags & NIX_RX_REAS_F) || !hdr->w4.sctr_size))
+		if (!hdr->w4.gthr_size)
 			return;
 
 		cq_w5 = *((const uint64_t *)rx + 4);
@@ -342,7 +375,12 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		finfo = (const struct cpt_frag_info_s *)sg_base;
 		sg_base += num_frags ? (num_frags > 4 ? 32 : 16) : 0;
 		sg = *(uint64_t *)sg_base;
+
+		is_oop = (hdr->w4.l4_chksum_type == 0) && (hdr->w4.l4_chksum == 1);
 		nb_segs = (sg >> 14) & 0x3;
+		if (is_oop && nb_segs <= 2)
+			return;
+
 		iova_list = (rte_iova_t *)(sg_base);
 		eol = iova_list + (hdr->w4.gthr_size << 2);
 		iova_list += 2;
@@ -374,6 +412,12 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		sg_swap = vreinterpret_u16_u64(vdup_n_u64(sg));
 		sg_swap = vrev64_u16(sg_swap);
 		sg = vget_lane_u64(vreinterpret_u64_u16(sg_swap), 0);
+
+		/* For Non inplace, first SG pointer will be original encrypted,
+		 * whereas input mbuf is decrypted one. So need to update mbuf pointer
+		 * in order to process SG list accordingly.
+		 */
+		mbuf = is_oop ? *rte_security_oop_dynfield(mbuf) : mbuf;
 	} else {
 		sg = *(const uint64_t *)(rx + 1);
 		nb_segs = (sg >> 48) & 0x3;
@@ -397,17 +441,17 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 	head = mbuf;
 
 	/* Update IP header */
-	if ((flags & NIX_RX_REAS_F) && num_frags && !reas_fail)
+	if ((flags & NIX_RX_REAS_F) && num_frags && !reas_fail && !is_oop)
 		nix_sec_reass_first_frag_update(mbuf, iova_list - 1, cpth, cq_w1, cq_w5, rlen);
 
-	len -= sg_len;
+	len -= is_oop ? 0 : sg_len;
 	nb_segs--;
 
 	later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf;
 
 	while (nb_segs) {
 		last_mbuf = mbuf;
-		if ((flags & NIX_RX_REAS_F) && num_frags) {
+		if ((flags & NIX_RX_REAS_F) && (num_frags || is_oop)) {
 			offset = (*iova_list) % (buf_sz & 0xFFFFFFFF);
 			mbuf->next = (struct rte_mbuf *)((*iova_list) - offset + (buf_sz >> 32));
 		} else {
@@ -451,12 +495,14 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 			}
 		}
 
-		if ((flags & NIX_RX_REAS_F) && num_frags && !reas_fail)
+		if ((flags & NIX_RX_REAS_F) && ((num_frags && !reas_fail) || is_oop))
 			data_off = *iova_list - (uint64_t)mbuf->buf_addr;
 
-		if ((flags & NIX_RX_OFFLOAD_SECURITY_F) && !(flags & NIX_RX_REAS_F)) {
+		if (((flags & NIX_RX_OFFLOAD_SECURITY_F) && !(flags & NIX_RX_REAS_F)) ||
+		    (is_oop && (sg_cnt % 2))) {
 			/* Adjust last mbuf data length with negative offset for
 			 * security pkts if needed.
+			 * For OOP, will correct mbuf length of decrypted pkt.
 			 */
 			len -= sg_len;
 			sg_len = (len > 0) ? sg_len : (sg_len + len);
@@ -496,6 +542,29 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		}
 	}
 
+	if (unlikely(is_oop)) {
+		struct rte_mbuf *o_mbuf;
+
+		/* mbuf chain will have all pointers of encrypted + decrypted
+		 * alternatively. So will need to sort it.
+		 */
+		mbuf = head;
+		o_mbuf = head->next;
+		nb_segs = head->nb_segs;
+		mbuf->nb_segs = nb_segs / 2;
+		o_mbuf->nb_segs = nb_segs / 2;
+		nb_segs -= 2;
+		while (unlikely(nb_segs && (nb_segs % 2 == 0))) {
+			mbuf->next = o_mbuf->next;
+			o_mbuf->next = o_mbuf->next->next;
+			mbuf = mbuf->next;
+			o_mbuf = o_mbuf->next;
+			nb_segs -= 2;
+		}
+		mbuf->next = NULL;
+		o_mbuf->next = NULL;
+	}
+
 	/* Update for last failure fragment */
 	if ((flags & NIX_RX_REAS_F) && reas_fail) {
 		cnxk_ip_reassembly_dynfield(head, dyn_off)->next_frag = NULL;
@@ -648,6 +717,8 @@ cn20k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, co
 	uintptr_t cpth = 0;
 	uint16_t lmt_id;
 	uint64_t laddr;
+	uint64_t w4;
+	bool is_oop;
 
 	nb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);
 
@@ -685,7 +756,12 @@ cn20k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, co
 				 */
 				*(uint64_t *)(laddr + (loff << 3)) = (uint64_t)mbuf;
 				loff = loff + 1;
-				mbuf = (struct rte_mbuf *)(*(uint64_t *)(cpth + 8) - m_sz);
+				w4 = *(uint64_t *)(cpth + 32);
+				is_oop = !((w4 >> 32) & 0x3) && ((w4 & 0xffffffff) == 1);
+				if ((flags & NIX_RX_REAS_F) && is_oop)
+					mbuf = nix_sec_oop_process(cpth, buf_sz);
+				else
+					mbuf = (struct rte_mbuf *)(*(uint64_t *)(cpth + 8) - m_sz);
 
 				/* Mark inner mbuf as get */
 				RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
@@ -815,11 +891,21 @@ cn20k_nix_flush_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pk
 
 static __rte_always_inline void
 nix_sec_meta_to_mbuf(uintptr_t inb_sa, uintptr_t cpth, struct rte_mbuf **inner, uint64_t *ol_flags,
-		     const uint16_t flags, uint64x2_t *rearm)
+		     const uint16_t flags, uint64x2_t *rearm, uint64_t buf_sz)
 {
 	const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)cpth;
-	struct rte_mbuf *inner_m = inner[0];
 	struct cn20k_inb_priv_data *inb_priv;
+	struct rte_mbuf *inner_m;
+	uint64_t w4;
+	bool is_oop;
+
+	w4 = *(uint64_t *)(cpth + 32);
+	is_oop = !((w4 >> 32) & 0x3) && ((w4 & 0xffffffff) == 1);
+
+	if ((flags & NIX_RX_REAS_F) && is_oop)
+		inner[0] = nix_sec_oop_process(cpth, buf_sz);
+
+	inner_m = inner[0];
 
 	/* Clear checksum flags */
 	*ol_flags &= ~(RTE_MBUF_F_RX_L4_CKSUM_MASK | RTE_MBUF_F_RX_IP_CKSUM_MASK);
@@ -1328,7 +1414,8 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				f0 = vsetq_lane_u16(len, f0, 2);
 				f0 = vsetq_lane_u16(len, f0, 4);
 
-				nix_sec_meta_to_mbuf(sa, cpth0, &mbuf0, &ol_flags0, flags, &rearm0);
+				nix_sec_meta_to_mbuf(sa, cpth0, &mbuf0, &ol_flags0, flags, &rearm0,
+						     buf_sz);
 				mbuf01 = vsetq_lane_u64((uintptr_t)mbuf0, mbuf01, 0);
 				code = vget_lane_u8(ucc, 1);
 				ol_flags0 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :
@@ -1344,7 +1431,6 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 
 				cpth1 = (uintptr_t)mbuf1 + d_off;
 
-				/* Free meta to aura */
 				NIX_PUSH_META_TO_FREE(mbuf1, laddr, &loff);
 				mbuf1 = (struct rte_mbuf *)wqe;
 
@@ -1352,7 +1438,8 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				f1 = vsetq_lane_u16(len, f1, 2);
 				f1 = vsetq_lane_u16(len, f1, 4);
 
-				nix_sec_meta_to_mbuf(sa, cpth1, &mbuf1, &ol_flags1, flags, &rearm1);
+				nix_sec_meta_to_mbuf(sa, cpth1, &mbuf1, &ol_flags1, flags, &rearm1,
+						     buf_sz);
 				mbuf01 = vsetq_lane_u64((uintptr_t)mbuf1, mbuf01, 1);
 				code = vget_lane_u8(ucc, 3);
 				ol_flags1 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :
@@ -1375,7 +1462,8 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				f2 = vsetq_lane_u16(len, f2, 2);
 				f2 = vsetq_lane_u16(len, f2, 4);
 
-				nix_sec_meta_to_mbuf(sa, cpth2, &mbuf2, &ol_flags2, flags, &rearm2);
+				nix_sec_meta_to_mbuf(sa, cpth2, &mbuf2, &ol_flags2, flags, &rearm2,
+						     buf_sz);
 				mbuf23 = vsetq_lane_u64((uintptr_t)mbuf2, mbuf23, 0);
 				code = vget_lane_u8(ucc, 5);
 				ol_flags2 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :
@@ -1398,7 +1486,8 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				f3 = vsetq_lane_u16(len, f3, 2);
 				f3 = vsetq_lane_u16(len, f3, 4);
 
-				nix_sec_meta_to_mbuf(sa, cpth3, &mbuf3, &ol_flags3, flags, &rearm3);
+				nix_sec_meta_to_mbuf(sa, cpth3, &mbuf3, &ol_flags3, flags, &rearm3,
+						     buf_sz);
 				mbuf23 = vsetq_lane_u64((uintptr_t)mbuf3, mbuf23, 1);
 				code = vget_lane_u8(ucc, 7);
 				ol_flags3 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :
-- 
2.34.1

[PATCH 13/18] event/cnxk: update fastpath function for OOP

[Rahul Bhansali]

Update fastpath functions to support non inplace (OOP).

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/event/cnxk/cn20k_eventdev.c | 18 +++++++++++++++++
 drivers/event/cnxk/cn20k_worker.h   | 30 +++++++++++++++++++++--------
 2 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c
index 1c5d927239..ff3aaac16a 100644
--- a/drivers/event/cnxk/cn20k_eventdev.c
+++ b/drivers/event/cnxk/cn20k_eventdev.c
@@ -710,6 +710,23 @@ cn20k_sso_tstamp_hdl_update(uint16_t port_id, uint16_t flags, bool ptp_en)
 	eventdev_fops_tstamp_update(event_dev);
 }
 
+static void
+cn20k_sso_rx_offload_cb(uint16_t port_id, uint64_t flags)
+{
+	struct rte_eth_dev *dev = &rte_eth_devices[port_id];
+	struct cnxk_eth_dev *cnxk_eth_dev = dev->data->dev_private;
+	struct rte_eventdev *event_dev = cnxk_eth_dev->evdev_priv;
+	struct cnxk_sso_evdev *evdev;
+
+	if (event_dev == NULL)
+		return;
+
+	evdev = cnxk_sso_pmd_priv(event_dev);
+	evdev->rx_offloads |= flags;
+	cn20k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
+	eventdev_fops_tstamp_update(event_dev);
+}
+
 static int
 cn20k_sso_rxq_enable(struct cnxk_eth_dev *cnxk_eth_dev, uint16_t rq_id, uint16_t port_id,
 		     const struct rte_event_eth_rx_adapter_queue_conf *queue_conf, int agq)
@@ -1241,6 +1258,7 @@ cn20k_sso_init(struct rte_eventdev *event_dev)
 		return rc;
 	}
 
+	cnxk_ethdev_rx_offload_cb_register(cn20k_sso_rx_offload_cb);
 	event_dev->dev_ops = &cn20k_sso_dev_ops;
 	/* For secondary processes, the primary has done all the work */
 	if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
diff --git a/drivers/event/cnxk/cn20k_worker.h b/drivers/event/cnxk/cn20k_worker.h
index 608f93dcd4..6442113e09 100644
--- a/drivers/event/cnxk/cn20k_worker.h
+++ b/drivers/event/cnxk/cn20k_worker.h
@@ -18,15 +18,11 @@
 static __rte_always_inline void
 cn20k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf, uint8_t port_id, const uint32_t tag,
 		  const uint32_t flags, const void *const lookup_mem, uintptr_t cpth,
-		  uintptr_t sa_base)
+		  uintptr_t sa_base, uint64_t buf_sz)
 {
 	const uint64_t mbuf_init =
 		0x100010000ULL | RTE_PKTMBUF_HEADROOM | (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 	struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
-	uint64_t buf_sz = 0;
-
-	if (flags & NIX_RX_REAS_F)
-		buf_sz = cnxk_nix_inl_bufsize_get(port_id, lookup_mem);
 
 	cn20k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag, (struct rte_mbuf *)mbuf, lookup_mem,
 			      mbuf_init | ((uint64_t)port_id) << 48, cpth, sa_base, buf_sz, flags);
@@ -66,6 +62,8 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, struc
 	uint64_t buf_sz = 0;
 	uintptr_t cpth = 0;
 	uint8_t loff = 0;
+	uint64_t w4;
+	bool is_oop;
 	int i;
 
 	mbuf_init |= ((uint64_t)port_id) << 48;
@@ -136,7 +134,12 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, struc
 				 */
 				*(uint64_t *)(laddr + (loff << 3)) = (uint64_t)mbuf;
 				loff = loff + 1;
-				mbuf = (struct rte_mbuf *)(*(uint64_t *)(cpth + 8) - m_sz);
+				w4 = *(uint64_t *)(cpth + 32);
+				is_oop = !((w4 >> 32) & 0x3) && ((w4 & 0xffffffff) == 1);
+				if ((flags & NIX_RX_REAS_F) && is_oop)
+					mbuf = nix_sec_oop_process(cpth, buf_sz);
+				else
+					mbuf = (struct rte_mbuf *)(*(uint64_t *)(cpth + 8) - m_sz);
 				/* Mark inner mbuf as get */
 				RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 			}
@@ -176,6 +179,7 @@ cn20k_sso_hws_post_process(struct cn20k_sso_hws *ws, uint64_t *u64, const uint32
 		u64[1] = cn20k_cpt_crypto_adapter_vector_dequeue(u64[1]);
 	} else if (CNXK_EVENT_TYPE_FROM_TAG(u64[0]) == RTE_EVENT_TYPE_ETHDEV) {
 		uint8_t port = CNXK_SUB_EVENT_FROM_TAG(u64[0]);
+		uint64_t buf_sz = 0;
 		uintptr_t cpth = 0;
 		uint64_t mbuf;
 
@@ -194,6 +198,8 @@ cn20k_sso_hws_post_process(struct cn20k_sso_hws *ws, uint64_t *u64, const uint32
 			uint8_t loff = 0;
 			uint16_t d_off;
 			uint64_t cq_w1;
+			uint64_t w4;
+			bool is_oop;
 
 			m = (struct rte_mbuf *)mbuf;
 			d_off = (*(uint64_t *)(u64[1] + 72)) - (uintptr_t)m;
@@ -210,12 +216,20 @@ cn20k_sso_hws_post_process(struct cn20k_sso_hws *ws, uint64_t *u64, const uint32
 				/* Mark meta mbuf as put */
 				RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);
 
+				if (flags & NIX_RX_REAS_F)
+					buf_sz = cnxk_nix_inl_bufsize_get(port, lookup_mem);
 				/* Store meta in lmtline to free
 				 * Assume all meta's from same aura.
 				 */
 				*(uint64_t *)((uintptr_t)&iova + (loff << 3)) = (uint64_t)m;
 				loff = loff + 1;
-				mbuf = (uint64_t)(*(uint64_t *)(cpth + 8) - m_sz);
+				w4 = *(uint64_t *)(cpth + 32);
+				is_oop = !((w4 >> 32) & 0x3) && ((w4 & 0xffffffff) == 1);
+				if ((flags & NIX_RX_REAS_F) && is_oop)
+					mbuf = (uint64_t)nix_sec_oop_process(cpth, buf_sz);
+				else
+					mbuf = (uint64_t)(*(uint64_t *)(cpth + 8) - m_sz);
+
 				/* Mark inner mbuf as get */
 				RTE_MEMPOOL_CHECK_COOKIES(((struct rte_mbuf *)mbuf)->pool,
 							  (void **)&mbuf, 1, 1);
@@ -225,7 +239,7 @@ cn20k_sso_hws_post_process(struct cn20k_sso_hws *ws, uint64_t *u64, const uint32
 
 		u64[0] = CNXK_CLR_SUB_EVENT(u64[0]);
 		cn20k_wqe_to_mbuf(u64[1], mbuf, port, u64[0] & 0xFFFFF, flags, ws->lookup_mem, cpth,
-				  sa_base);
+				  sa_base, buf_sz);
 		if (flags & NIX_RX_OFFLOAD_TSTAMP_F)
 			cn20k_sso_process_tstamp(u64[1], mbuf, ws->tstamp[port]);
 		u64[1] = mbuf;
-- 
2.34.1

[PATCH 14/18] common/cnxk: flow rule config for non-inplace

[Rahul Bhansali]

Adds flow rule for non-inplace security action
configuration

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/roc_npc.c | 13 ++++++++++++-
 drivers/common/cnxk/roc_npc.h |  3 +++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 7846913417..acf0007e05 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -613,10 +613,12 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 	const struct roc_npc_action_mark *act_mark;
 	const struct roc_npc_action_meter *act_mtr;
 	const struct roc_npc_action_queue *act_q;
+	const struct roc_npc_sec_action *sec_act;
 	const struct roc_npc_action_vf *vf_act;
 	uint8_t has_spi_to_sa_act = 0;
 	int sel_act, req_act = 0;
 	uint16_t pf_func, vf_id;
+	bool is_non_inp = false;
 	int errcode = 0;
 	int mark = 0;
 	int rq = 0;
@@ -704,6 +706,15 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 			 *  session_protocol ==
 			 *    NPC_SECURITY_PROTOCOL_IPSEC
 			 */
+
+			if (!actions->no_sec_action) {
+				sec_act = (const struct roc_npc_sec_action *)actions->conf;
+				sec_action = actions;
+				is_non_inp = sec_act ? sec_act->is_non_inp : false;
+			} else {
+				is_non_inp = actions->is_non_inp;
+			}
+
 			req_act |= ROC_NPC_ACTION_TYPE_SEC;
 			rq = 0;
 			roc_nix = roc_npc->roc_nix;
@@ -724,7 +735,6 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 
 			if (roc_nix_inl_dev_is_probed())
 				flow->is_inline_dev = 1;
-			sec_action = actions;
 			break;
 		case ROC_NPC_ACTION_TYPE_VLAN_STRIP:
 			req_act |= ROC_NPC_ACTION_TYPE_VLAN_STRIP;
@@ -931,6 +941,7 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 			flow->npc_action |= (uint64_t)rq << 20;
 			flow->npc_action2 =
 				roc_nix_inl_inb_ipsec_profile_id_get(roc_nix, true) << 8;
+			flow->npc_action2 |= is_non_inp ? (1ULL << 15) : 0;
 		} else {
 			flow->npc_action = NIX_RX_ACTIONOP_UCAST_IPSEC;
 			flow->npc_action |= (uint64_t)rq << 20;
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index b7565806c0..62385e4481 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -204,6 +204,8 @@ struct roc_npc_action {
 	enum roc_npc_action_type type; /**< Action type. */
 	const void *conf;	       /**< Pointer to action configuration object. */
 	uint16_t rss_repte_pf_func;    /**< Per flow tmp var for rss representee pffunc */
+	bool is_non_inp;	       /**< Non inplace config */
+	bool no_sec_action;	       /**< No security action */
 };
 
 struct roc_npc_action_sample {
@@ -282,6 +284,7 @@ struct roc_npc_sec_action {
 	 * XOR
 	 */
 	enum roc_npc_sec_action_alg alg;
+	bool is_non_inp;
 };
 
 struct roc_npc_attr {
-- 
2.34.1

[PATCH 15/18] net/cnxk: enable PDB in IPsec outbound path

[Rahul Bhansali]

From: Nithin Dabilpuram <ndabilpuram@marvell.com>

Enabled PDB in IPsec outbound datapath.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn20k_tx.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/cnxk/cn20k_tx.h b/drivers/net/cnxk/cn20k_tx.h
index 9e48744831..8e64d2e352 100644
--- a/drivers/net/cnxk/cn20k_tx.h
+++ b/drivers/net/cnxk/cn20k_tx.h
@@ -520,6 +520,7 @@ cn20k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1,
 		nixtx += 16;
 
 		w0 |= cn20k_nix_tx_ext_subs(flags) + 1ULL;
+		w0 |= sess_priv.chksum ? BIT_ULL(63) : BIT_ULL(62);
 		dptr += l2_len;
 		ucode_cmd[1] = dptr;
 		*cmd1 = vsetq_lane_u16(pkt_len + dlen_adj, *cmd1, 0);
@@ -660,6 +661,7 @@ cn20k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, uin
 		nixtx += 16;
 
 		w0 |= cn20k_nix_tx_ext_subs(flags) + 1ULL;
+		w0 |= sess_priv.chksum ? BIT_ULL(63) : BIT_ULL(62);
 		dptr += l2_len;
 		ucode_cmd[1] = dptr;
 		sg->seg1_size = pkt_len + dlen_adj;
-- 
2.34.1

[PATCH 16/18] common/cnxk: initialize CPT LF for CQ config

[Rahul Bhansali]

From: Rakesh Kudurumalla <rkudurumalla@marvell.com>

Initialize inline outbound CPT LF for CPT CQ
configurations.

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.c | 42 +++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 8 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 917c2c669a..86d571c6e2 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1573,8 +1573,18 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 		lf->msixoff = nix->cpt_msixoff[i];
 		lf->pci_dev = nix->pci_dev;
 
+		if (roc_feature_nix_has_cpt_cq_support()) {
+			if (inl_dev && inl_dev->cpt_cq_ena) {
+				lf->dq_ack_ena = true;
+				lf->cpt_cq_ena = true;
+				lf->cq_entry_size = 0;
+				lf->cq_all = 0;
+				lf->cq_size = lf->nb_desc;
+			}
+		}
+
 		/* Setup CPT LF instruction queue */
-		rc = cpt_lf_init(lf, false);
+		rc = cpt_lf_init(lf, lf->cpt_cq_ena);
 		if (rc) {
 			plt_err("Failed to initialize CPT LF, rc=%d", rc);
 			goto lf_fini;
@@ -1591,6 +1601,13 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 
 		/* Enable IQ */
 		roc_cpt_iq_enable(lf);
+		/* Enable CQ */
+		if (lf->cpt_cq_ena) {
+			rc = cpt_lf_register_irqs(lf, cpt_lf_misc_irq, nix_inl_cpt_done_irq);
+			if (rc)
+				goto lf_fini;
+			roc_cpt_cq_enable(lf);
+		}
 	}
 
 	if (!roc_nix->ipsec_out_max_sa)
@@ -1635,6 +1652,9 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	nix->outb_se_ring_base =
 		roc_nix->port_id * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS;
 
+	/* Fetch engine capabilities */
+	nix_inl_eng_caps_get(nix);
+
 	if (inl_dev == NULL || !inl_dev->set_soft_exp_poll) {
 		nix->outb_se_ring_cnt = 0;
 		return 0;
@@ -1658,13 +1678,15 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 		}
 	}
 
-	/* Fetch engine capabilities */
-	nix_inl_eng_caps_get(nix);
 	return 0;
 
 lf_fini:
-	for (j = i - 1; j >= 0; j--)
-		cpt_lf_fini(&lf_base[j], false);
+	for (j = i - 1; j >= 0; j--) {
+		lf = &lf_base[j];
+		cpt_lf_fini(lf, lf->cpt_cq_ena);
+		if (lf->cpt_cq_ena)
+			cpt_lf_unregister_irqs(lf, cpt_lf_misc_irq, nix_inl_cpt_done_irq);
+	}
 	plt_free(lf_base);
 lf_free:
 	rc |= cpt_lfs_free(dev);
@@ -1681,6 +1703,7 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix)
 	struct idev_cfg *idev = idev_get_cfg();
 	struct dev *dev = &nix->dev;
 	struct nix_inl_dev *inl_dev;
+	struct roc_cpt_lf *lf;
 	uint64_t *ring_base;
 	int i, rc, ret = 0;
 
@@ -1690,9 +1713,12 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix)
 	nix->inl_outb_ena = false;
 
 	/* Cleanup CPT LF instruction queue */
-	for (i = 0; i < nix->nb_cpt_lf; i++)
-		cpt_lf_fini(&lf_base[i], false);
-
+	for (i = 0; i < nix->nb_cpt_lf; i++) {
+		lf = &lf_base[i];
+		cpt_lf_fini(lf, lf->cpt_cq_ena);
+		if (lf->cpt_cq_ena)
+			cpt_lf_unregister_irqs(lf, cpt_lf_misc_irq, nix_inl_cpt_done_irq);
+	}
 	/* Free LF resources */
 	rc = cpt_lfs_free(dev);
 	if (rc)
-- 
2.34.1

[PATCH 17/18] common/cnxk: fix CPT CQ roll over handling

[Rahul Bhansali]

This fixes handling of CPT CQ ring roll over case.

Fixes: a7d64a7740e0 ("net/cnxk: handle soft expiry")

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/roc_cpt.c             |  2 +-
 drivers/common/cnxk/roc_cpt.h             |  1 +
 drivers/common/cnxk/roc_nix_inl.c         |  1 +
 drivers/common/cnxk/roc_nix_inl_dev_irq.c | 18 ++++++++++++------
 4 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 83e0c9896b..63419884ac 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -712,7 +712,7 @@ cpt_lf_cq_init(struct roc_cpt_lf *lf)
 
 	lf_cq_base.s.addr = addr >> 7;
 	plt_write64(lf_cq_base.u, lf->rbase + CPT_LF_CQ_BASE);
-	lf_cq_size.s.size = PLT_ALIGN(len, ROC_ALIGN);
+	lf_cq_size.s.size = lf->cq_size;
 	plt_write64(lf_cq_size.u, lf->rbase + CPT_LF_CQ_SIZE);
 
 	return 0;
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 67956758be..7547d0b020 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -159,6 +159,7 @@ struct roc_cpt_lf {
 	bool cpt_cq_ena;
 	uint8_t cq_entry_size;
 	uint32_t cq_size;
+	uint32_t cq_head;
 	/* End of Input parameters */
 	struct plt_pci_device *pci_dev;
 	struct dev *dev;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 86d571c6e2..aad2631673 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1580,6 +1580,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 				lf->cq_entry_size = 0;
 				lf->cq_all = 0;
 				lf->cq_size = lf->nb_desc;
+				lf->cq_head = 1;
 			}
 		}
 
diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
index 1c4822925c..89155a1f7d 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
@@ -57,8 +57,8 @@ nix_inl_cpt_cq_cb(struct roc_cpt_lf *lf)
 	union cpt_lf_cq_ptr cq_ptr;
 	struct cpt_cq_s *cq_s;
 	uint8_t fmt_msk = 0x3;
-	uint64_t nq_ptr;
-	uint32_t count;
+	uint32_t count, head;
+	uint32_t nq_ptr;
 	uint64_t i;
 
 	if (idev)
@@ -69,14 +69,15 @@ nix_inl_cpt_cq_cb(struct roc_cpt_lf *lf)
 		return;
 	}
 
+	head = lf->cq_head;
 	cq_base.u = plt_read64(lf->rbase + CPT_LF_CQ_BASE);
 	cq_ptr.u = plt_read64(lf->rbase + CPT_LF_CQ_PTR);
 	count = cq_ptr.s.count;
-
-	nq_ptr = (((cq_base.s.addr << 7)) + ((cq_ptr.s.nq_ptr - count) << 5));
-	cq_s = (struct cpt_cq_s *)nq_ptr;
+	nq_ptr = cq_ptr.s.nq_ptr;
 
 	for (i = 0; i < count; i++) {
+		cq_s = (struct cpt_cq_s *)(uintptr_t)(((cq_base.s.addr << 7)) + (head << 5));
+
 		if (cq_s->w0.s.uc_compcode && cq_s->w0.s.compcode) {
 			switch (cq_s->w2.s.fmt & fmt_msk) {
 			case WQE_PTR_CPTR:
@@ -93,8 +94,13 @@ nix_inl_cpt_cq_cb(struct roc_cpt_lf *lf)
 			inl_dev->work_cb(&tmp, sa, NIX_INL_CPT_CQ, (void *)cq_s, port_id);
 		}
 done:
-		cq_s = cq_s + 1;
+		head = (head + 1) % lf->cq_size;
 	}
+
+	lf->cq_head = head;
+	if (unlikely(nq_ptr != head))
+		plt_err("CPT LF[%d] CQ head %d != NQ ptr %d", lf->lf_id, head, nq_ptr);
+
 	/* Acknowledge the number of completed requests */
 	plt_write64(count, lf->rbase + CPT_LF_DONE_ACK);
 }
-- 
2.34.1

[PATCH 18/18] common/cnxk: fix duplicate branch compiler warning

[Rahul Bhansali]

With compiler option '-Wduplicated-branches', getting few
warnings such as "this condition has identical branches".

Macros are updated to address these warnings.

Bugzilla ID: 1811
Fixes: 0d9e323bacf0 ("common/cnxk: support for CN20K inline IPsec")
Fixes: c045d2e5cbbc ("common/cnxk: add CPT configuration")

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 drivers/common/cnxk/hw/rvu.h          |  2 ++
 drivers/common/cnxk/roc_cpt.c         |  7 +++----
 drivers/common/cnxk/roc_nix_inl.c     | 25 +++++++++----------------
 drivers/common/cnxk/roc_nix_inl_dev.c |  6 +-----
 drivers/common/cnxk/roc_nix_inl_dp.h  |  3 +++
 drivers/common/cnxk/roc_nix_priv.h    |  4 ++--
 6 files changed, 20 insertions(+), 27 deletions(-)

diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index ed2ba996e0..6f02d1e3d2 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -105,6 +105,8 @@
 #define RVU_VF_MBOX_REGION		 (0xc0000ull) /* [CN10K, .) */
 #define RVU_VF_MSIX_PBAX(a)		 (0xf0000ull | (uint64_t)(a) << 3)
 
+#define RVU_BLOCK_ADDRX_DISC(a) RVU_PF_BLOCK_ADDRX_DISC(a)
+
 /* CN20k RVU mbox registers */
 #define RVU_MBOX_AF_AFPFX_TRIGX(a)    (0x9000 | (a) << 3)
 #define RVU_MBOX_PF_PFAF_TRIGX(a)     RVU_PF_PFAF_MBOXX(a)
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 63419884ac..13eb9d3767 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -677,10 +677,9 @@ cpt_get_blkaddr(struct dev *dev)
 	 * attached to. Assume CPT LF's of only one block are attached
 	 * to a pffunc.
 	 */
-	if (dev_is_vf(dev))
-		off = RVU_VF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
-	else
-		off = RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
+
+	/* PF and VF block address offset is same, hence using common offset */
+	off = RVU_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
 
 	reg = plt_read64(dev->bar2 + off);
 
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index aad2631673..a21c40acf1 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -19,6 +19,10 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ ==
 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024);
 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==
 		  1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);
+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == ROC_NIX_INL_OW_IPSEC_INB_SA_SZ);
+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == ROC_NIX_INL_ON_IPSEC_INB_SA_SZ);
+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ);
+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ);
 
 static int
 nix_inl_meta_aura_destroy(struct roc_nix *roc_nix)
@@ -427,12 +431,8 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
 	/* CN9K SA size is different */
 	if (roc_nix->custom_inb_sa)
 		inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ;
-	else if (roc_model_is_cn9k())
-		inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
-	else if (roc_model_is_cn10k())
-		inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
 	else
-		inb_sa_sz = ROC_NIX_INL_OW_IPSEC_INB_SA_SZ;
+		inb_sa_sz = ROC_NIX_INL_IPSEC_INB_SA_SZ;
 
 	/* Alloc contiguous memory for Inbound SA's */
 	nix->inb_sa_sz[profile_id] = inb_sa_sz;
@@ -1198,10 +1198,9 @@ nix_inl_eng_caps_get(struct nix *nix)
 	inst.rptr = (uint64_t)rptr;
 	inst.w4.s.opcode_major = ROC_LOADFVC_MAJOR_OP;
 	inst.w4.s.opcode_minor = ROC_LOADFVC_MINOR_OP;
-	if (roc_model_is_cn9k() || roc_model_is_cn10k())
-		inst.w7.s.egrp = ROC_LEGACY_CPT_DFLT_ENG_GRP_SE;
-	else
-		inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
+
+	/* SE engine group ID is same for all platform */
+	inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
 
 	/* Use 1 min timeout for the poll */
 	const uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz();
@@ -1614,13 +1613,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	if (!roc_nix->ipsec_out_max_sa)
 		goto skip_sa_alloc;
 
-	/* CN9K SA size is different */
-	if (roc_model_is_cn9k())
-		sa_sz = ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ;
-	else if (roc_model_is_cn10k())
-		sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;
-	else
-		sa_sz = ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ;
+	sa_sz = ROC_NIX_INL_IPSEC_OUTB_SA_SZ;
 
 	/* Alloc contiguous memory of outbound SA */
 	sa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index fcbe9314a1..8414b9edc6 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -837,12 +837,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 	/* CN9K SA is different */
 	if (inl_dev->custom_inb_sa)
 		inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ;
-	else if (roc_model_is_cn9k())
-		inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
-	else if (roc_model_is_cn10k())
-		inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
 	else
-		inb_sa_sz = ROC_NIX_INL_OW_IPSEC_INB_SA_SZ;
+		inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
 
 	/* Alloc contiguous memory for Inbound SA's */
 	inl_dev->inb_sa_sz[profile_id] = inb_sa_sz;
diff --git a/drivers/common/cnxk/roc_nix_inl_dp.h b/drivers/common/cnxk/roc_nix_inl_dp.h
index eb101db179..6443770871 100644
--- a/drivers/common/cnxk/roc_nix_inl_dp.h
+++ b/drivers/common/cnxk/roc_nix_inl_dp.h
@@ -41,6 +41,9 @@
 	(ROC_NIX_INL_OW_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OW_IPSEC_OUTB_SW_RSVD)
 #define ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ_LOG2 9
 
+#define ROC_NIX_INL_IPSEC_INB_SA_SZ  ROC_NIX_INL_OT_IPSEC_INB_SA_SZ
+#define ROC_NIX_INL_IPSEC_OUTB_SA_SZ ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ
+
 /* Alignment of SA Base */
 #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)
 
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index 308a62a70e..d4b3c7c1af 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -23,10 +23,10 @@
 #define NIX_CQ_SEC_THRESH_LEVEL_REF1	(20 * 256 / 100)
 #define NIX_CQ_BP_THRESH_LEVEL_REF1	(60 * 256 / 100)
 #define NIX_CQ_SEC_BP_THRESH_LEVEL_REF1 (50 * 256 / 100)
-#define NIX_CQ_LBP_THRESH_FRAC_REF1	(80 * 16 / 100)
+#define NIX_CQ_LBP_THRESH_FRAC_REF1	(80 * 16 / 100.0)
 
 /* Apply LBP at 75% of actual BP */
-#define NIX_CQ_LBP_THRESH_FRAC	(75 * 16 / 100)
+#define NIX_CQ_LBP_THRESH_FRAC	(75 * 16 / 100.0)
 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
 #define NIX_RQ_AURA_BP_THRESH(percent, limit, shift) ((((limit) * (percent)) / 100) >> (shift))
 
-- 
2.34.1

[REVIEW] common/cnxk: fix duplicate branch compiler warning

[Stephen Hemminger]

AI-generated review of bundle-1704-common-cnxk.mbox
Reviewed using Claude (claude-opus-4-5-20251101)

This is an automated review. Please verify all suggestions.

---

# DPDK Patch Review: bundle-1704-common-cnxk.mbox

## Overview
This is a patch series of 18 patches for DPDK common/cnxk and net/cnxk drivers, primarily dealing with inline IPsec improvements for CN20K platform.

---

## Patch 1/18: common/cnxk: fix engine capabilities fetch logic

### Commit Message
**Warning**: The commit message body lacks detail. The description "This patch fixes the same" is vague and should explain what the actual fix is.

**Info**: The `Fixes:` tag is correctly formatted with 12-character SHA.

### Code Review
**Error**: In `cnxk_security.c`, lines 1400 and 1409 - The change from `ROC_IE_OT_SA_LIFE_UNIT_*` to `ROC_IE_OW_SA_LIFE_UNIT_*` macros appears correct for the OW (cn20k) context.

**Error**: In `roc_nix_inl.c`, line 1231 - The loop condition change from `while (lmt_status != 0)` to `while (lmt_status == 0)` is a significant logic change. The commit message should explain why the previous condition was wrong (it was causing an infinite loop as stated).

---

## Patch 2/18: common/cnxk: remove dependency on cryptodev for RXC

### Commit Message
**Info**: Good descriptive subject line.

### Code Review
**Info**: The code correctly moves the cryptodev check inside the `roc_model_is_cn10k()` block, allowing cn20k to proceed without this dependency.

---

## Patch 3/18: common/cnxk: support inbound pdb configuration

### Commit Message
**Info**: Subject and body are acceptable.

### Code Review
**Info**: Simple addition of `pdb_ena` field usage in mbox configuration.

---

## Patch 4/18: common/cnxk: update CPT RXC structures

### Commit Message
**Warning**: The subject says "update" but should be more specific about what was updated (byte order/endianness handling).

### Code Review
**Info**: The structures are being reorganized with proper unions for different platforms (cn10k vs generic). The byte order appears to be reversed in the new `cpt_frag_info_s` compared to `cpt_cn10k_frag_info_s`.

---

## Patch 5/18: common/cnxk: update inline profile ID for cn20k

### Commit Message
**Info**: Acceptable.

### Code Review
**Info**: Correctly adds cn20k-specific profile ID handling.

---

## Patch 6/18: common/cnxk: update inline RQ mask

### Commit Message
**Info**: Acceptable.

### Code Review
**Warning**: Significant code removal - the `nix_inl_rq_mask_cfg` function removes the SPB setup via `nix_rx_inl_lf_cfg` mbox call. This should be validated that it's not needed for cn20k.

---

## Patch 7/18: net/cnxk: avoid security flag for custom inbound SA

### Commit Message
**Info**: Good descriptive subject.

### Code Review
**Info**: Simple conditional change that looks correct.

---

## Patch 8/18: net/cnxk: add CPT code check for soft expiry

### Commit Message
**Info**: Acceptable.

### Code Review
**Info**: Adding `ROC_IE_OW_UCC_SUCCESS_SA_SOFTEXP_AGAIN` case is a valid addition.

---

## Patch 9/18: net/cnxk: skip write SA for cn20k

### Commit Message
**Info**: Acceptable but could explain why write SA should be skipped.

### Code Review
**Info**: Simple flag change.

---

## Patch 10/18: net/cnxk: update NIX reassembly fast path

### Commit Message
**Info**: Acceptable.

### Code Review
**Warning**: The function `nix_cqe_xtract_mseg` now has an `#if defined(RTE_ARCH_ARM64)` guard with an empty stub for non-ARM64. This may break functionality on other architectures silently.

**Info**: The use of NEON intrinsics (`vreinterpret_u16_u64`, `vrev64_u16`, etc.) is appropriate for ARM64 optimization.

---

## Patch 11/18: net/cnxk: update aura batch free

### Commit Message
**Info**: Subject could be more descriptive about what was updated (mask change from 0x1 to 0x3).

### Code Review
**Info**: The mask change from `0x1` to `0x3` appears consistent across all occurrences.

---

## Patch 12/18: net/cnxk: update fastpath function for OOP

### Commit Message
**Info**: OOP should be expanded (Out-Of-Place) in the commit body for clarity.

### Code Review
**Info**: Adds OOP (out-of-place) processing support. The `nix_sec_oop_process` function is well-implemented.

**Info**: The function correctly handles the alternate encrypted-decrypted pointer pattern in the gather list.

---

## Patch 13/18: event/cnxk: update fastpath function for OOP

### Commit Message
**Info**: Acceptable.

### Code Review
**Info**: Consistent OOP handling with the net/cnxk changes.

---

## Patch 14/18: common/cnxk: flow rule config for non-inplace

### Commit Message
**Info**: Acceptable.

### Code Review
**Info**: Adds `is_non_inp` flag handling in flow rules.

---

## Patch 15/18: net/cnxk: enable PDB in IPsec outbound path

### Commit Message
**Info**: PDB should be expanded in the commit body.

### Code Review
**Info**: Simple bit flag additions for PDB enablement.

---

## Patch 16/18: common/cnxk: initialize CPT LF for CQ config

### Commit Message
**Info**: Acceptable.

### Code Review
**Info**: Properly initializes CPT LF for CQ configurations with appropriate cleanup in the error path and fini function.

---

## Patch 17/18: common/cnxk: fix CPT CQ roll over handling

### Commit Message
**Info**: Good - includes proper `Fixes:` tag.

### Code Review
**Info**: The fix correctly handles ring rollover by tracking `cq_head` separately and using modulo arithmetic.

**Warning**: Line 102-103 adds error logging with `plt_err` but this could be noisy in production. Consider using `plt_warn` or adding rate limiting.

---

## Patch 18/18: common/cnxk: fix duplicate branch compiler warning

### Commit Message
**Info**: Good - includes Bugzilla ID and proper `Fixes:` tags.

### Code Review
**Info**: The `PLT_STATIC_ASSERT` additions verify that SA sizes are equal across platforms, which justifies using a common macro.

**Warning**: In `roc_nix_priv.h`, lines 26 and 29 - changing integer division to floating point division (`100` to `100.0`) changes the type of the result. Verify this doesn't cause issues with consumers of these macros.

```c
#define NIX_CQ_LBP_THRESH_FRAC_REF1	(80 * 16 / 100.0)
#define NIX_CQ_LBP_THRESH_FRAC	(75 * 16 / 100.0)
```

---

## General Issues Across All Patches

### License Compliance
**Info**: All modified files appear to have proper SPDX license identifiers already present.

### Missing Items
**Warning**: No release notes updates found in this patch series despite API/behavior changes. Consider adding entries to `doc/guides/rel_notes/`.

**Warning**: Several patches lack `Cc: stable@dpdk.org` tag despite being bug fixes (patches 1, 17, 18).

### Coding Style
**Info**: Code generally follows DPDK coding standards with proper indentation and naming conventions.

---

## Summary

| Severity | Count |
|----------|-------|
| Error | 0 |
| Warning | 8 |
| Info | Multiple |

The patch series is generally well-structured. Main concerns are:
1. Missing `Cc: stable@dpdk.org` on fix patches
2. Missing release notes
3. Some commit messages could be more descriptive
4. Floating point division change in macros should be verified

Re: [PATCH 18/18] common/cnxk: fix duplicate branch compiler warning

[Jerin Jacob]

On Wed, Jan 28, 2026 at 11:44 AM Rahul Bhansali <rbhansali@marvell.com> wrote:
>
> With compiler option '-Wduplicated-branches', getting few
> warnings such as "this condition has identical branches".
>
> Macros are updated to address these warnings.
>
> Bugzilla ID: 1811
> Fixes: 0d9e323bacf0 ("common/cnxk: support for CN20K inline IPsec")
> Fixes: c045d2e5cbbc ("common/cnxk: add CPT configuration")
>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>

Please check AI the comments in
https://patches.dpdk.org/project/dpdk/patch/20260128060316.3967610-18-rbhansali@marvell.com/

1)Please fix
Is it candidate for Cc: stable@dpdk.org backport?
        common/cnxk: fix engine capabilities fetch logic
        common/cnxk: fix CPT CQ roll over handling
        common/cnxk: fix duplicate branch compiler warning

2)Add new feature to release notes

3)Some of the changes are fixes: and mark the as fixes


> ---
>  drivers/common/cnxk/hw/rvu.h          |  2 ++
>  drivers/common/cnxk/roc_cpt.c         |  7 +++----
>  drivers/common/cnxk/roc_nix_inl.c     | 25 +++++++++----------------
>  drivers/common/cnxk/roc_nix_inl_dev.c |  6 +-----
>  drivers/common/cnxk/roc_nix_inl_dp.h  |  3 +++
>  drivers/common/cnxk/roc_nix_priv.h    |  4 ++--
>  6 files changed, 20 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
> index ed2ba996e0..6f02d1e3d2 100644
> --- a/drivers/common/cnxk/hw/rvu.h
> +++ b/drivers/common/cnxk/hw/rvu.h
> @@ -105,6 +105,8 @@
>  #define RVU_VF_MBOX_REGION              (0xc0000ull) /* [CN10K, .) */
>  #define RVU_VF_MSIX_PBAX(a)             (0xf0000ull | (uint64_t)(a) << 3)
>
> +#define RVU_BLOCK_ADDRX_DISC(a) RVU_PF_BLOCK_ADDRX_DISC(a)
> +
>  /* CN20k RVU mbox registers */
>  #define RVU_MBOX_AF_AFPFX_TRIGX(a)    (0x9000 | (a) << 3)
>  #define RVU_MBOX_PF_PFAF_TRIGX(a)     RVU_PF_PFAF_MBOXX(a)
> diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
> index 63419884ac..13eb9d3767 100644
> --- a/drivers/common/cnxk/roc_cpt.c
> +++ b/drivers/common/cnxk/roc_cpt.c
> @@ -677,10 +677,9 @@ cpt_get_blkaddr(struct dev *dev)
>          * attached to. Assume CPT LF's of only one block are attached
>          * to a pffunc.
>          */
> -       if (dev_is_vf(dev))
> -               off = RVU_VF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
> -       else
> -               off = RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
> +
> +       /* PF and VF block address offset is same, hence using common offset */
> +       off = RVU_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
>
>         reg = plt_read64(dev->bar2 + off);
>
> diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
> index aad2631673..a21c40acf1 100644
> --- a/drivers/common/cnxk/roc_nix_inl.c
> +++ b/drivers/common/cnxk/roc_nix_inl.c
> @@ -19,6 +19,10 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ ==
>  PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024);
>  PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==
>                   1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);
> +PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == ROC_NIX_INL_OW_IPSEC_INB_SA_SZ);
> +PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == ROC_NIX_INL_ON_IPSEC_INB_SA_SZ);
> +PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ);
> +PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ);
>
>  static int
>  nix_inl_meta_aura_destroy(struct roc_nix *roc_nix)
> @@ -427,12 +431,8 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
>         /* CN9K SA size is different */
>         if (roc_nix->custom_inb_sa)
>                 inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ;
> -       else if (roc_model_is_cn9k())
> -               inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
> -       else if (roc_model_is_cn10k())
> -               inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
>         else
> -               inb_sa_sz = ROC_NIX_INL_OW_IPSEC_INB_SA_SZ;
> +               inb_sa_sz = ROC_NIX_INL_IPSEC_INB_SA_SZ;
>
>         /* Alloc contiguous memory for Inbound SA's */
>         nix->inb_sa_sz[profile_id] = inb_sa_sz;
> @@ -1198,10 +1198,9 @@ nix_inl_eng_caps_get(struct nix *nix)
>         inst.rptr = (uint64_t)rptr;
>         inst.w4.s.opcode_major = ROC_LOADFVC_MAJOR_OP;
>         inst.w4.s.opcode_minor = ROC_LOADFVC_MINOR_OP;
> -       if (roc_model_is_cn9k() || roc_model_is_cn10k())
> -               inst.w7.s.egrp = ROC_LEGACY_CPT_DFLT_ENG_GRP_SE;
> -       else
> -               inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
> +
> +       /* SE engine group ID is same for all platform */
> +       inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
>
>         /* Use 1 min timeout for the poll */
>         const uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz();
> @@ -1614,13 +1613,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
>         if (!roc_nix->ipsec_out_max_sa)
>                 goto skip_sa_alloc;
>
> -       /* CN9K SA size is different */
> -       if (roc_model_is_cn9k())
> -               sa_sz = ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ;
> -       else if (roc_model_is_cn10k())
> -               sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;
> -       else
> -               sa_sz = ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ;
> +       sa_sz = ROC_NIX_INL_IPSEC_OUTB_SA_SZ;
>
>         /* Alloc contiguous memory of outbound SA */
>         sa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,
> diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
> index fcbe9314a1..8414b9edc6 100644
> --- a/drivers/common/cnxk/roc_nix_inl_dev.c
> +++ b/drivers/common/cnxk/roc_nix_inl_dev.c
> @@ -837,12 +837,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
>         /* CN9K SA is different */
>         if (inl_dev->custom_inb_sa)
>                 inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ;
> -       else if (roc_model_is_cn9k())
> -               inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
> -       else if (roc_model_is_cn10k())
> -               inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
>         else
> -               inb_sa_sz = ROC_NIX_INL_OW_IPSEC_INB_SA_SZ;
> +               inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
>
>         /* Alloc contiguous memory for Inbound SA's */
>         inl_dev->inb_sa_sz[profile_id] = inb_sa_sz;
> diff --git a/drivers/common/cnxk/roc_nix_inl_dp.h b/drivers/common/cnxk/roc_nix_inl_dp.h
> index eb101db179..6443770871 100644
> --- a/drivers/common/cnxk/roc_nix_inl_dp.h
> +++ b/drivers/common/cnxk/roc_nix_inl_dp.h
> @@ -41,6 +41,9 @@
>         (ROC_NIX_INL_OW_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OW_IPSEC_OUTB_SW_RSVD)
>  #define ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ_LOG2 9
>
> +#define ROC_NIX_INL_IPSEC_INB_SA_SZ  ROC_NIX_INL_OT_IPSEC_INB_SA_SZ
> +#define ROC_NIX_INL_IPSEC_OUTB_SA_SZ ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ
> +
>  /* Alignment of SA Base */
>  #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)
>
> diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
> index 308a62a70e..d4b3c7c1af 100644
> --- a/drivers/common/cnxk/roc_nix_priv.h
> +++ b/drivers/common/cnxk/roc_nix_priv.h
> @@ -23,10 +23,10 @@
>  #define NIX_CQ_SEC_THRESH_LEVEL_REF1   (20 * 256 / 100)
>  #define NIX_CQ_BP_THRESH_LEVEL_REF1    (60 * 256 / 100)
>  #define NIX_CQ_SEC_BP_THRESH_LEVEL_REF1 (50 * 256 / 100)
> -#define NIX_CQ_LBP_THRESH_FRAC_REF1    (80 * 16 / 100)
> +#define NIX_CQ_LBP_THRESH_FRAC_REF1    (80 * 16 / 100.0)
>
>  /* Apply LBP at 75% of actual BP */
> -#define NIX_CQ_LBP_THRESH_FRAC (75 * 16 / 100)
> +#define NIX_CQ_LBP_THRESH_FRAC (75 * 16 / 100.0)
>  #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
>  #define NIX_RQ_AURA_BP_THRESH(percent, limit, shift) ((((limit) * (percent)) / 100) >> (shift))
>
> --
> 2.34.1
>

[PATCH v2 01/18] common/cnxk: fix engine capabilities fetch logic

[Rahul Bhansali]

From: Rakesh Kudurumalla <rkudurumalla@marvell.com>

For CN9k platform, incorrect status is checked from LOAD
FVC instruction while retrieving engine capabilities.

The loop is updated for a valid return status check on
LOADFVC instruction.

Fixes: 7c67c489d466 ("common/cnxk: fetch engine capabilities")
Cc: stable@dpdk.org

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
Changes in v2: Updated commit message. Removed not related macro change.

 drivers/common/cnxk/roc_nix_inl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index f8be98efd5..683a9cc7ce 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1228,7 +1228,7 @@ nix_inl_eng_caps_get(struct nix *nix)
 		do {
 			roc_lmt_mov_seg((void *)lmt_base, &inst, 4);
 			lmt_status = roc_lmt_submit_ldeor(lf->io_addr);
-		} while (lmt_status != 0);
+		} while (lmt_status == 0);

 		/* Wait until CPT instruction completes */
 		do {
--
2.34.1

[PATCH v2 02/18] common/cnxk: remove dependency on cryptodev for RXC

[Rahul Bhansali]

Removes dependency on probe of cryptodev for reassembly
configuration and included RXC queue config for cn20k
platform.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.

 drivers/common/cnxk/roc_nix_inl.c | 15 ++++++++-------
 drivers/common/cnxk/roc_nix_inl.h |  2 ++
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 683a9cc7ce..86bafd5c33 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -968,12 +968,6 @@ roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t max_
 	if (!idev)
 		return -EFAULT;

-	roc_cpt = idev->cpt;
-	if (!roc_cpt) {
-		plt_err("Cannot support inline inbound, cryptodev not probed");
-		return -ENOTSUP;
-	}
-
 	cfg.step = req_cfg->step ? req_cfg->step :
 				   (max_wait_time * 1000 / ROC_NIX_INL_REAS_ACTIVE_LIMIT);
 	cfg.zombie_limit =
@@ -985,8 +979,14 @@ roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t max_
 	cfg.active_thres =
 		req_cfg->active_thres ? req_cfg->active_thres : ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;

-	if (roc_model_is_cn10k())
+	if (roc_model_is_cn10k()) {
+		roc_cpt = idev->cpt;
+		if (!roc_cpt) {
+			plt_err("Cryptodev not probed");
+			return -ENOTSUP;
+		}
 		return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
+	}

 	inl_dev = idev->nix_inl_dev;
 	if (!inl_dev) {
@@ -1009,6 +1009,7 @@ roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t max_
 	req->zombie_thres = cfg.zombie_thres;
 	req->active_limit = cfg.active_limit;
 	req->active_thres = cfg.active_thres;
+	req->cpt_af_rxc_que_cfg = ROC_NIX_INL_RXC_QUE_BLK_THR << 32;

 	rc = mbox_process(mbox);
 exit:
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index 7970ac2258..68f395438c 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -41,6 +41,8 @@
 #define ROC_NIX_INL_REAS_ZOMBIE_LIMIT	  0xFFF
 #define ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD 10

+#define ROC_NIX_INL_RXC_QUE_BLK_THR 0x40UL
+
 enum nix_inl_event_type {
 	NIX_INL_CPT_CQ = 1,
 	NIX_INL_SSO,
--
2.34.1

[PATCH v2 03/18] common/cnxk: support inbound pdb configuration

[Rahul Bhansali]

Mbox cpt_rx_inl_queue_cfg is extended to enable/disable PDB
for inline inbound IPsec path.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.

 drivers/common/cnxk/roc_mbox.h        | 4 +++-
 drivers/common/cnxk/roc_nix_inl_dev.c | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 3e913fa13c..7871613d9c 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -2423,7 +2423,9 @@ struct cpt_rx_inline_qcfg_req {
 	uint8_t __io pf_func_ctx;
 	uint8_t __io inflight_limit;
 	uint8_t __io queue_pri;
-	uint8_t __io rsvd[32]; /* For future extensions */
+	uint8_t __io cq_remap;
+	uint8_t __io pdb_ena;
+	uint8_t __io rsvd[30]; /* For future extensions */
 };

 #define CPT_INLINE_INBOUND  0
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 3a4f1ac1e7..727a2e2a81 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -212,6 +212,7 @@ nix_inl_inb_queue_setup(struct nix_inl_dev *inl_dev, uint8_t slot_id)
 	cpt_req->slot = slot_id;
 	cpt_req->rx_queue_id = qid;
 	cpt_req->eng_grpmsk = inl_dev->eng_grpmask;
+	cpt_req->pdb_ena = 1;
 	rc = mbox_process(mbox);
 	if (rc) {
 		plt_err("Failed to configure CPT LF for inline processing, rc=%d", rc);
--
2.34.1

[PATCH v2 04/18] common/cnxk: update CPT RXC structures

[Rahul Bhansali]

Updates CPT RXC SGs and frag info structures as per
CN20k and CN10k platforms.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/common/cnxk/hw/cpt.h        | 143 +++++++++++++++++++---------
 drivers/common/cnxk/roc_cpt_debug.c |   2 +-
 2 files changed, 101 insertions(+), 44 deletions(-)

diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index 727cee07b4..6e577b6277 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -549,30 +549,60 @@ union cpt_frag_info {
 	};
 };

-struct cpt_frag_info_s {
-	/* WORD 0 */
-	union {
-		uint64_t u64;
-		struct {
-			/* CPT HW swaps each 8B word implicitly */
-			union cpt_frag_info f0;
-			union cpt_frag_info f1;
-			union cpt_frag_info f2;
-			union cpt_frag_info f3;
-		};
-	} w0;
+union cpt_rxc_frag_info_u {
+	struct cpt_frag_info_s {
+		/* WORD 0 */
+		union {
+			uint64_t u64;
+			struct {
+				/* CPT HW swaps each 8B word implicitly */
+				union cpt_frag_info f3;
+				union cpt_frag_info f2;
+				union cpt_frag_info f1;
+				union cpt_frag_info f0;
+			};
+		} w0;

-	/* WORD 1 */
-	union {
-		uint64_t u64;
-		struct {
-			/* CPT HW swaps each 8B word implicitly */
-			uint16_t frag_size0;
-			uint16_t frag_size1;
-			uint16_t frag_size2;
-			uint16_t frag_size3;
-		};
-	} w1;
+		/* WORD 1 */
+		union {
+			uint64_t u64;
+			struct {
+				/* CPT HW swaps each 8B word implicitly */
+				uint16_t frag_size3;
+				uint16_t frag_size2;
+				uint16_t frag_size1;
+				uint16_t frag_size0;
+			};
+		} w1;
+	} s;
+
+	struct cpt_cn10k_frag_info_s {
+		/* WORD 0 */
+		union {
+			uint64_t u64;
+			struct {
+				/* CPT HW swaps each 8B word implicitly */
+				union cpt_frag_info f0;
+				union cpt_frag_info f1;
+				union cpt_frag_info f2;
+				union cpt_frag_info f3;
+			};
+		} w0;
+
+		/* WORD 1 */
+		union {
+			uint64_t u64;
+			struct {
+				/* CPT HW swaps each 8B word implicitly */
+				uint16_t frag_size0;
+				uint16_t frag_size1;
+				uint16_t frag_size2;
+				uint16_t frag_size3;
+			};
+		} w1;
+	} cn10k;
+
+	uint64_t u64[2];
 };

 /* CPT rxc pointer info structure */
@@ -591,29 +621,56 @@ struct cpt_rxc_ptr_info_s {
 };

 /* CPT rxc scatter/gather subdescriptor structure */
-struct cpt_rxc_sg_s {
-	/* WORD 0 */
-	union {
-		uint64_t u64;
-		struct {
-			uint16_t seg1_size;
-			uint16_t seg2_size;
-			uint16_t seg3_size;
-			uint16_t segs : 2;
-			uint16_t nxt_fst_frag : 3;
-			uint16_t blk_sz : 4;
-			uint16_t rsvd_63_57 : 7;
-		};
-	} w0;
+union cpt_rxc_sg_u {
+	struct cpt_rxc_sg_s {
+		/* WORD 0 */
+		union {
+			uint64_t u64;
+			struct {
+				uint16_t rsvd_63_57 : 7;
+				uint16_t blk_sz : 4;
+				uint16_t nxt_fst_frag : 3;
+				uint16_t segs : 2;
+				uint16_t seg3_size;
+				uint16_t seg2_size;
+				uint16_t seg1_size;
+			};
+		} w0;

-	/* WORD 1 */
-	uint64_t seg1_ptr;
+		/* WORD 1 */
+		uint64_t seg1_ptr;

-	/* WORD 2 */
-	uint64_t seg2_ptr;
+		/* WORD 2 */
+		uint64_t seg2_ptr;
+
+		/* WORD 3 */
+		uint64_t seg3_ptr;
+	} s;
+
+	struct cpt_cn10k_rxc_sg_s {
+		/* WORD 0 */
+		union {
+			uint64_t u64;
+			struct {
+				uint16_t seg1_size;
+				uint16_t seg2_size;
+				uint16_t seg3_size;
+				uint16_t segs : 2;
+				uint16_t rsvd_63_50 : 14;
+			};
+		} w0;
+
+		/* WORD 1 */
+		uint64_t seg1_ptr;
+
+		/* WORD 2 */
+		uint64_t seg2_ptr;
+
+		/* WORD 3 */
+		uint64_t seg3_ptr;
+	} cn10k;

-	/* WORD 3 */
-	uint64_t seg3_ptr;
+	uint64_t u64[4];
 };

 union cpt_fc_write_s {
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index 28aedf088e..3b3e678c20 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -125,7 +125,7 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
 static inline void
 cpt_cn10k_parse_hdr_dump(FILE *file, const struct cpt_cn10k_parse_hdr_s *cpth)
 {
-	struct cpt_frag_info_s *frag_info;
+	struct cpt_cn10k_frag_info_s *frag_info;
 	uint32_t offset;
 	uint64_t *slot;

--
2.34.1

[PATCH v2 05/18] common/cnxk: update inline profile ID for cn20k

[Rahul Bhansali]

Update inline IPsec profile ID in nix_spi_to_sa_add mbox
as required by ROC_NPC_SEC_ACTION_ALG4 for cn20k.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.

 drivers/common/cnxk/roc_npc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 56e0e05b63..7846913417 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -491,6 +491,7 @@ npc_parse_spi_to_sa_action(struct roc_npc *roc_npc, const struct roc_npc_action
 			   struct roc_npc_flow *flow, uint8_t *has_spi_to_sa_action)
 {
 	const struct roc_npc_sec_action *sec_action;
+	struct roc_nix *roc_nix = roc_npc->roc_nix;
 	struct nix_spi_to_sa_add_req *req;
 	struct nix_spi_to_sa_add_rsp *rsp;
 	struct nix_inl_dev *inl_dev;
@@ -546,6 +547,9 @@ npc_parse_spi_to_sa_action(struct roc_npc *roc_npc, const struct roc_npc_action
 		req->spi_index = plt_be_to_cpu_32(flow->spi_to_sa_info.spi);
 		req->match_id = flow->match_id;
 		req->valid = true;
+		if (roc_model_is_cn20k())
+			req->inline_profile_id =
+				roc_nix_inl_inb_ipsec_profile_id_get(roc_nix, true);
 		rc = mbox_process_msg(mbox, (void *)&rsp);
 		if (rc)
 			return rc;
--
2.34.1

[PATCH v2 06/18] common/cnxk: update inline RQ mask configuration

[Rahul Bhansali]

Inline IPsec RQ mask configuration is modified as per
updates in nix_lf_inline_rq_cfg mbox.
Also, adds the support of default RQ first skip bytes
configuration for local meta aura option.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/common/cnxk/roc_mbox.h    |  4 +-
 drivers/common/cnxk/roc_nix.h     |  1 +
 drivers/common/cnxk/roc_nix_inl.c | 82 +++++++++++++------------------
 3 files changed, 37 insertions(+), 50 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 7871613d9c..3da85b4d12 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1844,12 +1844,12 @@ struct nix_rq_cpt_field_mask_cfg_req {
 		uint64_t __io rq_ctx_word_mask[RQ_CTX_MASK_MAX];
 		__io struct nix_cn10k_rq_ctx_s rq_mask;
 	};
-	struct nix_lf_rx_ipec_cfg1_req {
+	struct nix_lf_rx_ipsec_cfg1_inline_replay_req {
 		uint32_t __io spb_cpt_aura;
 		uint8_t __io rq_mask_enable;
 		uint8_t __io spb_cpt_sizem1;
 		uint8_t __io spb_cpt_enable;
-	} ipsec_cfg1;
+	} ipsec_cfg1_inline_replay;
 };

 struct nix_lso_format_cfg {
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 326decde2b..58f71c10e8 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -590,6 +590,7 @@ struct roc_nix {
 	bool force_tail_drop;
 	bool dis_xqe_drop;
 	bool sq_resize_ena;
+	uint8_t def_first_skip;
 	/* End of input parameters */
 	/* LMT line base for "Per Core Tx LMT line" mode*/
 	uintptr_t lmt_base;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 86bafd5c33..917c2c669a 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -101,10 +101,12 @@ nix_inl_meta_aura_create(struct idev_cfg *idev, struct roc_nix *roc_nix, uint16_
 			nb_bufs += roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);

 		/* Override meta buf size from NIX devargs if present */
-		if (roc_nix->meta_buf_sz)
+		if (roc_nix->meta_buf_sz) {
 			buf_sz = roc_nix->meta_buf_sz;
-		else
-			buf_sz = first_skip + NIX_INL_META_SIZE;
+		} else {
+			buf_sz = NIX_INL_META_SIZE;
+			buf_sz += roc_nix->def_first_skip ? roc_nix->def_first_skip : first_skip;
+		}

 		/* Create Metapool name */
 		snprintf(mempool_name, sizeof(mempool_name), "NIX_INL_META_POOL_%d",
@@ -304,10 +306,14 @@ nix_inl_global_meta_buffer_validate(struct idev_cfg *idev, struct roc_nix_rq *rq
 static int
 nix_inl_local_meta_buffer_validate(struct roc_nix *roc_nix, struct roc_nix_rq *rq)
 {
+	uint32_t buf_sz = NIX_INL_META_SIZE;
+
+	buf_sz += roc_nix->def_first_skip ? roc_nix->def_first_skip : rq->first_skip;
+
 	/* Validate if we have enough space for meta buffer */
-	if (roc_nix->buf_sz && (rq->first_skip + NIX_INL_META_SIZE > roc_nix->buf_sz)) {
-		plt_err("Meta buffer size %u not sufficient to meet RQ first skip %u",
-			roc_nix->buf_sz, rq->first_skip);
+	if (roc_nix->buf_sz && (buf_sz > roc_nix->buf_sz)) {
+		plt_err("Meta buffer size %u is not sufficient to meet minimum required %u",
+			roc_nix->buf_sz, buf_sz);
 		return -EIO;
 	}

@@ -1018,7 +1024,7 @@ roc_nix_reassembly_configure(struct roc_cpt_rxc_time_cfg *req_cfg, uint32_t max_
 }

 static void
-nix_inl_rq_mask_init(struct nix_rq_cpt_field_mask_cfg_req *msk_req)
+nix_inl_rq_mask_init(struct nix_rq_cpt_field_mask_cfg_req *msk_req, uint8_t first_skip)
 {
 	int i;

@@ -1041,6 +1047,8 @@ nix_inl_rq_mask_init(struct nix_rq_cpt_field_mask_cfg_req *msk_req)
 	msk_req->rq_set.spb_drop_ena = 0;
 	msk_req->rq_set.xqe_drop_ena = 0;
 	msk_req->rq_set.spb_ena = 1;
+	if (first_skip)
+		msk_req->rq_set.first_skip = first_skip;

 	if (!roc_feature_nix_has_second_pass_drop()) {
 		msk_req->rq_set.ena = 1;
@@ -1065,6 +1073,8 @@ nix_inl_rq_mask_init(struct nix_rq_cpt_field_mask_cfg_req *msk_req)
 	msk_req->rq_mask.spb_drop_ena = 0;
 	msk_req->rq_mask.xqe_drop_ena = 0;
 	msk_req->rq_mask.spb_ena = 0;
+	if (first_skip)
+		msk_req->rq_mask.first_skip = 0;
 }

 static int
@@ -1087,7 +1097,7 @@ nix_inl_legacy_rq_mask_setup(struct roc_nix *roc_nix, bool enable)
 	if (msk_req == NULL)
 		goto exit;

-	nix_inl_rq_mask_init(msk_req);
+	nix_inl_rq_mask_init(msk_req, 0);
 	if (roc_nix->local_meta_aura_ena) {
 		aura_handle = roc_nix->meta_aura_handle;
 		buf_sz = roc_nix->buf_sz;
@@ -1100,10 +1110,10 @@ nix_inl_legacy_rq_mask_setup(struct roc_nix *roc_nix, bool enable)
 		buf_sz = inl_cfg->buf_sz;
 	}

-	msk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle);
-	msk_req->ipsec_cfg1.rq_mask_enable = enable;
-	msk_req->ipsec_cfg1.spb_cpt_sizem1 = (buf_sz >> 7) - 1;
-	msk_req->ipsec_cfg1.spb_cpt_enable = enable;
+	msk_req->ipsec_cfg1_inline_replay.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle);
+	msk_req->ipsec_cfg1_inline_replay.rq_mask_enable = enable;
+	msk_req->ipsec_cfg1_inline_replay.spb_cpt_sizem1 = (buf_sz >> 7) - 1;
+	msk_req->ipsec_cfg1_inline_replay.spb_cpt_enable = enable;

 	rc = mbox_process(mbox);
 exit:
@@ -1116,10 +1126,8 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
 {
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct nix_rq_cpt_field_mask_cfg_req *msk_req;
-	struct idev_cfg *idev = idev_get_cfg();
-	struct nix_rx_inl_lf_cfg_req *lf_cfg;
-	struct idev_nix_inl_cfg *inl_cfg;
 	uint64_t aura_handle;
+	uint8_t first_skip;
 	struct mbox *mbox;
 	int rc = -ENOSPC;
 	uint64_t buf_sz;
@@ -1133,21 +1141,8 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
 	if (msk_req == NULL)
 		goto exit;

-	nix_inl_rq_mask_init(msk_req);
-	rc = mbox_process(mbox);
-	if (rc) {
-		plt_err("Failed to setup NIX Inline RQ mask, rc=%d", rc);
-		goto exit;
-	}
-
-	/* SPB setup */
-	if (!roc_nix->local_meta_aura_ena && !roc_nix->custom_meta_aura_ena)
-		goto exit;
-
-	if (!idev)
-		return -ENOENT;
-
-	inl_cfg = &idev->inl_cfg;
+	first_skip = roc_nix->def_first_skip ? (roc_nix->def_first_skip / 8) : 0;
+	nix_inl_rq_mask_init(msk_req, first_skip);

 	if (roc_nix->local_meta_aura_ena) {
 		aura_handle = roc_nix->meta_aura_handle;
@@ -1157,28 +1152,19 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
 			rc = -EINVAL;
 			goto exit;
 		}
-	} else {
-		aura_handle = roc_npa_zero_aura_handle();
-		buf_sz = inl_cfg->buf_sz;
-	}

-	/* SPB setup */
-	lf_cfg = mbox_alloc_msg_nix_rx_inl_lf_cfg(mbox);
-	if (lf_cfg == NULL) {
-		rc = -ENOSPC;
-		goto exit;
+		/* SPB setup */
+		msk_req->ipsec_cfg1_inline_replay.spb_cpt_aura =
+			roc_npa_aura_handle_to_aura(aura_handle);
+		msk_req->ipsec_cfg1_inline_replay.rq_mask_enable = enable;
+		msk_req->ipsec_cfg1_inline_replay.spb_cpt_sizem1 = (buf_sz >> 7) - 1;
+		msk_req->ipsec_cfg1_inline_replay.spb_cpt_enable = enable;
 	}

-	lf_cfg->rx_inline_sa_base = (uintptr_t)nix->inb_sa_base;
-	lf_cfg->rx_inline_cfg0 = nix->rx_inline_cfg0;
-	lf_cfg->profile_id = nix->ipsec_prof_id;
-	if (enable)
-		lf_cfg->rx_inline_cfg1 =
-			(nix->rx_inline_cfg1 | BIT_ULL(37) | ((buf_sz >> 7) - 1) << 38 |
-			 roc_npa_aura_handle_to_aura(aura_handle) << 44);
-	else
-		lf_cfg->rx_inline_cfg1 = nix->rx_inline_cfg1;
 	rc = mbox_process(mbox);
+	if (rc)
+		plt_err("Failed to setup NIX Inline RQ mask, rc=%d", rc);
+
 exit:
 	mbox_put(mbox);
 	return rc;
--
2.34.1

[PATCH v2 07/18] net/cnxk: fix security flag for custom inbound SA

[Rahul Bhansali]

Avoid NIX_RX_OFFLOAD_SECURITY_F fast path flag for
custom_inb_sa config.

Fixes: 7eaa499dd0c2 ("net/cnxk: support CN20K inline IPsec session")
Cc: stable@dpdk.org

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/net/cnxk/cn20k_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index a7ef1dd386..20be35c0e0 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -35,7 +35,7 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
 	if (!dev->ptype_disable)
 		flags |= NIX_RX_OFFLOAD_PTYPE_F;

-	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
+	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && !dev->nix.custom_inb_sa)
 		flags |= NIX_RX_OFFLOAD_SECURITY_F;

 	return flags;
--
2.34.1

[PATCH v2 08/18] net/cnxk: add CPT code check for soft expiry

[Rahul Bhansali]

Add CPT ucode 0xF2 check as well for soft expiry handling.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.

 drivers/net/cnxk/cn20k_ethdev_sec.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index baa3423e28..bddc02eb3b 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -464,6 +464,7 @@ cn20k_eth_sec_post_event(struct rte_eth_dev *eth_dev, struct roc_ow_ipsec_outb_s
 			desc.subtype = RTE_ETH_EVENT_IPSEC_SA_BYTE_HARD_EXPIRY;
 		break;
 	case ROC_IE_OW_UCC_SUCCESS_SA_SOFTEXP_FIRST:
+	case ROC_IE_OW_UCC_SUCCESS_SA_SOFTEXP_AGAIN:
 		if (sa->w2.s.life_unit == ROC_IE_OW_SA_LIFE_UNIT_PKTS)
 			desc.subtype = RTE_ETH_EVENT_IPSEC_SA_PKT_EXPIRY;
 		else
--
2.34.1

[PATCH v2 09/18] net/cnxk: skip write SA for cn20k

[Rahul Bhansali]

For CN20k platform, write SA option is not required.
This will disable it and execute the hardware suggested
sequence to write SA context.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/net/cnxk/cn20k_ethdev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/cnxk/cn20k_ethdev.c b/drivers/net/cnxk/cn20k_ethdev.c
index 20be35c0e0..7e9e32f80b 100644
--- a/drivers/net/cnxk/cn20k_ethdev.c
+++ b/drivers/net/cnxk/cn20k_ethdev.c
@@ -948,8 +948,8 @@ cn20k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 	/* Register up msg callbacks for PTP information */
 	roc_nix_ptp_info_cb_register(&dev->nix, cn20k_nix_ptp_info_update_cb);

-	/* Use WRITE SA for inline IPsec */
-	dev->nix.use_write_sa = true;
+	/* Skip WRITE SA for inline IPsec */
+	dev->nix.use_write_sa = false;

 	return 0;
 }
--
2.34.1

[PATCH v2 10/18] net/cnxk: update NIX reassembly fast path

[Rahul Bhansali]

Update NIX reassembly fastpath as per CPT CSR changes
for CN20k platform.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/net/cnxk/cn20k_rx.h | 80 +++++++++++++++++++++++++++++--------
 1 file changed, 64 insertions(+), 16 deletions(-)

diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index 1944e507b0..ea8675be00 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -191,15 +191,13 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const rte_iova_t *iova_li
 	}

 	/* Remove the frag header by moving header 8 bytes forward */
-	ipv6_hdr->payload_len = rte_cpu_to_be_16(rlen - 8 - sizeof(struct rte_ipv6_hdr));
+	ipv6_hdr->payload_len = rte_cpu_to_be_16(rlen - sizeof(struct rte_ipv6_hdr));

 	/* tot_len is sum of all IP header's length before fragment header */
 	rte_memcpy(rte_pktmbuf_mtod_offset(head, void *, 8), rte_pktmbuf_mtod(head, void *),
 		   lc_off + tot_len);

-	head->data_len -= 8;
 	head->data_off += 8;
-	head->pkt_len -= 8;
 }

 static __rte_always_inline uint64_t
@@ -300,6 +298,7 @@ nix_update_match_id(const uint16_t match_id, uint64_t ol_flags, struct rte_mbuf
 	return ol_flags;
 }

+#if defined(RTE_ARCH_ARM64)
 static __rte_always_inline void
 nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint64_t rearm,
 		    uintptr_t cpth, uintptr_t sa_base, const uint64_t buf_sz, const uint16_t flags)
@@ -314,6 +313,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 	uint16_t rlen = hdr->w3.rlen;
 	const rte_iova_t *iova_list;
 	uint8_t sg_cnt = 1, nb_segs;
+	uint16x4_t fsz, sg_swap;
 	uint16_t later_skip = 0;
 	bool reas_fail = false;
 	const rte_iova_t *eol;
@@ -321,6 +321,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 	uint8_t ts_rx_off;
 	int dyn_off = 0;
 	uint16_t sg_len;
+	uint16_t l4_off;
 	int64_t len;
 	uintptr_t p;

@@ -341,7 +342,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		finfo = (const struct cpt_frag_info_s *)sg_base;
 		sg_base += num_frags ? (num_frags > 4 ? 32 : 16) : 0;
 		sg = *(uint64_t *)sg_base;
-		nb_segs = (sg >> 48) & 0x3;
+		nb_segs = (sg >> 14) & 0x3;
 		iova_list = (rte_iova_t *)(sg_base);
 		eol = iova_list + (hdr->w4.gthr_size << 2);
 		iova_list += 2;
@@ -357,11 +358,22 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 			if (hdr->w0.reas_sts ||
 			    (hdr->w0.err_sum && !roc_ie_ow_ucc_is_success(hdr->w3.uc_ccode))) {
 				reas_fail = true;
-				nxt_frag = (sg >> 51) & 0x3;
-				fsz_w1 = finfo->w1.u64 >> 16;
+				nxt_frag = (sg >> 11) & 0x3;
+				nxt_frag = ((nxt_frag << 1) | (nxt_frag >> 1)) & 0x3;
+
+				/* Reverse the order of fragment sizes */
+				fsz = vreinterpret_u16_u64(vdup_n_u64(finfo->w1.u64));
+				fsz = vrev64_u16(fsz);
+				fsz_w1 = vget_lane_u64(vreinterpret_u64_u16(fsz), 0) >> 16;
 				finfo++;
+				l4_off = ((cq_w5 >> 24) & 0xFF) - (cq_w5 & 0xFF);
 			}
 		}
+
+		/* sg byte swap */
+		sg_swap = vreinterpret_u16_u64(vdup_n_u64(sg));
+		sg_swap = vrev64_u16(sg_swap);
+		sg = vget_lane_u64(vreinterpret_u64_u16(sg_swap), 0);
 	} else {
 		sg = *(const uint64_t *)(rx + 1);
 		nb_segs = (sg >> 48) & 0x3;
@@ -376,8 +388,10 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		iova_list = ((const rte_iova_t *)(rx + 1)) + 2;
 	}

-	/* Update data len as per the segment size */
 	sg_len = sg & 0xFFFF;
+	sg = sg >> 16;
+
+	/* Update data len as per the segment size */
 	mbuf->data_len = sg_len;
 	mbuf->nb_segs = nb_segs;
 	head = mbuf;
@@ -387,7 +401,6 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		nix_sec_reass_first_frag_update(mbuf, iova_list - 1, cpth, cq_w1, cq_w5, rlen);

 	len -= sg_len;
-	sg = sg >> 16;
 	nb_segs--;

 	later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf;
@@ -404,6 +417,9 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6

 		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);

+		sg_len = sg & 0xFFFF;
+		sg = sg >> 16;
+
 		/* Process reassembly failure case */
 		if ((flags & NIX_RX_REAS_F) && unlikely(reas_fail && (nxt_frag & 1))) {
 			head->ol_flags |=
@@ -419,20 +435,25 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 			last_mbuf->next = NULL;
 			head = mbuf;
 			len = fsz_w1 & 0xFFFF;
-			head->pkt_len = len - ts_rx_off;
+			head->pkt_len = l4_off + len - ts_rx_off;
 			head->nb_segs = sg_cnt;
+			/* later frag size update*/
+			sg_len += l4_off;
 			data_off = rearm & 0xFFFF;
 			sg_cnt = 0;
 			nxt_frag = nxt_frag >> 1;
 			fsz_w1 = fsz_w1 >> 16;
-			if (--num_frags == 4)
-				fsz_w1 = finfo->w1.u64;
+			if (--num_frags == 4) {
+				/* Reverse the order of fragment sizes */
+				fsz = vreinterpret_u16_u64(vdup_n_u64(finfo->w1.u64));
+				fsz = vrev64_u16(fsz);
+				fsz_w1 = vget_lane_u64(vreinterpret_u64_u16(fsz), 0);
+			}
 		}

 		if ((flags & NIX_RX_REAS_F) && num_frags && !reas_fail)
 			data_off = *iova_list - (uint64_t)mbuf->buf_addr;

-		sg_len = sg & 0xFFFF;
 		if ((flags & NIX_RX_OFFLOAD_SECURITY_F) && !(flags & NIX_RX_REAS_F)) {
 			/* Adjust last mbuf data length with negative offset for
 			 * security pkts if needed.
@@ -443,7 +464,6 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		}

 		mbuf->data_len = sg_len;
-		sg = sg >> 16;
 		p = (uintptr_t)&mbuf->rearm_data;
 		*(uint64_t *)p = (rearm & ~0xFFFF) | data_off;

@@ -454,11 +474,25 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6

 		if (!nb_segs && (iova_list + 1 < eol)) {
 			sg = *(const uint64_t *)(iova_list);
-			nb_segs = (sg >> 48) & 0x3;
+
+			if ((flags & NIX_RX_SEC_REASSEMBLY_F) && (cq_w1 & BIT(11))) {
+				nb_segs = (sg >> 14) & 0x3;
+
+				if (unlikely(reas_fail)) {
+					nxt_frag = (sg >> 11) & 7;
+					nxt_frag = ((nxt_frag << 2) | (nxt_frag & 2) |
+						    (nxt_frag >> 2)) & 0x7;
+				}
+
+				sg_swap = vreinterpret_u16_u64(vdup_n_u64(sg));
+				sg_swap = vrev64_u16(sg_swap);
+				sg = vget_lane_u64(vreinterpret_u64_u16(sg_swap), 0);
+			} else {
+				nb_segs = (sg >> 48) & 0x3;
+			}
+
 			iova_list++;
 			head->nb_segs += nb_segs;
-			if ((flags & NIX_RX_REAS_F) && reas_fail)
-				nxt_frag = (sg >> 50) & 0x7;
 		}
 	}

@@ -468,6 +502,20 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		cnxk_ip_reassembly_dynfield(head, dyn_off)->nb_frags = 0;
 	}
 }
+#else
+static __rte_always_inline void
+nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint64_t rearm,
+		    uintptr_t cpth, uintptr_t sa_base, const uint64_t buf_sz, const uint16_t flags)
+{
+	RTE_SET_USED(rx);
+	RTE_SET_USED(mbuf);
+	RTE_SET_USED(rearm);
+	RTE_SET_USED(cpth);
+	RTE_SET_USED(sa_base);
+	RTE_SET_USED(buf_sz);
+	RTE_SET_USED(flags);
+}
+#endif

 static __rte_always_inline void
 cn20k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, struct rte_mbuf *mbuf,
--
2.34.1

[PATCH v2 11/18] net/cnxk: update aura batch free

[Rahul Bhansali]

From: Nithin Dabilpuram <ndabilpuram@marvell.com>

Modify aura batch free operation in RX fastpath as per
COUNT_EOT bits update in NPA_LF_AURA_BATCH_FREE0 CSR
for cn20k platform.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/net/cnxk/cn20k_rx.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index ea8675be00..eed8d59a14 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -112,7 +112,7 @@ nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff, uintptr_t aur

 	/* Update aura handle */
 	*(uint64_t *)laddr =
-		(((uint64_t)(loff & 0x1) << 32) | roc_npa_aura_handle_to_aura(aura_handle));
+		(((uint64_t)(loff & 0x3) << 32) | roc_npa_aura_handle_to_aura(aura_handle));

 	pa |= ((uint64_t)(loff >> 1) << 4);
 	roc_lmt_submit_steorl(lmt_id, pa);
@@ -1561,7 +1561,7 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 			/* Check if lmtline border is crossed and adjust lnum */
 			if (loff > 15) {
 				/* Update aura handle */
-				*(uint64_t *)(laddr - 8) = (((uint64_t)(15 & 0x1) << 32) |
+				*(uint64_t *)(laddr - 8) = (((uint64_t)(15 & 0x3) << 32) |
 							    roc_npa_aura_handle_to_aura(meta_aura));
 				loff = loff - 15;
 				shft += 3;
@@ -1582,7 +1582,7 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				uint64_t data = BIT_ULL(48) - 1;

 				/* Update aura handle */
-				*(uint64_t *)(laddr - 8) = (((uint64_t)(loff & 0x1) << 32) |
+				*(uint64_t *)(laddr - 8) = (((uint64_t)(loff & 0x3) << 32) |
 							    roc_npa_aura_handle_to_aura(meta_aura));

 				data = (data & ~(0x7UL << shft)) | (((uint64_t)loff >> 1) << shft);
@@ -1605,7 +1605,7 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c

 		/* Update aura handle */
 		*(uint64_t *)(laddr - 8) =
-			(((uint64_t)(loff & 0x1) << 32) | roc_npa_aura_handle_to_aura(meta_aura));
+			(((uint64_t)(loff & 0x3) << 32) | roc_npa_aura_handle_to_aura(meta_aura));

 		data = (data & ~(0x7UL << shft)) | (((uint64_t)loff >> 1) << shft);

--
2.34.1

[PATCH v2 12/18] net/cnxk: support out of place (OOP) in fastpath

[Rahul Bhansali]

For CN20k platform, support of Out-Of-Place (OOP) processing
is added in Rx fastpath.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated release notes and commit message.

 doc/guides/rel_notes/release_26_03.rst |   3 +
 drivers/net/cnxk/cn20k_ethdev_sec.c    |  22 +++--
 drivers/net/cnxk/cn20k_rx.h            | 119 +++++++++++++++++++++----
 3 files changed, 121 insertions(+), 23 deletions(-)

diff --git a/doc/guides/rel_notes/release_26_03.rst b/doc/guides/rel_notes/release_26_03.rst
index 5c2a4bb32e..f37c87fc5b 100644
--- a/doc/guides/rel_notes/release_26_03.rst
+++ b/doc/guides/rel_notes/release_26_03.rst
@@ -82,6 +82,9 @@ New Features
   * NEA5, NIA5, NCA5: AES 256 confidentiality, integrity and AEAD modes.
   * NEA6, NIA6, NCA6: ZUC 256 confidentiality, integrity and AEAD modes.

+* **Updated Marvell cnxk net driver.**
+
+  * Added Out-Of-Place support for CN20K SoC.

 Removed Items
 -------------
diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index bddc02eb3b..c6a51f99f5 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -9,6 +9,7 @@
 #include <rte_security_driver.h>

 #include <cn20k_ethdev.h>
+#include <cn20k_rx.h>
 #include <cnxk_security.h>
 #include <roc_priv.h>

@@ -810,10 +811,6 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
 			inb_sa_dptr->w0.s.count_mib_pkts = 1;
 		}

-		/* Enable out-of-place processing */
-		if (ipsec->options.ingress_oop)
-			inb_sa_dptr->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_FULL;
-
 		/* Prepare session priv */
 		sess_priv.inb_sa = 1;
 		sess_priv.sa_idx = ipsec->spi & spi_mask;
@@ -843,6 +840,13 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
 		if (ipsec->options.ingress_oop)
 			dev->inb.nb_oop++;

+		/* Update function pointer to handle OOP sessions */
+		if (dev->inb.nb_oop && !(dev->rx_offload_flags & NIX_RX_REAS_F)) {
+			dev->rx_offload_flags |= NIX_RX_REAS_F;
+			cn20k_eth_set_rx_function(eth_dev);
+			if (cnxk_ethdev_rx_offload_cb)
+				cnxk_ethdev_rx_offload_cb(eth_dev->data->port_id, NIX_RX_REAS_F);
+		}
 	} else {
 		struct roc_ow_ipsec_outb_sa *outb_sa, *outb_sa_dptr;
 		struct cn20k_outb_priv_data *outb_priv;
@@ -986,6 +990,12 @@ cn20k_eth_sec_session_destroy(void *device, struct rte_security_session *sess)
 		if (eth_sec->inb_oop)
 			dev->inb.nb_oop--;

+		/* Clear offload flags if was used by OOP */
+		if (!dev->inb.nb_oop && !dev->inb.reass_en &&
+		    dev->rx_offload_flags & NIX_RX_REAS_F) {
+			dev->rx_offload_flags &= ~NIX_RX_REAS_F;
+			cn20k_eth_set_rx_function(eth_dev);
+		}
 	} else {
 		/* Disable SA */
 		sa_dptr = dev->outb.sa_dptr;
@@ -1064,10 +1074,6 @@ cn20k_eth_sec_session_update(void *device, struct rte_security_session *sess,
 			inb_sa_dptr->w0.s.count_mib_pkts = 1;
 		}

-		/* Enable out-of-place processing */
-		if (ipsec->options.ingress_oop)
-			inb_sa_dptr->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_FULL;
-
 		rc = roc_nix_inl_ctx_write(&dev->nix, inb_sa_dptr, eth_sec->sa, eth_sec->inb,
 					   sizeof(struct roc_ow_ipsec_inb_sa));
 		if (rc)
diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h
index eed8d59a14..83c222c53c 100644
--- a/drivers/net/cnxk/cn20k_rx.h
+++ b/drivers/net/cnxk/cn20k_rx.h
@@ -200,6 +200,38 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const rte_iova_t *iova_li
 	head->data_off += 8;
 }

+static __rte_always_inline struct rte_mbuf *
+nix_sec_oop_process(uintptr_t cpth, uint64_t buf_sz)
+{
+	const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)cpth;
+	uint32_t offset = hdr->w2.ptr_offset;
+	struct rte_mbuf *inner, *mbuf;
+	union nix_rx_parse_u *rx;
+	rte_iova_t *iova_list;
+	uint64_t addr;
+
+	iova_list = (rte_iova_t *)(cpth + (offset ? (offset << 5) : 256)) + 1;
+	addr = *iova_list;
+	offset = addr % (buf_sz & 0xFFFFFFFF);
+	mbuf = (struct rte_mbuf *)(addr - offset + (buf_sz >> 32));
+
+	rx = (union nix_rx_parse_u *)(((uintptr_t)(mbuf + 1)) + 8);
+	mbuf->pkt_len = rx->pkt_lenm1 + 1;
+	mbuf->data_len = rx->pkt_lenm1 + 1;
+	mbuf->data_off = addr - (uint64_t)mbuf->buf_addr;
+
+	/* Pointers will be alternate encrypted-decrypted in gather list */
+	iova_list++;
+	addr = *iova_list;
+	inner = (struct rte_mbuf *)(addr - offset + (buf_sz >> 32));
+
+	/* Mark original mbuf as get */
+	RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&mbuf, 1, 1);
+
+	*rte_security_oop_dynfield(inner) = mbuf;
+	return inner;
+}
+
 static __rte_always_inline uint64_t
 nix_sec_meta_to_mbuf_sc(uint64_t cq_w5, uint64_t cpth, const uint64_t sa_base,
 			struct rte_mbuf *mbuf, uint16_t *len, uint64_t *mbuf_init,
@@ -318,10 +350,11 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 	bool reas_fail = false;
 	const rte_iova_t *eol;
 	uint16_t data_off = 0;
+	bool is_oop = false;
+	uint16_t l4_off = 0;
 	uint8_t ts_rx_off;
 	int dyn_off = 0;
 	uint16_t sg_len;
-	uint16_t l4_off;
 	int64_t len;
 	uintptr_t p;

@@ -332,7 +365,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		uint64_t sg_base;

 		/* Check if there are no SG's */
-		if (!hdr->w4.gthr_size && ((flags & NIX_RX_REAS_F) || !hdr->w4.sctr_size))
+		if (!hdr->w4.gthr_size)
 			return;

 		cq_w5 = *((const uint64_t *)rx + 4);
@@ -342,7 +375,12 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		finfo = (const struct cpt_frag_info_s *)sg_base;
 		sg_base += num_frags ? (num_frags > 4 ? 32 : 16) : 0;
 		sg = *(uint64_t *)sg_base;
+
+		is_oop = (hdr->w4.l4_chksum_type == 0) && (hdr->w4.l4_chksum == 1);
 		nb_segs = (sg >> 14) & 0x3;
+		if (is_oop && nb_segs <= 2)
+			return;
+
 		iova_list = (rte_iova_t *)(sg_base);
 		eol = iova_list + (hdr->w4.gthr_size << 2);
 		iova_list += 2;
@@ -374,6 +412,12 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		sg_swap = vreinterpret_u16_u64(vdup_n_u64(sg));
 		sg_swap = vrev64_u16(sg_swap);
 		sg = vget_lane_u64(vreinterpret_u64_u16(sg_swap), 0);
+
+		/* For Non inplace, first SG pointer will be original encrypted,
+		 * whereas input mbuf is decrypted one. So need to update mbuf pointer
+		 * in order to process SG list accordingly.
+		 */
+		mbuf = is_oop ? *rte_security_oop_dynfield(mbuf) : mbuf;
 	} else {
 		sg = *(const uint64_t *)(rx + 1);
 		nb_segs = (sg >> 48) & 0x3;
@@ -397,17 +441,17 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 	head = mbuf;

 	/* Update IP header */
-	if ((flags & NIX_RX_REAS_F) && num_frags && !reas_fail)
+	if ((flags & NIX_RX_REAS_F) && num_frags && !reas_fail && !is_oop)
 		nix_sec_reass_first_frag_update(mbuf, iova_list - 1, cpth, cq_w1, cq_w5, rlen);

-	len -= sg_len;
+	len -= is_oop ? 0 : sg_len;
 	nb_segs--;

 	later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf;

 	while (nb_segs) {
 		last_mbuf = mbuf;
-		if ((flags & NIX_RX_REAS_F) && num_frags) {
+		if ((flags & NIX_RX_REAS_F) && (num_frags || is_oop)) {
 			offset = (*iova_list) % (buf_sz & 0xFFFFFFFF);
 			mbuf->next = (struct rte_mbuf *)((*iova_list) - offset + (buf_sz >> 32));
 		} else {
@@ -451,12 +495,14 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 			}
 		}

-		if ((flags & NIX_RX_REAS_F) && num_frags && !reas_fail)
+		if ((flags & NIX_RX_REAS_F) && ((num_frags && !reas_fail) || is_oop))
 			data_off = *iova_list - (uint64_t)mbuf->buf_addr;

-		if ((flags & NIX_RX_OFFLOAD_SECURITY_F) && !(flags & NIX_RX_REAS_F)) {
+		if (((flags & NIX_RX_OFFLOAD_SECURITY_F) && !(flags & NIX_RX_REAS_F)) ||
+		    (is_oop && (sg_cnt % 2))) {
 			/* Adjust last mbuf data length with negative offset for
 			 * security pkts if needed.
+			 * For OOP, will correct mbuf length of decrypted pkt.
 			 */
 			len -= sg_len;
 			sg_len = (len > 0) ? sg_len : (sg_len + len);
@@ -496,6 +542,29 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint6
 		}
 	}

+	if (unlikely(is_oop)) {
+		struct rte_mbuf *o_mbuf;
+
+		/* mbuf chain will have all pointers of encrypted + decrypted
+		 * alternatively. So will need to sort it.
+		 */
+		mbuf = head;
+		o_mbuf = head->next;
+		nb_segs = head->nb_segs;
+		mbuf->nb_segs = nb_segs / 2;
+		o_mbuf->nb_segs = nb_segs / 2;
+		nb_segs -= 2;
+		while (unlikely(nb_segs && (nb_segs % 2 == 0))) {
+			mbuf->next = o_mbuf->next;
+			o_mbuf->next = o_mbuf->next->next;
+			mbuf = mbuf->next;
+			o_mbuf = o_mbuf->next;
+			nb_segs -= 2;
+		}
+		mbuf->next = NULL;
+		o_mbuf->next = NULL;
+	}
+
 	/* Update for last failure fragment */
 	if ((flags & NIX_RX_REAS_F) && reas_fail) {
 		cnxk_ip_reassembly_dynfield(head, dyn_off)->next_frag = NULL;
@@ -648,6 +717,8 @@ cn20k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, co
 	uintptr_t cpth = 0;
 	uint16_t lmt_id;
 	uint64_t laddr;
+	uint64_t w4;
+	bool is_oop;

 	nb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);

@@ -685,7 +756,12 @@ cn20k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, co
 				 */
 				*(uint64_t *)(laddr + (loff << 3)) = (uint64_t)mbuf;
 				loff = loff + 1;
-				mbuf = (struct rte_mbuf *)(*(uint64_t *)(cpth + 8) - m_sz);
+				w4 = *(uint64_t *)(cpth + 32);
+				is_oop = !((w4 >> 32) & 0x3) && ((w4 & 0xffffffff) == 1);
+				if ((flags & NIX_RX_REAS_F) && is_oop)
+					mbuf = nix_sec_oop_process(cpth, buf_sz);
+				else
+					mbuf = (struct rte_mbuf *)(*(uint64_t *)(cpth + 8) - m_sz);

 				/* Mark inner mbuf as get */
 				RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
@@ -815,11 +891,21 @@ cn20k_nix_flush_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pk

 static __rte_always_inline void
 nix_sec_meta_to_mbuf(uintptr_t inb_sa, uintptr_t cpth, struct rte_mbuf **inner, uint64_t *ol_flags,
-		     const uint16_t flags, uint64x2_t *rearm)
+		     const uint16_t flags, uint64x2_t *rearm, uint64_t buf_sz)
 {
 	const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)cpth;
-	struct rte_mbuf *inner_m = inner[0];
 	struct cn20k_inb_priv_data *inb_priv;
+	struct rte_mbuf *inner_m;
+	uint64_t w4;
+	bool is_oop;
+
+	w4 = *(uint64_t *)(cpth + 32);
+	is_oop = !((w4 >> 32) & 0x3) && ((w4 & 0xffffffff) == 1);
+
+	if ((flags & NIX_RX_REAS_F) && is_oop)
+		inner[0] = nix_sec_oop_process(cpth, buf_sz);
+
+	inner_m = inner[0];

 	/* Clear checksum flags */
 	*ol_flags &= ~(RTE_MBUF_F_RX_L4_CKSUM_MASK | RTE_MBUF_F_RX_IP_CKSUM_MASK);
@@ -1328,7 +1414,8 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				f0 = vsetq_lane_u16(len, f0, 2);
 				f0 = vsetq_lane_u16(len, f0, 4);

-				nix_sec_meta_to_mbuf(sa, cpth0, &mbuf0, &ol_flags0, flags, &rearm0);
+				nix_sec_meta_to_mbuf(sa, cpth0, &mbuf0, &ol_flags0, flags, &rearm0,
+						     buf_sz);
 				mbuf01 = vsetq_lane_u64((uintptr_t)mbuf0, mbuf01, 0);
 				code = vget_lane_u8(ucc, 1);
 				ol_flags0 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :
@@ -1344,7 +1431,6 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c

 				cpth1 = (uintptr_t)mbuf1 + d_off;

-				/* Free meta to aura */
 				NIX_PUSH_META_TO_FREE(mbuf1, laddr, &loff);
 				mbuf1 = (struct rte_mbuf *)wqe;

@@ -1352,7 +1438,8 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				f1 = vsetq_lane_u16(len, f1, 2);
 				f1 = vsetq_lane_u16(len, f1, 4);

-				nix_sec_meta_to_mbuf(sa, cpth1, &mbuf1, &ol_flags1, flags, &rearm1);
+				nix_sec_meta_to_mbuf(sa, cpth1, &mbuf1, &ol_flags1, flags, &rearm1,
+						     buf_sz);
 				mbuf01 = vsetq_lane_u64((uintptr_t)mbuf1, mbuf01, 1);
 				code = vget_lane_u8(ucc, 3);
 				ol_flags1 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :
@@ -1375,7 +1462,8 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				f2 = vsetq_lane_u16(len, f2, 2);
 				f2 = vsetq_lane_u16(len, f2, 4);

-				nix_sec_meta_to_mbuf(sa, cpth2, &mbuf2, &ol_flags2, flags, &rearm2);
+				nix_sec_meta_to_mbuf(sa, cpth2, &mbuf2, &ol_flags2, flags, &rearm2,
+						     buf_sz);
 				mbuf23 = vsetq_lane_u64((uintptr_t)mbuf2, mbuf23, 0);
 				code = vget_lane_u8(ucc, 5);
 				ol_flags2 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :
@@ -1398,7 +1486,8 @@ cn20k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, c
 				f3 = vsetq_lane_u16(len, f3, 2);
 				f3 = vsetq_lane_u16(len, f3, 4);

-				nix_sec_meta_to_mbuf(sa, cpth3, &mbuf3, &ol_flags3, flags, &rearm3);
+				nix_sec_meta_to_mbuf(sa, cpth3, &mbuf3, &ol_flags3, flags, &rearm3,
+						     buf_sz);
 				mbuf23 = vsetq_lane_u64((uintptr_t)mbuf3, mbuf23, 1);
 				code = vget_lane_u8(ucc, 7);
 				ol_flags3 |= code ? (code > 1 ? ((uint64_t)code) << 1 : 0) :
--
2.34.1

[PATCH v2 13/18] event/cnxk: support out of place (OOP) in fastpath

[Rahul Bhansali]

For CN20k platform, support of Out-Of-Place (OOP) processing
is added in event Rx fastpath.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/event/cnxk/cn20k_eventdev.c | 18 +++++++++++++++++
 drivers/event/cnxk/cn20k_worker.h   | 30 +++++++++++++++++++++--------
 2 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c
index 1c5d927239..ff3aaac16a 100644
--- a/drivers/event/cnxk/cn20k_eventdev.c
+++ b/drivers/event/cnxk/cn20k_eventdev.c
@@ -710,6 +710,23 @@ cn20k_sso_tstamp_hdl_update(uint16_t port_id, uint16_t flags, bool ptp_en)
 	eventdev_fops_tstamp_update(event_dev);
 }

+static void
+cn20k_sso_rx_offload_cb(uint16_t port_id, uint64_t flags)
+{
+	struct rte_eth_dev *dev = &rte_eth_devices[port_id];
+	struct cnxk_eth_dev *cnxk_eth_dev = dev->data->dev_private;
+	struct rte_eventdev *event_dev = cnxk_eth_dev->evdev_priv;
+	struct cnxk_sso_evdev *evdev;
+
+	if (event_dev == NULL)
+		return;
+
+	evdev = cnxk_sso_pmd_priv(event_dev);
+	evdev->rx_offloads |= flags;
+	cn20k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
+	eventdev_fops_tstamp_update(event_dev);
+}
+
 static int
 cn20k_sso_rxq_enable(struct cnxk_eth_dev *cnxk_eth_dev, uint16_t rq_id, uint16_t port_id,
 		     const struct rte_event_eth_rx_adapter_queue_conf *queue_conf, int agq)
@@ -1241,6 +1258,7 @@ cn20k_sso_init(struct rte_eventdev *event_dev)
 		return rc;
 	}

+	cnxk_ethdev_rx_offload_cb_register(cn20k_sso_rx_offload_cb);
 	event_dev->dev_ops = &cn20k_sso_dev_ops;
 	/* For secondary processes, the primary has done all the work */
 	if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
diff --git a/drivers/event/cnxk/cn20k_worker.h b/drivers/event/cnxk/cn20k_worker.h
index 608f93dcd4..6442113e09 100644
--- a/drivers/event/cnxk/cn20k_worker.h
+++ b/drivers/event/cnxk/cn20k_worker.h
@@ -18,15 +18,11 @@
 static __rte_always_inline void
 cn20k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf, uint8_t port_id, const uint32_t tag,
 		  const uint32_t flags, const void *const lookup_mem, uintptr_t cpth,
-		  uintptr_t sa_base)
+		  uintptr_t sa_base, uint64_t buf_sz)
 {
 	const uint64_t mbuf_init =
 		0x100010000ULL | RTE_PKTMBUF_HEADROOM | (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
 	struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
-	uint64_t buf_sz = 0;
-
-	if (flags & NIX_RX_REAS_F)
-		buf_sz = cnxk_nix_inl_bufsize_get(port_id, lookup_mem);

 	cn20k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag, (struct rte_mbuf *)mbuf, lookup_mem,
 			      mbuf_init | ((uint64_t)port_id) << 48, cpth, sa_base, buf_sz, flags);
@@ -66,6 +62,8 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, struc
 	uint64_t buf_sz = 0;
 	uintptr_t cpth = 0;
 	uint8_t loff = 0;
+	uint64_t w4;
+	bool is_oop;
 	int i;

 	mbuf_init |= ((uint64_t)port_id) << 48;
@@ -136,7 +134,12 @@ cn20k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, struc
 				 */
 				*(uint64_t *)(laddr + (loff << 3)) = (uint64_t)mbuf;
 				loff = loff + 1;
-				mbuf = (struct rte_mbuf *)(*(uint64_t *)(cpth + 8) - m_sz);
+				w4 = *(uint64_t *)(cpth + 32);
+				is_oop = !((w4 >> 32) & 0x3) && ((w4 & 0xffffffff) == 1);
+				if ((flags & NIX_RX_REAS_F) && is_oop)
+					mbuf = nix_sec_oop_process(cpth, buf_sz);
+				else
+					mbuf = (struct rte_mbuf *)(*(uint64_t *)(cpth + 8) - m_sz);
 				/* Mark inner mbuf as get */
 				RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 			}
@@ -176,6 +179,7 @@ cn20k_sso_hws_post_process(struct cn20k_sso_hws *ws, uint64_t *u64, const uint32
 		u64[1] = cn20k_cpt_crypto_adapter_vector_dequeue(u64[1]);
 	} else if (CNXK_EVENT_TYPE_FROM_TAG(u64[0]) == RTE_EVENT_TYPE_ETHDEV) {
 		uint8_t port = CNXK_SUB_EVENT_FROM_TAG(u64[0]);
+		uint64_t buf_sz = 0;
 		uintptr_t cpth = 0;
 		uint64_t mbuf;

@@ -194,6 +198,8 @@ cn20k_sso_hws_post_process(struct cn20k_sso_hws *ws, uint64_t *u64, const uint32
 			uint8_t loff = 0;
 			uint16_t d_off;
 			uint64_t cq_w1;
+			uint64_t w4;
+			bool is_oop;

 			m = (struct rte_mbuf *)mbuf;
 			d_off = (*(uint64_t *)(u64[1] + 72)) - (uintptr_t)m;
@@ -210,12 +216,20 @@ cn20k_sso_hws_post_process(struct cn20k_sso_hws *ws, uint64_t *u64, const uint32
 				/* Mark meta mbuf as put */
 				RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);

+				if (flags & NIX_RX_REAS_F)
+					buf_sz = cnxk_nix_inl_bufsize_get(port, lookup_mem);
 				/* Store meta in lmtline to free
 				 * Assume all meta's from same aura.
 				 */
 				*(uint64_t *)((uintptr_t)&iova + (loff << 3)) = (uint64_t)m;
 				loff = loff + 1;
-				mbuf = (uint64_t)(*(uint64_t *)(cpth + 8) - m_sz);
+				w4 = *(uint64_t *)(cpth + 32);
+				is_oop = !((w4 >> 32) & 0x3) && ((w4 & 0xffffffff) == 1);
+				if ((flags & NIX_RX_REAS_F) && is_oop)
+					mbuf = (uint64_t)nix_sec_oop_process(cpth, buf_sz);
+				else
+					mbuf = (uint64_t)(*(uint64_t *)(cpth + 8) - m_sz);
+
 				/* Mark inner mbuf as get */
 				RTE_MEMPOOL_CHECK_COOKIES(((struct rte_mbuf *)mbuf)->pool,
 							  (void **)&mbuf, 1, 1);
@@ -225,7 +239,7 @@ cn20k_sso_hws_post_process(struct cn20k_sso_hws *ws, uint64_t *u64, const uint32

 		u64[0] = CNXK_CLR_SUB_EVENT(u64[0]);
 		cn20k_wqe_to_mbuf(u64[1], mbuf, port, u64[0] & 0xFFFFF, flags, ws->lookup_mem, cpth,
-				  sa_base);
+				  sa_base, buf_sz);
 		if (flags & NIX_RX_OFFLOAD_TSTAMP_F)
 			cn20k_sso_process_tstamp(u64[1], mbuf, ws->tstamp[port]);
 		u64[1] = mbuf;
--
2.34.1

[PATCH v2 14/18] common/cnxk: flow rule config for non-inplace

[Rahul Bhansali]

Adds flow rule for non-inplace (Out-Of-Place) security action
configuration.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.

 drivers/common/cnxk/roc_npc.c | 13 ++++++++++++-
 drivers/common/cnxk/roc_npc.h |  3 +++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 7846913417..acf0007e05 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -613,10 +613,12 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 	const struct roc_npc_action_mark *act_mark;
 	const struct roc_npc_action_meter *act_mtr;
 	const struct roc_npc_action_queue *act_q;
+	const struct roc_npc_sec_action *sec_act;
 	const struct roc_npc_action_vf *vf_act;
 	uint8_t has_spi_to_sa_act = 0;
 	int sel_act, req_act = 0;
 	uint16_t pf_func, vf_id;
+	bool is_non_inp = false;
 	int errcode = 0;
 	int mark = 0;
 	int rq = 0;
@@ -704,6 +706,15 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 			 *  session_protocol ==
 			 *    NPC_SECURITY_PROTOCOL_IPSEC
 			 */
+
+			if (!actions->no_sec_action) {
+				sec_act = (const struct roc_npc_sec_action *)actions->conf;
+				sec_action = actions;
+				is_non_inp = sec_act ? sec_act->is_non_inp : false;
+			} else {
+				is_non_inp = actions->is_non_inp;
+			}
+
 			req_act |= ROC_NPC_ACTION_TYPE_SEC;
 			rq = 0;
 			roc_nix = roc_npc->roc_nix;
@@ -724,7 +735,6 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,

 			if (roc_nix_inl_dev_is_probed())
 				flow->is_inline_dev = 1;
-			sec_action = actions;
 			break;
 		case ROC_NPC_ACTION_TYPE_VLAN_STRIP:
 			req_act |= ROC_NPC_ACTION_TYPE_VLAN_STRIP;
@@ -931,6 +941,7 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 			flow->npc_action |= (uint64_t)rq << 20;
 			flow->npc_action2 =
 				roc_nix_inl_inb_ipsec_profile_id_get(roc_nix, true) << 8;
+			flow->npc_action2 |= is_non_inp ? (1ULL << 15) : 0;
 		} else {
 			flow->npc_action = NIX_RX_ACTIONOP_UCAST_IPSEC;
 			flow->npc_action |= (uint64_t)rq << 20;
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index b7565806c0..62385e4481 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -204,6 +204,8 @@ struct roc_npc_action {
 	enum roc_npc_action_type type; /**< Action type. */
 	const void *conf;	       /**< Pointer to action configuration object. */
 	uint16_t rss_repte_pf_func;    /**< Per flow tmp var for rss representee pffunc */
+	bool is_non_inp;	       /**< Non inplace config */
+	bool no_sec_action;	       /**< No security action */
 };

 struct roc_npc_action_sample {
@@ -282,6 +284,7 @@ struct roc_npc_sec_action {
 	 * XOR
 	 */
 	enum roc_npc_sec_action_alg alg;
+	bool is_non_inp;
 };

 struct roc_npc_attr {
--
2.34.1

[PATCH v2 15/18] net/cnxk: enable PDB in IPsec outbound path

[Rahul Bhansali]

From: Nithin Dabilpuram <ndabilpuram@marvell.com>

Enabled PDB in IPsec outbound datapath.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
Changes in v2: No change.

 drivers/net/cnxk/cn20k_tx.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/cnxk/cn20k_tx.h b/drivers/net/cnxk/cn20k_tx.h
index 9e48744831..8e64d2e352 100644
--- a/drivers/net/cnxk/cn20k_tx.h
+++ b/drivers/net/cnxk/cn20k_tx.h
@@ -520,6 +520,7 @@ cn20k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1,
 		nixtx += 16;

 		w0 |= cn20k_nix_tx_ext_subs(flags) + 1ULL;
+		w0 |= sess_priv.chksum ? BIT_ULL(63) : BIT_ULL(62);
 		dptr += l2_len;
 		ucode_cmd[1] = dptr;
 		*cmd1 = vsetq_lane_u16(pkt_len + dlen_adj, *cmd1, 0);
@@ -660,6 +661,7 @@ cn20k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, uin
 		nixtx += 16;

 		w0 |= cn20k_nix_tx_ext_subs(flags) + 1ULL;
+		w0 |= sess_priv.chksum ? BIT_ULL(63) : BIT_ULL(62);
 		dptr += l2_len;
 		ucode_cmd[1] = dptr;
 		sg->seg1_size = pkt_len + dlen_adj;
--
2.34.1

[PATCH v2 16/18] common/cnxk: initialize CPT LF for CQ config

[Rahul Bhansali]

From: Rakesh Kudurumalla <rkudurumalla@marvell.com>

Initialize inline outbound CPT LF for CPT CQ
configurations.

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
Changes in v2: No change.

 drivers/common/cnxk/roc_nix_inl.c | 42 +++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 8 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 917c2c669a..86d571c6e2 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1573,8 +1573,18 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 		lf->msixoff = nix->cpt_msixoff[i];
 		lf->pci_dev = nix->pci_dev;

+		if (roc_feature_nix_has_cpt_cq_support()) {
+			if (inl_dev && inl_dev->cpt_cq_ena) {
+				lf->dq_ack_ena = true;
+				lf->cpt_cq_ena = true;
+				lf->cq_entry_size = 0;
+				lf->cq_all = 0;
+				lf->cq_size = lf->nb_desc;
+			}
+		}
+
 		/* Setup CPT LF instruction queue */
-		rc = cpt_lf_init(lf, false);
+		rc = cpt_lf_init(lf, lf->cpt_cq_ena);
 		if (rc) {
 			plt_err("Failed to initialize CPT LF, rc=%d", rc);
 			goto lf_fini;
@@ -1591,6 +1601,13 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)

 		/* Enable IQ */
 		roc_cpt_iq_enable(lf);
+		/* Enable CQ */
+		if (lf->cpt_cq_ena) {
+			rc = cpt_lf_register_irqs(lf, cpt_lf_misc_irq, nix_inl_cpt_done_irq);
+			if (rc)
+				goto lf_fini;
+			roc_cpt_cq_enable(lf);
+		}
 	}

 	if (!roc_nix->ipsec_out_max_sa)
@@ -1635,6 +1652,9 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	nix->outb_se_ring_base =
 		roc_nix->port_id * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS;

+	/* Fetch engine capabilities */
+	nix_inl_eng_caps_get(nix);
+
 	if (inl_dev == NULL || !inl_dev->set_soft_exp_poll) {
 		nix->outb_se_ring_cnt = 0;
 		return 0;
@@ -1658,13 +1678,15 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 		}
 	}

-	/* Fetch engine capabilities */
-	nix_inl_eng_caps_get(nix);
 	return 0;

 lf_fini:
-	for (j = i - 1; j >= 0; j--)
-		cpt_lf_fini(&lf_base[j], false);
+	for (j = i - 1; j >= 0; j--) {
+		lf = &lf_base[j];
+		cpt_lf_fini(lf, lf->cpt_cq_ena);
+		if (lf->cpt_cq_ena)
+			cpt_lf_unregister_irqs(lf, cpt_lf_misc_irq, nix_inl_cpt_done_irq);
+	}
 	plt_free(lf_base);
 lf_free:
 	rc |= cpt_lfs_free(dev);
@@ -1681,6 +1703,7 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix)
 	struct idev_cfg *idev = idev_get_cfg();
 	struct dev *dev = &nix->dev;
 	struct nix_inl_dev *inl_dev;
+	struct roc_cpt_lf *lf;
 	uint64_t *ring_base;
 	int i, rc, ret = 0;

@@ -1690,9 +1713,12 @@ roc_nix_inl_outb_fini(struct roc_nix *roc_nix)
 	nix->inl_outb_ena = false;

 	/* Cleanup CPT LF instruction queue */
-	for (i = 0; i < nix->nb_cpt_lf; i++)
-		cpt_lf_fini(&lf_base[i], false);
-
+	for (i = 0; i < nix->nb_cpt_lf; i++) {
+		lf = &lf_base[i];
+		cpt_lf_fini(lf, lf->cpt_cq_ena);
+		if (lf->cpt_cq_ena)
+			cpt_lf_unregister_irqs(lf, cpt_lf_misc_irq, nix_inl_cpt_done_irq);
+	}
 	/* Free LF resources */
 	rc = cpt_lfs_free(dev);
 	if (rc)
--
2.34.1

[PATCH v2 17/18] common/cnxk: fix CPT CQ roll over handling

[Rahul Bhansali]

This fixes the handling of CPT CQ ring roll over case.

Fixes: a7d64a7740e0 ("net/cnxk: handle soft expiry")
Cc: stable@dpdk.org

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/common/cnxk/roc_cpt.c             |  2 +-
 drivers/common/cnxk/roc_cpt.h             |  1 +
 drivers/common/cnxk/roc_nix_inl.c         |  1 +
 drivers/common/cnxk/roc_nix_inl_dev_irq.c | 18 ++++++++++++------
 4 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 83e0c9896b..63419884ac 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -712,7 +712,7 @@ cpt_lf_cq_init(struct roc_cpt_lf *lf)

 	lf_cq_base.s.addr = addr >> 7;
 	plt_write64(lf_cq_base.u, lf->rbase + CPT_LF_CQ_BASE);
-	lf_cq_size.s.size = PLT_ALIGN(len, ROC_ALIGN);
+	lf_cq_size.s.size = lf->cq_size;
 	plt_write64(lf_cq_size.u, lf->rbase + CPT_LF_CQ_SIZE);

 	return 0;
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 67956758be..7547d0b020 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -159,6 +159,7 @@ struct roc_cpt_lf {
 	bool cpt_cq_ena;
 	uint8_t cq_entry_size;
 	uint32_t cq_size;
+	uint32_t cq_head;
 	/* End of Input parameters */
 	struct plt_pci_device *pci_dev;
 	struct dev *dev;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 86d571c6e2..aad2631673 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -1580,6 +1580,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 				lf->cq_entry_size = 0;
 				lf->cq_all = 0;
 				lf->cq_size = lf->nb_desc;
+				lf->cq_head = 1;
 			}
 		}

diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
index 1c4822925c..89155a1f7d 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
@@ -57,8 +57,8 @@ nix_inl_cpt_cq_cb(struct roc_cpt_lf *lf)
 	union cpt_lf_cq_ptr cq_ptr;
 	struct cpt_cq_s *cq_s;
 	uint8_t fmt_msk = 0x3;
-	uint64_t nq_ptr;
-	uint32_t count;
+	uint32_t count, head;
+	uint32_t nq_ptr;
 	uint64_t i;

 	if (idev)
@@ -69,14 +69,15 @@ nix_inl_cpt_cq_cb(struct roc_cpt_lf *lf)
 		return;
 	}

+	head = lf->cq_head;
 	cq_base.u = plt_read64(lf->rbase + CPT_LF_CQ_BASE);
 	cq_ptr.u = plt_read64(lf->rbase + CPT_LF_CQ_PTR);
 	count = cq_ptr.s.count;
-
-	nq_ptr = (((cq_base.s.addr << 7)) + ((cq_ptr.s.nq_ptr - count) << 5));
-	cq_s = (struct cpt_cq_s *)nq_ptr;
+	nq_ptr = cq_ptr.s.nq_ptr;

 	for (i = 0; i < count; i++) {
+		cq_s = (struct cpt_cq_s *)(uintptr_t)(((cq_base.s.addr << 7)) + (head << 5));
+
 		if (cq_s->w0.s.uc_compcode && cq_s->w0.s.compcode) {
 			switch (cq_s->w2.s.fmt & fmt_msk) {
 			case WQE_PTR_CPTR:
@@ -93,8 +94,13 @@ nix_inl_cpt_cq_cb(struct roc_cpt_lf *lf)
 			inl_dev->work_cb(&tmp, sa, NIX_INL_CPT_CQ, (void *)cq_s, port_id);
 		}
 done:
-		cq_s = cq_s + 1;
+		head = (head + 1) % lf->cq_size;
 	}
+
+	lf->cq_head = head;
+	if (unlikely(nq_ptr != head))
+		plt_err("CPT LF[%d] CQ head %d != NQ ptr %d", lf->lf_id, head, nq_ptr);
+
 	/* Acknowledge the number of completed requests */
 	plt_write64(count, lf->rbase + CPT_LF_DONE_ACK);
 }
--
2.34.1

[PATCH v2 18/18] common/cnxk: fix duplicate branch compiler warning

[Rahul Bhansali]

With compiler option '-Wduplicated-branches', getting few
warnings such as "this condition has identical branches".

Macros are updated to address these warnings.

Bugzilla ID: 1811
Fixes: 0d9e323bacf0 ("common/cnxk: support for CN20K inline IPsec")
Fixes: c045d2e5cbbc ("common/cnxk: add CPT configuration")
Cc: stable@dpdk.org

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: Updated commit message.

 drivers/common/cnxk/hw/rvu.h          |  2 ++
 drivers/common/cnxk/roc_cpt.c         |  7 +++----
 drivers/common/cnxk/roc_nix_inl.c     | 25 +++++++++----------------
 drivers/common/cnxk/roc_nix_inl_dev.c |  6 +-----
 drivers/common/cnxk/roc_nix_inl_dp.h  |  3 +++
 drivers/common/cnxk/roc_nix_priv.h    |  4 ++--
 6 files changed, 20 insertions(+), 27 deletions(-)

diff --git a/drivers/common/cnxk/hw/rvu.h b/drivers/common/cnxk/hw/rvu.h
index ed2ba996e0..6f02d1e3d2 100644
--- a/drivers/common/cnxk/hw/rvu.h
+++ b/drivers/common/cnxk/hw/rvu.h
@@ -105,6 +105,8 @@
 #define RVU_VF_MBOX_REGION		 (0xc0000ull) /* [CN10K, .) */
 #define RVU_VF_MSIX_PBAX(a)		 (0xf0000ull | (uint64_t)(a) << 3)

+#define RVU_BLOCK_ADDRX_DISC(a) RVU_PF_BLOCK_ADDRX_DISC(a)
+
 /* CN20k RVU mbox registers */
 #define RVU_MBOX_AF_AFPFX_TRIGX(a)    (0x9000 | (a) << 3)
 #define RVU_MBOX_PF_PFAF_TRIGX(a)     RVU_PF_PFAF_MBOXX(a)
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 63419884ac..13eb9d3767 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -677,10 +677,9 @@ cpt_get_blkaddr(struct dev *dev)
 	 * attached to. Assume CPT LF's of only one block are attached
 	 * to a pffunc.
 	 */
-	if (dev_is_vf(dev))
-		off = RVU_VF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
-	else
-		off = RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
+
+	/* PF and VF block address offset is same, hence using common offset */
+	off = RVU_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);

 	reg = plt_read64(dev->bar2 + off);

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index aad2631673..a21c40acf1 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -19,6 +19,10 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ ==
 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024);
 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==
 		  1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);
+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == ROC_NIX_INL_OW_IPSEC_INB_SA_SZ);
+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == ROC_NIX_INL_ON_IPSEC_INB_SA_SZ);
+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ);
+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ == ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ);

 static int
 nix_inl_meta_aura_destroy(struct roc_nix *roc_nix)
@@ -427,12 +431,8 @@ nix_inl_inb_ipsec_sa_tbl_setup(struct roc_nix *roc_nix)
 	/* CN9K SA size is different */
 	if (roc_nix->custom_inb_sa)
 		inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ;
-	else if (roc_model_is_cn9k())
-		inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
-	else if (roc_model_is_cn10k())
-		inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
 	else
-		inb_sa_sz = ROC_NIX_INL_OW_IPSEC_INB_SA_SZ;
+		inb_sa_sz = ROC_NIX_INL_IPSEC_INB_SA_SZ;

 	/* Alloc contiguous memory for Inbound SA's */
 	nix->inb_sa_sz[profile_id] = inb_sa_sz;
@@ -1198,10 +1198,9 @@ nix_inl_eng_caps_get(struct nix *nix)
 	inst.rptr = (uint64_t)rptr;
 	inst.w4.s.opcode_major = ROC_LOADFVC_MAJOR_OP;
 	inst.w4.s.opcode_minor = ROC_LOADFVC_MINOR_OP;
-	if (roc_model_is_cn9k() || roc_model_is_cn10k())
-		inst.w7.s.egrp = ROC_LEGACY_CPT_DFLT_ENG_GRP_SE;
-	else
-		inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;
+
+	/* SE engine group ID is same for all platform */
+	inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE;

 	/* Use 1 min timeout for the poll */
 	const uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz();
@@ -1614,13 +1613,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	if (!roc_nix->ipsec_out_max_sa)
 		goto skip_sa_alloc;

-	/* CN9K SA size is different */
-	if (roc_model_is_cn9k())
-		sa_sz = ROC_NIX_INL_ON_IPSEC_OUTB_SA_SZ;
-	else if (roc_model_is_cn10k())
-		sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;
-	else
-		sa_sz = ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ;
+	sa_sz = ROC_NIX_INL_IPSEC_OUTB_SA_SZ;

 	/* Alloc contiguous memory of outbound SA */
 	sa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 727a2e2a81..35528efa46 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -837,12 +837,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 	/* CN9K SA is different */
 	if (inl_dev->custom_inb_sa)
 		inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ;
-	else if (roc_model_is_cn9k())
-		inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ;
-	else if (roc_model_is_cn10k())
-		inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
 	else
-		inb_sa_sz = ROC_NIX_INL_OW_IPSEC_INB_SA_SZ;
+		inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;

 	/* Alloc contiguous memory for Inbound SA's */
 	inl_dev->inb_sa_sz[profile_id] = inb_sa_sz;
diff --git a/drivers/common/cnxk/roc_nix_inl_dp.h b/drivers/common/cnxk/roc_nix_inl_dp.h
index eb101db179..6443770871 100644
--- a/drivers/common/cnxk/roc_nix_inl_dp.h
+++ b/drivers/common/cnxk/roc_nix_inl_dp.h
@@ -41,6 +41,9 @@
 	(ROC_NIX_INL_OW_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OW_IPSEC_OUTB_SW_RSVD)
 #define ROC_NIX_INL_OW_IPSEC_OUTB_SA_SZ_LOG2 9

+#define ROC_NIX_INL_IPSEC_INB_SA_SZ  ROC_NIX_INL_OT_IPSEC_INB_SA_SZ
+#define ROC_NIX_INL_IPSEC_OUTB_SA_SZ ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ
+
 /* Alignment of SA Base */
 #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)

diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index 308a62a70e..d4b3c7c1af 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -23,10 +23,10 @@
 #define NIX_CQ_SEC_THRESH_LEVEL_REF1	(20 * 256 / 100)
 #define NIX_CQ_BP_THRESH_LEVEL_REF1	(60 * 256 / 100)
 #define NIX_CQ_SEC_BP_THRESH_LEVEL_REF1 (50 * 256 / 100)
-#define NIX_CQ_LBP_THRESH_FRAC_REF1	(80 * 16 / 100)
+#define NIX_CQ_LBP_THRESH_FRAC_REF1	(80 * 16 / 100.0)

 /* Apply LBP at 75% of actual BP */
-#define NIX_CQ_LBP_THRESH_FRAC	(75 * 16 / 100)
+#define NIX_CQ_LBP_THRESH_FRAC	(75 * 16 / 100.0)
 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
 #define NIX_RQ_AURA_BP_THRESH(percent, limit, shift) ((((limit) * (percent)) / 100) >> (shift))

--
2.34.1

Re: [PATCH v2 18/18] common/cnxk: fix duplicate branch compiler warning

[Jerin Jacob]

On Tue, Feb 17, 2026 at 11:16 AM Rahul Bhansali <rbhansali@marvell.com> wrote:
>
> With compiler option '-Wduplicated-branches', getting few
> warnings such as "this condition has identical branches".
>
> Macros are updated to address these warnings.
>
> Bugzilla ID: 1811
> Fixes: 0d9e323bacf0 ("common/cnxk: support for CN20K inline IPsec")
> Fixes: c045d2e5cbbc ("common/cnxk: add CPT configuration")
> Cc: stable@dpdk.org
>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>

Series applied to dpdk-next-net-mrvl/for-main. Thanks