From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ferruh Yigit <ferruh.yigit@intel.com>
Subject: Re: [PATCH 0/3 v2] disable vector PMD for i686
Date: Fri, 28 Apr 2017 10:34:24 +0100
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Cc: Qi Zhang <qi.z.zhang@intel.com>, dev@dpdk.org, jingjing.wu@intel.com,
 helin.zhang@intel.com, wenzhuo.lu@intel.com, jing.d.chen@intel.com
To: Bruce Richardson <bruce.richardson@intel.com>,
 Thomas Monjalon <thomas@monjalon.net>
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On 4/28/2017 10:26 AM, Bruce Richardson wrote:
> On Fri, Apr 28, 2017 at 11:14:24AM +0200, Thomas Monjalon wrote:
>> 27/04/2017 11:25, Bruce Richardson:
>>> On Thu, Apr 27, 2017 at 03:01:04AM -0400, Qi Zhang wrote:
>>>> Vector PMD is not designed for i686 orginally, but it still can be active
>>>> with i686 compile option.
>>>> Below are observed failure when vPMD is invovled on i686
>>>> (but may not limited to)
>>>>
>>>> 1) memory overwrite when assign 2 mbuf points to rx return points.
>>>> _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2)
>>>
>>> Is this a serious issue that prevents us using the driver? I think it's been
>>> in the code for quite some time. Can it not be relatively easily fixed for
>>> 32-bit builds?
>>>
>>>>
>>>> 2) rearm_data is not 16 bytes aligned that cause general-protection exception
>>>> _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
>>>>
>>>
>>> Good catch. I think this is also an easy fix. My preferred fix is to
>>> explicitly align the rearm data on a 16-byte boundary. It would add some
>>> padding to the middle of cacheline0 of the mbuf, but given that we
>>> explicitly move other data to cacheline1, we will have padding on 32-bit
>>> anyway, be it in the middle or the end of the mbuf cachelines.
>>>
>>>> So the patch set will exclude Vector PMD from compile with i686 configure.
>>
>> Please try to fix the drivers instead of turning them off.
> 
> The patch for alignment of physical addresses should fix these issues,
> removing the need for these patches.

Patches marked as rejected, Thanks for the fix Bruce!

> 
> /Bruce
>