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Subject: SORING cache guards
Date: Tue, 21 Apr 2026 12:46:20 +0200
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Thread-Topic: SORING cache guards
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From: =?iso-8859-1?Q?Morten_Br=F8rup?= <mb@smartsharesystems.com>
To: "Konstantin Ananyev" <konstantin.ananyev@huawei.com>,
	<dev@dpdk.org>
Cc: "Konstantin Ananyev" <konstantin.v.ananyev@yandex.ru>,
 "Wathsala Vithanage" <wathsala.vithanage@arm.com>
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Konstantin,

Suggestion:

I'm not sure about this, but shouldn't the arrays in the SORING be =
padded by cache guards?

/*
 * Calculate size offsets for SORING internal data layout.
 */
static size_t
soring_get_szofs(uint32_t esize, uint32_t msize, uint32_t count,
	uint32_t stages, size_t *elst_ofs, size_t *state_ofs,
	size_t *stage_ofs)
{
	size_t sz;
	const struct rte_soring * const r =3D NULL;

	sz =3D sizeof(r[0]) + (size_t)count * esize;
	sz =3D RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE);
+	sz +=3D RTE_CACHE_GUARD_LINES * RTE_CACHE_LINE_SIZE;

	if (elst_ofs !=3D NULL)
		*elst_ofs =3D sz;

-	sz =3D sz + (size_t)count * msize;
+	sz +=3D (size_t)count * msize;
	sz =3D RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE);
+	sz +=3D RTE_CACHE_GUARD_LINES * RTE_CACHE_LINE_SIZE;

	if (state_ofs !=3D NULL)
		*state_ofs =3D sz;

	sz +=3D sizeof(r->state[0]) * count;
	sz =3D RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE);
+	sz +=3D RTE_CACHE_GUARD_LINES * RTE_CACHE_LINE_SIZE;

	if (stage_ofs !=3D NULL)
		*stage_ofs =3D sz;

	sz +=3D sizeof(r->stage[0]) * stages;
	sz =3D RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE);
+	sz +=3D RTE_CACHE_GUARD_LINES * RTE_CACHE_LINE_SIZE;

	return sz;
}

Such a change would break the ABI, so it should be announced in advance.

I'll leave it up to you to provide patches, if you agree. ;-)

-Morten