From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jianbo Liu <jianbo.liu@linaro.org>
Subject: Re: [PATCH 2/2] net/ixgbe: calculate correct number of
 received packets for ARM NEON-version vPMD
Date: Thu, 22 Dec 2016 09:18:12 +0800
Message-ID: <CAP4Qi38KtF7gKdoBvo9Np=WxoGarfTb-TxSgexLQcAUeHAEbcA@mail.gmail.com>
References: <1482127758-4904-1-git-send-email-jianbo.liu@linaro.org>
 <1482127758-4904-2-git-send-email-jianbo.liu@linaro.org>
 <20161221100848.GA4506@localhost.localdomain>
 <20161221110331.GA9108@bricha3-MOBL3.ger.corp.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Cc: Jerin Jacob <jerin.jacob@caviumnetworks.com>, dev@dpdk.org,
 "Zhang, Helin" <helin.zhang@intel.com>,
 "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: Bruce Richardson <bruce.richardson@intel.com>
Return-path: <dev-bounces@dpdk.org>
Received: from mail-yb0-f180.google.com (mail-yb0-f180.google.com
 [209.85.213.180]) by dpdk.org (Postfix) with ESMTP id 47D4C10CD5
 for <dev@dpdk.org>; Thu, 22 Dec 2016 02:18:12 +0100 (CET)
Received: by mail-yb0-f180.google.com with SMTP id 84so10426126ybe.3
 for <dev@dpdk.org>; Wed, 21 Dec 2016 17:18:12 -0800 (PST)
In-Reply-To: <20161221110331.GA9108@bricha3-MOBL3.ger.corp.intel.com>
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

On 21 December 2016 at 19:03, Bruce Richardson
<bruce.richardson@intel.com> wrote:
> On Wed, Dec 21, 2016 at 03:38:51PM +0530, Jerin Jacob wrote:
>> On Mon, Dec 19, 2016 at 11:39:18AM +0530, Jianbo Liu wrote:
>>
>> Hi Jianbo,
>>
>> > vPMD will check 4 descriptors in one time, but the statuses are not consistent
>> > because the memory allocated for RX descriptors is cacheable huagepage.
>> Is it different in X86 case ?i.e Is x86 creating non cacheable hugepages?
>
> This is not a problem on IA, because the instruction ordering rules on
> IA guarantee that the reads will be done in the correct program order,
> and we never get stale cache data.
>

Yes, I think it's an issue for ARM arch.
It's because more than one cacheline-sized data (4/8 descriptors can
be in two cachelines) will be read at one time in bulk alloc RX or
vPMD.
There is the same issue for i40e, I'll send the same patch later.