From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jianbo Liu <jianbo.liu@linaro.org>
Subject: Re: [PATCH 08/28] eal/arm64: define smp barrier
 definition for arm64
Date: Thu, 15 Dec 2016 16:13:33 +0800
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References: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com>
 <1481680558-4003-9-git-send-email-jerin.jacob@caviumnetworks.com>
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Cc: dev@dpdk.org, "Ananyev, Konstantin" <konstantin.ananyev@intel.com>,
 Thomas Monjalon <thomas.monjalon@6wind.com>,
 Bruce Richardson <bruce.richardson@intel.com>,
 Jan Viktorin <viktorin@rehivetech.com>
To: Jerin Jacob <jerin.jacob@caviumnetworks.com>
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On 14 December 2016 at 09:55, Jerin Jacob
<jerin.jacob@caviumnetworks.com> wrote:
> dmb instruction based barrier is used for smp version of memory barrier.
>
> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> ---
>  lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index bc7de64..78ebea2 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -82,11 +82,11 @@ static inline void rte_rmb(void)
>         dsb(ld);
>  }
>
> -#define rte_smp_mb() rte_mb()
> +#define rte_smp_mb() dmb(ish)
>
> -#define rte_smp_wmb() rte_wmb()
> +#define rte_smp_wmb() dmb(ishst)
>
> -#define rte_smp_rmb() rte_rmb()
> +#define rte_smp_rmb() dmb(ishld)
>

rte_*mb are inline functions, while rte_smp_*mb are macro. As they are
all derived from dsb/dmb, can you keep them consistent?

>  #ifdef __cplusplus
>  }
> --
> 2.5.5
>