[PATCH v1 0/6] Update ICE Base Driver

[PATCH v1 0/6] Update ICE Base Driver

[Soumyadeep Hore]

This series updates shared code of ICE PMD.

Aleksandr Loktionov (1):
  net/ice/base: enable LLDP filter control for E830

Grzegorz Nitka (1):
  net/ice/base: fix 'adjust' timer programming for E830

Maciej Paczkowski (1):
  net/ice/base: resolve comparison-with-wider-type violations

Paul Greenwalt (2):
  net/ice/base: update crash on invalid topology
  net/ice/base: support RDMA on 4+ ports of E830

Pawel Sobczyk (1):
  net/ice/base: add pending admin queue events API

 drivers/net/intel/ice/base/ice_acl_ctrl.c |  6 +++---
 drivers/net/intel/ice/base/ice_bitops.h   | 14 +++++++-------
 drivers/net/intel/ice/base/ice_common.c   | 22 ++++++++++++++++------
 drivers/net/intel/ice/base/ice_common.h   |  1 +
 drivers/net/intel/ice/base/ice_controlq.c | 16 ++++++++++++++++
 drivers/net/intel/ice/base/ice_dcb.c      |  8 ++++----
 drivers/net/intel/ice/base/ice_ptp_hw.c   |  6 +++---
 drivers/net/intel/ice/base/ice_sched.c    | 13 ++++++++++++-
 drivers/net/intel/ice/base/ice_switch.c   |  2 +-
 drivers/net/intel/ice/base/ice_type.h     |  7 ++++++-
 10 files changed, 69 insertions(+), 26 deletions(-)

-- 
2.47.1

[PATCH v1 1/6] net/ice/base: update crash on invalid topology

[Soumyadeep Hore]

From: Paul Greenwalt <paul.greenwalt@intel.com>

In some cases, after NVM update finish and triggers EMPR, FW will return
invalid information about Tx Scheduler topology
(in reply to ice_sched_query_res_alloc(), we end up with 0 as a number
children to allocate in 4th layer, then adding 5th layer nodes would
crash).

As in this scenario we need to reboot the platform anyway, it is safe to
just fail building the scheduler tree.

Add a warning, so we will be sure that this was the case.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/net/intel/ice/base/ice_sched.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/net/intel/ice/base/ice_sched.c b/drivers/net/intel/ice/base/ice_sched.c
index be9393a7d6..3a0907eda7 100644
--- a/drivers/net/intel/ice/base/ice_sched.c
+++ b/drivers/net/intel/ice/base/ice_sched.c
@@ -174,6 +174,16 @@ ice_sched_add_node(struct ice_port_info *pi, u8 layer,
 		return ICE_ERR_PARAM;
 	}
 
+	/* After NVM update FW will(in some cases) not return proper
+	 * topology, bail out early in such cases
+	 * (as there is a need of platform reboot anyway).
+	 */
+	if (!parent->children) {
+		ice_debug(hw, ICE_DBG_SCHED, "Parent (teid = 0x%x) hasn't prepared to have children, aborting\n",
+			LE32_TO_CPU(info->parent_teid));
+		return ICE_ERR_PARAM;
+	}
+
 	/* query the current node information from FW before adding it
 	 * to the SW DB
 	 */
-- 
2.47.1

[PATCH v1 2/6] net/ice/base: resolve comparison-with-wider-type violations

[Soumyadeep Hore]

From: Maciej Paczkowski <maciej.paczkowski@intel.com>

- This patch resolves violations raised by Windows CodeQL
  tool related to comparison-with-wider-type error.

- Added data type casting to resolve these errors.

Signed-off-by: Maciej Paczkowski <maciej.paczkowski@intel.com>
Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/net/intel/ice/base/ice_acl_ctrl.c |  6 +++---
 drivers/net/intel/ice/base/ice_bitops.h   | 14 +++++++-------
 drivers/net/intel/ice/base/ice_dcb.c      |  8 ++++----
 drivers/net/intel/ice/base/ice_sched.c    |  3 ++-
 drivers/net/intel/ice/base/ice_switch.c   |  2 +-
 5 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/drivers/net/intel/ice/base/ice_acl_ctrl.c b/drivers/net/intel/ice/base/ice_acl_ctrl.c
index 6cee2c98ea..6ec9f7f754 100644
--- a/drivers/net/intel/ice/base/ice_acl_ctrl.c
+++ b/drivers/net/intel/ice/base/ice_acl_ctrl.c
@@ -494,7 +494,7 @@ ice_acl_alloc_partition(struct ice_hw *hw, struct ice_acl_scen *req)
 			 * is available.
 			 */
 			p = dir > 0 ? i : ICE_AQC_MAX_TCAM_ALLOC_UNITS - i - 1;
-			for (w = row; w < row + width && avail; w++) {
+			for (w = row; w < (u16)(row + width) && avail; w++) {
 				u16 b;
 
 				b = (w * ICE_AQC_MAX_TCAM_ALLOC_UNITS) + p;
@@ -644,7 +644,7 @@ ice_acl_set_scen_chnk_msk(struct ice_aqc_acl_scen *scen_buf,
 		 * For each TCAM, there will be (ICE_AQC_ACL_TCAM_DEPTH
 		 * / ICE_ACL_ENTRY_ALLOC_UNIT) or 8 chunks.
 		 */
-		for (i = tcam_idx; i < tcam_idx + num_cscd; i++)
+		for (i = tcam_idx; i < (u16)(tcam_idx + num_cscd); i++)
 			scen_buf->tcam_cfg[i].chnk_msk |= BIT(chnk_offst);
 
 		chnk_offst = (chnk_offst + 1) % ICE_AQC_MAX_TCAM_ALLOC_UNITS;
@@ -799,7 +799,7 @@ ice_acl_create_scen(struct ice_hw *hw, u16 match_width, u16 num_entries,
 			ICE_AQC_ACL_ALLOC_SCE_START_CMP;
 
 		/* cascade TCAMs up to the width of the scenario */
-		for (i = k; i < cascade_cnt + k; i++) {
+		for (i = k; i < (u8)(cascade_cnt + k); i++) {
 			ice_acl_fill_tcam_select(&scen_buf, scen, i, i - k);
 			ice_acl_assign_act_mem_for_scen(hw->acl_tbl, scen,
 							&scen_buf,
diff --git a/drivers/net/intel/ice/base/ice_bitops.h b/drivers/net/intel/ice/base/ice_bitops.h
index 85e14a2358..829b2062c8 100644
--- a/drivers/net/intel/ice/base/ice_bitops.h
+++ b/drivers/net/intel/ice/base/ice_bitops.h
@@ -188,7 +188,7 @@ ice_and_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
 	u16 i;
 
 	/* Handle all but the last chunk */
-	for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++) {
+	for (i = 0; i < (u16)(BITS_TO_CHUNKS(size) - 1); i++) {
 		dst[i] = bmp1[i] & bmp2[i];
 		res |= dst[i];
 	}
@@ -225,7 +225,7 @@ ice_or_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
 	u16 i;
 
 	/* Handle all but last chunk */
-	for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)
+	for (i = 0; i < (u16)(BITS_TO_CHUNKS(size) - 1); i++)
 		dst[i] = bmp1[i] | bmp2[i];
 
 	/* We want to only OR bits within the size. Furthermore, we also do
@@ -256,7 +256,7 @@ ice_xor_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
 	u16 i;
 
 	/* Handle all but last chunk */
-	for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)
+	for (i = 0; i < (u16)(BITS_TO_CHUNKS(size) - 1); i++)
 		dst[i] = bmp1[i] ^ bmp2[i];
 
 	/* We want to only XOR bits within the size. Furthermore, we also do
@@ -287,7 +287,7 @@ ice_andnot_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,
 	u16 i;
 
 	/* Handle all but last chunk */
-	for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)
+	for (i = 0; i < (u16)(BITS_TO_CHUNKS(size) - 1); i++)
 		dst[i] = bmp1[i] & ~bmp2[i];
 
 	/* We want to only clear bits within the size. Furthermore, we also do
@@ -330,7 +330,7 @@ ice_find_next_bit(const ice_bitmap_t *bitmap, u16 size, u16 offset)
 	}
 
 	/* Now we handle the remaining chunks, if any */
-	for (i++; i < BITS_TO_CHUNKS(size); i++) {
+	for (i++; i < (u16)BITS_TO_CHUNKS(size); i++) {
 		if (bitmap[i] != 0) {
 			u16 off = i * BITS_PER_CHUNK;
 
@@ -405,7 +405,7 @@ ice_bitmap_set(ice_bitmap_t *dst, u16 pos, u16 num_bits)
 {
 	u16 i;
 
-	for (i = pos; i < pos + num_bits; i++)
+	for (i = pos; i < (u16)(pos + num_bits); i++)
 		ice_set_bit(i, dst);
 }
 
@@ -447,7 +447,7 @@ ice_cmp_bitmap(ice_bitmap_t *bmp1, ice_bitmap_t *bmp2, u16 size)
 	u16 i;
 
 	/* Handle all but last chunk */
-	for (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)
+	for (i = 0; i < (u16)(BITS_TO_CHUNKS(size) - 1); i++)
 		if (bmp1[i] != bmp2[i])
 			return false;
 
diff --git a/drivers/net/intel/ice/base/ice_dcb.c b/drivers/net/intel/ice/base/ice_dcb.c
index 607af03525..f5fbf535d5 100644
--- a/drivers/net/intel/ice/base/ice_dcb.c
+++ b/drivers/net/intel/ice/base/ice_dcb.c
@@ -465,7 +465,7 @@ ice_parse_cee_app_tlv(struct ice_cee_feat_tlv *tlv, struct ice_dcbx_cfg *dcbcfg)
 {
 	u16 len, typelen, offset = 0;
 	struct ice_cee_app_prio *app;
-	u8 i;
+	u32 i;
 
 	typelen = NTOHS(tlv->hdr.typelen);
 	len = ((typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S);
@@ -790,8 +790,8 @@ ice_cee_to_dcb_cfg(struct ice_aqc_get_cee_dcb_cfg_resp *cee_cfg,
 		   struct ice_port_info *pi)
 {
 	u32 status, tlv_status = LE32_TO_CPU(cee_cfg->tlv_status);
-	u32 ice_aqc_cee_status_mask, ice_aqc_cee_status_shift;
-	u8 i, j, err, sync, oper, app_index, ice_app_sel_type;
+	u32 j, ice_aqc_cee_status_mask, ice_aqc_cee_status_shift;
+	u8 i, err, sync, oper, app_index, ice_app_sel_type;
 	u16 app_prio = LE16_TO_CPU(cee_cfg->oper_app_prio);
 	u16 ice_aqc_cee_app_mask, ice_aqc_cee_app_shift;
 	struct ice_dcbx_cfg *cmp_dcbcfg, *dcbcfg;
@@ -1324,7 +1324,7 @@ ice_add_ieee_app_pri_tlv(struct ice_lldp_org_tlv *tlv,
 	 *   Bits:|23    21|20 19|18 16|15                0|
 	 *        -----------------------------------------
 	 */
-	while (i < dcbcfg->numapps) {
+	while (i < (u8)dcbcfg->numapps) {
 		priority = dcbcfg->app[i].priority & 0x7;
 		selector = dcbcfg->app[i].selector & 0x7;
 		buf[offset] = (priority << ICE_IEEE_APP_PRIO_S) | selector;
diff --git a/drivers/net/intel/ice/base/ice_sched.c b/drivers/net/intel/ice/base/ice_sched.c
index 3a0907eda7..2b867b74de 100644
--- a/drivers/net/intel/ice/base/ice_sched.c
+++ b/drivers/net/intel/ice/base/ice_sched.c
@@ -1257,7 +1257,8 @@ int ice_sched_init_port(struct ice_port_info *pi)
 	u8 num_branches;
 	u16 num_elems;
 	int status;
-	u8 i, j;
+	u8 i;
+	u16 j;
 
 	if (!pi)
 		return ICE_ERR_PARAM;
diff --git a/drivers/net/intel/ice/base/ice_switch.c b/drivers/net/intel/ice/base/ice_switch.c
index fff61b89d7..94099c5215 100644
--- a/drivers/net/intel/ice/base/ice_switch.c
+++ b/drivers/net/intel/ice/base/ice_switch.c
@@ -7437,7 +7437,7 @@ ice_fill_fv_word_index(struct ice_hw *hw, struct LIST_HEAD_TYPE *fv_list,
 			struct ice_fv_word *pr;
 			bool found = false;
 			u16 mask;
-			u8 j;
+			u16 j;
 
 			pr = &rg->r_group.pairs[i];
 			mask = rg->r_group.mask[i];
-- 
2.47.1

[PATCH v1 3/6] net/ice/base: enable LLDP filter control for E830

[Soumyadeep Hore]

From: Aleksandr Loktionov <aleksandr.loktionov@intel.com>

The ice_fw_supports_lldp_fltr_ctrl() function previously restricted the
LLDP filter control API (admin queue command 0x0A0A) to E810 devices
only. This limitation prevented newer hardware like E830 from using the
more efficient LLDP packet filtering method, even when firmware support
was available.

Remove the hardware type restriction and implement hardware-specific
firmware API version checks to determine LLDP filter control support.
E810 and E82x cards require firmware API version >= 1.7.1, while E830
cards require firmware API version >= 1.7.11. This enables E830 and
future hardware to utilize the improved filtering mechanism when
supported by firmware.

Additionally, add fallback logic in ice_cfg_sw_lldp() to automatically
fall back to the legacy ethernet filter method if the new LLDP filter
control API fails. This provides resilience against buggy firmware that
may report API support but fail during actual command execution.

The try-fallback pattern ensures LLDP configuration succeeds regardless
of firmware quirks, improving driver robustness across hardware
generations and firmware versions.

Signed-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/net/intel/ice/base/ice_common.c | 20 ++++++++++++++------
 drivers/net/intel/ice/base/ice_type.h   |  7 ++++++-
 2 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/net/intel/ice/base/ice_common.c b/drivers/net/intel/ice/base/ice_common.c
index 72f84d49cd..7d8f677c99 100644
--- a/drivers/net/intel/ice/base/ice_common.c
+++ b/drivers/net/intel/ice/base/ice_common.c
@@ -6561,15 +6561,23 @@ ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
 /**
  * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
  * @hw: pointer to HW struct
+ *
+ * Check if firmware supports the LLDP filter control feature (AQ command 0x0A0A).
+ * Different hardware families require different minimum firmware versions:
+ * - E810 and E82x cards require API version 1.7.1 or later
+ * - E830 cards require API version 1.7.11 or later
  */
 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw)
 {
-	if (hw->mac_type != ICE_MAC_E810 && hw->mac_type != ICE_MAC_GENERIC)
-		return false;
-
-	return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ,
-				     ICE_FW_API_LLDP_FLTR_MIN,
-				     ICE_FW_API_LLDP_FLTR_PATCH);
+	if (hw->mac_type == ICE_MAC_E830)
+		return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ_E830,
+					     ICE_FW_API_LLDP_FLTR_MIN_E830,
+					     ICE_FW_API_LLDP_FLTR_PATCH_E830);
+	if (hw->mac_type == ICE_MAC_E810 || hw->mac_type == ICE_MAC_GENERIC)
+		return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ,
+					     ICE_FW_API_LLDP_FLTR_MIN,
+					     ICE_FW_API_LLDP_FLTR_PATCH);
+	return false;
 }
 
 /**
diff --git a/drivers/net/intel/ice/base/ice_type.h b/drivers/net/intel/ice/base/ice_type.h
index 4b05a800af..6d8c187689 100644
--- a/drivers/net/intel/ice/base/ice_type.h
+++ b/drivers/net/intel/ice/base/ice_type.h
@@ -1718,11 +1718,16 @@ struct ice_aq_get_set_rss_lut_params {
 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
 
-/* AQ API version for LLDP_FILTER_CONTROL */
+/* AQ API version for LLDP_FILTER_CONTROL - E810 and E82x */
 #define ICE_FW_API_LLDP_FLTR_MAJ	1
 #define ICE_FW_API_LLDP_FLTR_MIN	7
 #define ICE_FW_API_LLDP_FLTR_PATCH	1
 
+/* AQ API version for LLDP_FILTER_CONTROL - E830 */
+#define ICE_FW_API_LLDP_FLTR_MAJ_E830	1
+#define ICE_FW_API_LLDP_FLTR_MIN_E830	7
+#define ICE_FW_API_LLDP_FLTR_PATCH_E830	11
+
 /* AQ API version for report default configuration */
 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ		1
 #define ICE_FW_API_REPORT_DFLT_CFG_MIN		7
-- 
2.47.1

[PATCH v1 4/6] net/ice/base: support RDMA on 4+ ports of E830

[Soumyadeep Hore]

From: Paul Greenwalt <paul.greenwalt@intel.com>

E810/E82X devices do not support RDMA on 4+ ports configurations. This is
not true for E830 devices.

During device capability discovery do not apply RDMA limitation when
the device is E830.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/net/intel/ice/base/ice_common.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/intel/ice/base/ice_common.c b/drivers/net/intel/ice/base/ice_common.c
index 7d8f677c99..934e0c2d5b 100644
--- a/drivers/net/intel/ice/base/ice_common.c
+++ b/drivers/net/intel/ice/base/ice_common.c
@@ -2668,6 +2668,8 @@ ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
 		caps->maxtc = 4;
 		ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %u (based on #ports)\n",
 			  caps->maxtc);
+		if (hw->mac_type == ICE_MAC_E830)
+			return;
 	}
 }
 
-- 
2.47.1

[PATCH v1 5/6] net/ice/base: add pending admin queue events API

[Soumyadeep Hore]

From: Pawel Sobczyk <pawel.sobczyk@intel.com>

Adds a new API ice_ctrlq_pending() to check if there
are pending messages in the admin control queue. The
function is intended to be called after clearing the
ADMINQ_EVENT_PENDING flag to ensure all pending
messages are processed before re-enabling interrupts.

Signed-off-by: Pawel Sobczyk <pawel.sobczyk@intel.com>
Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
---
 drivers/net/intel/ice/base/ice_common.h   |  1 +
 drivers/net/intel/ice/base/ice_controlq.c | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/net/intel/ice/base/ice_common.h b/drivers/net/intel/ice/base/ice_common.h
index 884b8f7834..3e9d3c2f80 100644
--- a/drivers/net/intel/ice/base/ice_common.h
+++ b/drivers/net/intel/ice/base/ice_common.h
@@ -148,6 +148,7 @@ ice_aq_ena_dis_txtimeq(struct ice_hw *hw, u16 txtimeq, u16 q_count, bool q_ena,
 extern const struct ice_ctx_ele ice_txtime_ctx_info[];
 
 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
+bool ice_ctrlq_pending(struct ice_hw *hw, struct ice_ctl_q_info *cq);
 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
 extern const struct ice_ctx_ele ice_tlan_ctx_info[];
diff --git a/drivers/net/intel/ice/base/ice_controlq.c b/drivers/net/intel/ice/base/ice_controlq.c
index b210495827..d68e603a8c 100644
--- a/drivers/net/intel/ice/base/ice_controlq.c
+++ b/drivers/net/intel/ice/base/ice_controlq.c
@@ -965,6 +965,22 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 	return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
 }
 
+/**
+ * ice_ctrlq_pending - check if there are pending messages on the control queue
+ * @hw: pointer to the HW struct
+ * @cq: pointer to the specific Control queue
+ *
+ * Returns: true if there are pending messages in a queue (i.e. next_to_clean
+ *          does not match the hardware head register), false otherwise
+ */
+bool ice_ctrlq_pending(struct ice_hw *hw, struct ice_ctl_q_info *cq)
+{
+	u16 ntu;
+
+	ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
+	return cq->rq.next_to_clean != ntu;
+}
+
 /**
  * ice_sq_send_cmd_nolock - send command to a control queue
  * @hw: pointer to the HW struct
-- 
2.47.1

[PATCH v1 6/6] net/ice/base: fix 'adjust' timer programming for E830

[Soumyadeep Hore]

From: Grzegorz Nitka <grzegorz.nitka@intel.com>

Fix incorrect 'adjust the timer' programming sequence for E830 devices
series. Only shadow registers GLTSYN_SHADJ were programmed in the current
implementation. According to the specification [1], write to command
GLTSYN_CMD register is also required with CMD field set to "Adjust the
Time" value, for the timer adjustment to take the effect.

The flow was broken for the adjustment less than S32_MAX/MIN range
(around +/- 2 seconds). For bigger adjustment, non-atomic programming
flow is used, involving set timer programming. Non-atomic flow is
implemented correctly.

Fixes: 881169950d80 ("net/ice/base: implement initial PTP support for E830")
Cc: stable@dpdk.org

Signed-off-by: Soumyadeep Hore <soumyadeep.hore@intel.com>
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
---
 drivers/net/intel/ice/base/ice_ptp_hw.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/intel/ice/base/ice_ptp_hw.c b/drivers/net/intel/ice/base/ice_ptp_hw.c
index 7d16965674..5688f969ce 100644
--- a/drivers/net/intel/ice/base/ice_ptp_hw.c
+++ b/drivers/net/intel/ice/base/ice_ptp_hw.c
@@ -6083,7 +6083,7 @@ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval,
  */
 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
 {
-	int err;
+	int err = 0;
 	u8 tmr_idx;
 
 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
@@ -6101,8 +6101,8 @@ int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
 		err = ice_ptp_prep_phy_adj_eth56g(hw, adj, lock_sbq);
 		break;
 	case ICE_PHY_E830:
-		/* E830 sync PHYs automatically after setting GLTSYN_SHADJ */
-		return 0;
+		/* E830 sync PHYs automatically after setting cmd register */
+		break;
 	case ICE_PHY_E810:
 		err = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
 		break;
-- 
2.47.1

Re: [PATCH v1 0/6] Update ICE Base Driver

[Bruce Richardson]

On Tue, Mar 10, 2026 at 05:52:03AM -0400, Soumyadeep Hore wrote:
> This series updates shared code of ICE PMD.
> 
> Aleksandr Loktionov (1):
>   net/ice/base: enable LLDP filter control for E830
> 
> Grzegorz Nitka (1):
>   net/ice/base: fix 'adjust' timer programming for E830
> 
> Maciej Paczkowski (1):
>   net/ice/base: resolve comparison-with-wider-type violations
> 
> Paul Greenwalt (2):
>   net/ice/base: update crash on invalid topology
>   net/ice/base: support RDMA on 4+ ports of E830
> 
> Pawel Sobczyk (1):
>   net/ice/base: add pending admin queue events API
> 
Series-acked-by: Bruce Richardson <bruce.richardson@intel.com>

Series applied to dpdk-next-net-intel, except patch 4 which is a no-op
change for DPDK itself.

Thanks,
/Bruce