From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2751C433DB for ; Mon, 22 Mar 2021 09:22:48 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id DC32461972 for ; Mon, 22 Mar 2021 09:22:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DC32461972 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 033F740040; Mon, 22 Mar 2021 10:22:47 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 906AF4003D for ; Mon, 22 Mar 2021 10:22:44 +0100 (CET) IronPort-SDR: v6XQ22YNVxWc8sQ450XOy6YsAa7Lp5Y98JTjt95INuiXTwi3XIElngRhDhghP8niUJaJaSTJ1n eaTAQdI86vAA== X-IronPort-AV: E=McAfee;i="6000,8403,9930"; a="210300764" X-IronPort-AV: E=Sophos;i="5.81,268,1610438400"; d="scan'208";a="210300764" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 02:22:43 -0700 IronPort-SDR: pHrakj6JyfASeNVcPnjwGrQyb+au7PDz6nX76L++FXygI/sCz1k4X0zKtr2q7vgmocxx/ckfzm PNJZ6xzDWS8Q== X-IronPort-AV: E=Sophos;i="5.81,268,1610438400"; d="scan'208";a="451672343" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.252.14.44]) ([10.252.14.44]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 02:22:41 -0700 To: Lijun Ou , thomas@monjalon.net Cc: dev@dpdk.org, linuxarm@openeuler.org, Andrew Rybchenko , David Marchand , Ray Kinsella , Luca Boccassi References: <1616070332-63414-1-git-send-email-oulijun@huawei.com> From: Ferruh Yigit X-User: ferruhy Message-ID: Date: Mon, 22 Mar 2021 09:22:37 +0000 MIME-Version: 1.0 In-Reply-To: <1616070332-63414-1-git-send-email-oulijun@huawei.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-dev] [PATCH] ethdev: add queue state when retrieve queue information X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 3/18/2021 12:25 PM, Lijun Ou wrote: > Currently, upper-layer application could get queue state only > through pointers such as dev->data->tx_queue_state[queue_id], > this is not the recommended way to access it. So this patch > add get queue state when call rte_eth_rx_queue_info_get and > rte_eth_tx_queue_info_get API. > > Note: The hairpin queue is not supported with above > rte_eth_*x_queue_info_get, so the queue state could be > RTE_ETH_QUEUE_STATE_STARTED or RTE_ETH_QUEUE_STATE_STOPPED. > Note: After add queue_state field, the 'struct rte_eth_rxq_info' size > remains 128B, and the 'struct rte_eth_txq_info' size remains 64B, so > it could be ABI compatible. > > Signed-off-by: Chengwen Feng > Signed-off-by: Lijun Ou <...> > diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h > index efda313..3b83c5a 100644 > --- a/lib/librte_ethdev/rte_ethdev.h > +++ b/lib/librte_ethdev/rte_ethdev.h > @@ -1591,6 +1591,8 @@ struct rte_eth_rxq_info { > uint8_t scattered_rx; /**< scattered packets RX supported. */ > uint16_t nb_desc; /**< configured number of RXDs. */ > uint16_t rx_buf_size; /**< hardware receive buffer size. */ > + /**< Queues state: STARTED(1) / STOPPED(0). */ > + uint8_t queue_state; > } __rte_cache_min_aligned; > > /** > @@ -1600,6 +1602,8 @@ struct rte_eth_rxq_info { > struct rte_eth_txq_info { > struct rte_eth_txconf conf; /**< queue config parameters. */ > uint16_t nb_desc; /**< configured number of TXDs. */ > + /**< Queues state: STARTED(1) / STOPPED(0). */ > + uint8_t queue_state; > } __rte_cache_min_aligned; > > /* Generic Burst mode flag definition, values can be ORed. */ > This is causing an ABI warning [1], but I guess it is safe since the size of the struct is not changing (cache align). Adding a few more people to comment. [1] https://travis-ci.com/github/ovsrobot/dpdk/builds/220497651