From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jia He Subject: Re: [PATCH] ring: guarantee ordering of cons/prod loading when doing enqueue/dequeue Date: Wed, 1 Nov 2017 12:48:31 +0800 Message-ID: References: <8806e2bd-c57b-03ff-a315-0a311690f1d9@163.com> <2601191342CEEE43887BDE71AB9772585FAAB404@IRSMSX103.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772585FAAB570@IRSMSX103.ger.corp.intel.com> <3e580cd7-2854-d855-be9c-7c4ce06e3ed5@gmail.com> <20171020054319.GA4249@jerin> <20171023100617.GA17957@jerin> <20171025132642.GA13977@jerin> <20171031111433.GA21742@jerin> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Cc: "Ananyev, Konstantin" , "Zhao, Bing" , Olivier MATZ , "dev@dpdk.org" , "jia.he@hxt-semitech.com" , "jie2.liu@hxt-semitech.com" , "bing.zhao@hxt-semitech.com" , "Richardson, Bruce" , jianbo.liu@arm.com, hemant.agrawal@nxp.com To: Jerin Jacob Return-path: Received: from mail-pg0-f50.google.com (mail-pg0-f50.google.com [74.125.83.50]) by dpdk.org (Postfix) with ESMTP id AF8101B20C for ; Wed, 1 Nov 2017 05:48:45 +0100 (CET) Received: by mail-pg0-f50.google.com with SMTP id s75so1137483pgs.0 for ; Tue, 31 Oct 2017 21:48:45 -0700 (PDT) In-Reply-To: <20171031111433.GA21742@jerin> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Jerin On 10/31/2017 7:14 PM, Jerin Jacob Wrote: > -----Original Message----- >> Date: Tue, 31 Oct 2017 10:55:15 +0800 >> From: Jia He >> To: Jerin Jacob >> Cc: "Ananyev, Konstantin" , "Zhao, Bing" >> , Olivier MATZ , >> "dev@dpdk.org" , "jia.he@hxt-semitech.com" >> , "jie2.liu@hxt-semitech.com" >> , "bing.zhao@hxt-semitech.com" >> , "Richardson, Bruce" >> >> Subject: Re: [dpdk-dev] [PATCH] ring: guarantee ordering of cons/prod >> loading when doing enqueue/dequeue >> User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 >> Thunderbird/52.4.0 >> >> Hi Jerin > Hi Jia, > >> Do you thinkĀ  next step whether I need to implement the load_acquire half >> barrier as per freebsd > I did a quick prototype using C11 memory model(ACQUIRE/RELEASE) schematics > and tested on two arm64 platform in Cavium(Platform A: Non arm64 OOO machine) > and Platform B: arm64 OOO machine) Can you elaborate anything about your Non arm64 OOO machine? As I know, all arm64 server is strong memory order. Am I missed anything? -- Cheers, Jia