* Re: [PATCH 0/4] bnxt patch series
From: Ferruh Yigit @ 2016-09-29 17:32 UTC (permalink / raw)
To: Ajit Khaparde, DPDK
In-Reply-To: <20160929170328.GA52117@C02PT1RBG8WP.aus.broadcom.com>
On 9/29/2016 6:03 PM, Ajit Khaparde wrote:
> Please consider applying this patch series.
> This series is expected to be applied over the previous patchset
> once it is accepted.
> Depends on: [v2,15/15] bnxt: Update struct definitions to use the 1.5.1
> HWRM API
> http://dpdk.org/dev/patchwork/patch/16154/
>
> Ajit Khaparde (4):
> testpmd: Add support to configure 25G and 50G speeds
> bnxt: Fix a segfault encountered during KNI exit
> bnxt: Add support for Async Link Notification
> bnxt: Update the Broadcom PMD driver documentation
>
> app/test-pmd/cmdline.c | 14 ++-
> doc/guides/nics/bnxt.rst | 18 ++--
> doc/guides/testpmd_app_ug/testpmd_funcs.rst | 2 +-
> drivers/net/bnxt/Makefile | 1 +
> drivers/net/bnxt/bnxt.h | 7 +-
> drivers/net/bnxt/bnxt_cpr.c | 21 ++--
> drivers/net/bnxt/bnxt_ethdev.c | 148 +++++++++++++++++++++-----
> drivers/net/bnxt/bnxt_hwrm.c | 93 +++++++++--------
> drivers/net/bnxt/bnxt_irq.c | 156 ++++++++++++++++++++++++++++
> drivers/net/bnxt/bnxt_irq.h | 51 +++++++++
> 10 files changed, 409 insertions(+), 102 deletions(-)
> create mode 100644 drivers/net/bnxt/bnxt_irq.c
> create mode 100644 drivers/net/bnxt/bnxt_irq.h
>
Hi Ajit,
Can you please prefer sending patches in a threaded manner, that helps
keeping them organized.
All other patches in patchset should be as reply to first patch of
patchset (and if it is a patchset, first patch is most probably a
cover-letter):
[0/x] ...
[1/x] ...
....
[x/x] ...
if you use git send-email, it does this automatically for you (with
proper configuration), more details on:
http://dpdk.org/doc/guides/contributing/patches.html#sending-patches
Thanks,
ferruh
^ permalink raw reply
* [PATCH v2] app/test: remove hard-coding of crypto num qps
From: Fiona Trahe @ 2016-09-29 17:18 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, fiona.trahe, Akhil Goyal
In-Reply-To: <20160926163300.22990-1-akhil.goyal@nxp.com>
ts_params->conf.nb_queue_pairs should not be hard coded with device
specific number. It should be retrieved from the device info.
Any test which changes it should restore it to orig value.
Also related cleanup of test code setting number and size of
queue-pairs on a device, e.g.
* Removed irrelevant “for” loop – was hardcoded to only loop once.
* Removed obsolete comment re inability to free and re-allocate queu memory
and obsolete workaround for it which used to create maximum size queues.
And added freeing of ring memory on queue-pair release in aesni_mb PMD,
else releasing and setting up queue-pair of a different size fails.
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
v2:
Fix for broken QAT PMD unit tests exposed by v1
i.e. In test_device_configure_invalid_queue_pair_ids() after running tests
for invalid values restore original nb_queue_pairs.
Also cleanup of test code setting number and size of queue-pairs on a device
Also fix for aesni_mb PMD not freeing ring memory on qp release
app/test/test_cryptodev.c | 54 ++++++++++----------------
app/test/test_cryptodev_perf.c | 19 +--------
drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c | 10 ++++-
3 files changed, 30 insertions(+), 53 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index d960d72..cbcfb3f 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -307,37 +307,27 @@ testsuite_setup(void)
return TEST_FAILED;
/* Set up all the qps on the first of the valid devices found */
- for (i = 0; i < 1; i++) {
- dev_id = ts_params->valid_devs[i];
+ dev_id = ts_params->valid_devs[0];
- rte_cryptodev_info_get(dev_id, &info);
+ rte_cryptodev_info_get(dev_id, &info);
- /*
- * Since we can't free and re-allocate queue memory always set
- * the queues on this device up to max size first so enough
- * memory is allocated for any later re-configures needed by
- * other tests
- */
-
- ts_params->conf.nb_queue_pairs = info.max_nb_queue_pairs;
- ts_params->conf.socket_id = SOCKET_ID_ANY;
- ts_params->conf.session_mp.nb_objs = info.sym.max_nb_sessions;
+ ts_params->conf.nb_queue_pairs = info.max_nb_queue_pairs;
+ ts_params->conf.socket_id = SOCKET_ID_ANY;
+ ts_params->conf.session_mp.nb_objs = info.sym.max_nb_sessions;
- TEST_ASSERT_SUCCESS(rte_cryptodev_configure(dev_id,
- &ts_params->conf),
- "Failed to configure cryptodev %u with %u qps",
- dev_id, ts_params->conf.nb_queue_pairs);
+ TEST_ASSERT_SUCCESS(rte_cryptodev_configure(dev_id,
+ &ts_params->conf),
+ "Failed to configure cryptodev %u with %u qps",
+ dev_id, ts_params->conf.nb_queue_pairs);
- ts_params->qp_conf.nb_descriptors = MAX_NUM_OPS_INFLIGHT;
+ ts_params->qp_conf.nb_descriptors = DEFAULT_NUM_OPS_INFLIGHT;
- for (qp_id = 0; qp_id < info.max_nb_queue_pairs; qp_id++) {
- TEST_ASSERT_SUCCESS(rte_cryptodev_queue_pair_setup(
- dev_id, qp_id, &ts_params->qp_conf,
- rte_cryptodev_socket_id(dev_id)),
- "Failed to setup queue pair %u on "
- "cryptodev %u",
- qp_id, dev_id);
- }
+ for (qp_id = 0; qp_id < info.max_nb_queue_pairs; qp_id++) {
+ TEST_ASSERT_SUCCESS(rte_cryptodev_queue_pair_setup(
+ dev_id, qp_id, &ts_params->qp_conf,
+ rte_cryptodev_socket_id(dev_id)),
+ "Failed to setup queue pair %u on cryptodev %u",
+ qp_id, dev_id);
}
return TEST_SUCCESS;
@@ -372,7 +362,6 @@ ut_setup(void)
memset(ut_params, 0, sizeof(*ut_params));
/* Reconfigure device to default parameters */
- ts_params->conf.nb_queue_pairs = DEFAULT_NUM_QPS_PER_QAT_DEVICE;
ts_params->conf.socket_id = SOCKET_ID_ANY;
ts_params->conf.session_mp.nb_objs = DEFAULT_NUM_OPS_INFLIGHT;
@@ -381,12 +370,6 @@ ut_setup(void)
"Failed to configure cryptodev %u",
ts_params->valid_devs[0]);
- /*
- * Now reconfigure queues to size we actually want to use in this
- * test suite.
- */
- ts_params->qp_conf.nb_descriptors = DEFAULT_NUM_OPS_INFLIGHT;
-
for (qp_id = 0; qp_id < ts_params->conf.nb_queue_pairs ; qp_id++) {
TEST_ASSERT_SUCCESS(rte_cryptodev_queue_pair_setup(
ts_params->valid_devs[0], qp_id,
@@ -396,7 +379,6 @@ ut_setup(void)
qp_id, ts_params->valid_devs[0]);
}
-
rte_cryptodev_stats_reset(ts_params->valid_devs[0]);
/* Start the device */
@@ -490,6 +472,7 @@ static int
test_device_configure_invalid_queue_pair_ids(void)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
+ uint16_t orig_nb_qps = ts_params->conf.nb_queue_pairs;
/* Stop the device in case it's started so it can be configured */
rte_cryptodev_stop(ts_params->valid_devs[0]);
@@ -544,6 +527,9 @@ test_device_configure_invalid_queue_pair_ids(void)
ts_params->valid_devs[0],
ts_params->conf.nb_queue_pairs);
+ /* revert to original testsuite value */
+ ts_params->conf.nb_queue_pairs = orig_nb_qps;
+
return TEST_SUCCESS;
}
diff --git a/app/test/test_cryptodev_perf.c b/app/test/test_cryptodev_perf.c
index 6af0896..323995e 100644
--- a/app/test/test_cryptodev_perf.c
+++ b/app/test/test_cryptodev_perf.c
@@ -386,14 +386,12 @@ testsuite_setup(void)
/*
* Using Crypto Device Id 0 by default.
- * Since we can't free and re-allocate queue memory always set the queues
- * on this device up to max size first so enough memory is allocated for
- * any later re-configures needed by other tests
+ * Set up all the qps on this device.
*/
rte_cryptodev_info_get(ts_params->dev_id, &info);
- ts_params->conf.nb_queue_pairs = DEFAULT_NUM_QPS_PER_QAT_DEVICE;
+ ts_params->conf.nb_queue_pairs = info.max_nb_queue_pairs;
ts_params->conf.socket_id = SOCKET_ID_ANY;
ts_params->conf.session_mp.nb_objs = info.sym.max_nb_sessions;
@@ -402,19 +400,6 @@ testsuite_setup(void)
"Failed to configure cryptodev %u",
ts_params->dev_id);
-
- ts_params->qp_conf.nb_descriptors = MAX_NUM_OPS_INFLIGHT;
-
- for (qp_id = 0; qp_id < ts_params->conf.nb_queue_pairs ; qp_id++) {
- TEST_ASSERT_SUCCESS(rte_cryptodev_queue_pair_setup(
- ts_params->dev_id, qp_id,
- &ts_params->qp_conf,
- rte_cryptodev_socket_id(ts_params->dev_id)),
- "Failed to setup queue pair %u on cryptodev %u",
- qp_id, ts_params->dev_id);
- }
-
- /*Now reconfigure queues to size we actually want to use in this testsuite.*/
ts_params->qp_conf.nb_descriptors = PERF_NUM_OPS_INFLIGHT;
for (qp_id = 0; qp_id < ts_params->conf.nb_queue_pairs ; qp_id++) {
diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c
index d3c46ac..3d49e2a 100644
--- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c
+++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c
@@ -311,8 +311,14 @@ aesni_mb_pmd_info_get(struct rte_cryptodev *dev,
static int
aesni_mb_pmd_qp_release(struct rte_cryptodev *dev, uint16_t qp_id)
{
- if (dev->data->queue_pairs[qp_id] != NULL) {
- rte_free(dev->data->queue_pairs[qp_id]);
+ struct aesni_mb_qp *qp = dev->data->queue_pairs[qp_id];
+ struct rte_ring *r = NULL;
+
+ if (qp != NULL) {
+ r = rte_ring_lookup(qp->name);
+ if (r)
+ rte_ring_free(r);
+ rte_free(qp);
dev->data->queue_pairs[qp_id] = NULL;
}
return 0;
--
2.5.0
^ permalink raw reply related
* Re: [RFC v2] Generic flow director/filtering/classification API
From: Adrien Mazarguil @ 2016-09-29 17:10 UTC (permalink / raw)
To: dev; +Cc: Thomas Monjalon
In-Reply-To: <cover.1471632644.git.adrien.mazarguil@6wind.com>
On Fri, Aug 19, 2016 at 08:50:44PM +0200, Adrien Mazarguil wrote:
> Hi All,
>
> Thanks to many for the positive and constructive feedback I've received so
> far. Here is the updated specification (v0.7) at last.
>
> I've attempted to address as many comments as possible but could not
> process them all just yet. A new section "Future evolutions" has been
> added for the remaining topics.
>
> This series adds rte_flow.h to the DPDK tree. Next time I will attempt to
> convert the specification as a documentation commit part of the patchset
> and actually implement API functions.
[...]
A quick update, we initially targeted 16.11 as the DPDK release this API
would be available for, turns out this goal was somewhat too optimistic as
September is ending and we are about to overshoot the deadline for
integration (basically everything took longer than expected, big surprise).
So instead of rushing things now to include a botched API in 16.11 with no
PMD support, we simply modified the target, now set to 17.02. On the plus
side this should leave developers more time to refine and test the API
before applications and PMDs start to use it.
I intend to send the patchset for the first non-draft version mid-October
worst case (ASAP in fact). I still haven't replied to several comments but
did take them into account, thanks for your feedback.
--
Adrien Mazarguil
6WIND
^ permalink raw reply
* [PATCH 3/4] bnxt: Add support for Async Link Notification
From: Ajit Khaparde @ 2016-09-29 17:03 UTC (permalink / raw)
To: dev
This patch adds support to get Link notification asynchronously.
The HW sends Async notifications on default completion ring. The
PMD processes these notifications and logs a message appropriately.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/Makefile | 1 +
drivers/net/bnxt/bnxt.h | 6 +-
drivers/net/bnxt/bnxt_cpr.c | 21 +++---
drivers/net/bnxt/bnxt_ethdev.c | 114 ++++++++++++++++++++++++++----
drivers/net/bnxt/bnxt_hwrm.c | 93 ++++++++++++------------
drivers/net/bnxt/bnxt_irq.c | 156 +++++++++++++++++++++++++++++++++++++++++
drivers/net/bnxt/bnxt_irq.h | 51 ++++++++++++++
7 files changed, 367 insertions(+), 75 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_irq.c
create mode 100644 drivers/net/bnxt/bnxt_irq.h
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
index d9c5a4c..65aaa92 100644
--- a/drivers/net/bnxt/Makefile
+++ b/drivers/net/bnxt/Makefile
@@ -59,6 +59,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_stats.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_txq.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_txr.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_irq.c
#
# Export include files
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 07b4cf2..4418c7f 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -95,7 +95,7 @@ struct bnxt_pf_info {
#define BNXT_LINK_WAIT_CNT 10
#define BNXT_LINK_WAIT_INTERVAL 100
struct bnxt_link_info {
- uint8_t phy_flags;
+ uint32_t phy_flags;
uint8_t mac_type;
uint8_t phy_link_status;
uint8_t loop_back;
@@ -159,6 +159,8 @@ struct bnxt {
#define MAX_FF_POOLS ETH_64_POOLS
STAILQ_HEAD(, bnxt_vnic_info) ff_pool[MAX_FF_POOLS];
+ struct bnxt_irq *irq_tbl;
+
#define MAX_NUM_MAC_ADDR 32
uint8_t mac_addr[ETHER_ADDR_LEN];
@@ -178,4 +180,6 @@ struct bnxt {
uint8_t dev_stopped;
};
+int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
+
#endif
diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c
index e9f9741..3aedcb8 100644
--- a/drivers/net/bnxt/bnxt_cpr.c
+++ b/drivers/net/bnxt/bnxt_cpr.c
@@ -42,28 +42,23 @@
/*
* Async event handling
*/
-void bnxt_handle_async_event(struct bnxt *bp __rte_unused,
+void bnxt_handle_async_event(struct bnxt *bp,
struct cmpl_base *cmp)
{
struct hwrm_async_event_cmpl *async_cmp =
(struct hwrm_async_event_cmpl *)cmp;
+ uint16_t event_id = rte_le_to_cpu_16(async_cmp->event_id);
/* TODO: HWRM async events are not defined yet */
/* Needs to handle: link events, error events, etc. */
- switch (async_cmp->event_id) {
- case 0:
- /* Assume LINK_CHANGE == 0 */
- RTE_LOG(INFO, PMD, "Link change event\n");
-
- /* Can just prompt the update_op routine to do a qcfg
- * instead of doing the actual qcfg
- */
- break;
- case 1:
+ switch (event_id) {
+ case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
+ case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
+ case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE:
+ bnxt_link_update_op(bp->eth_dev, 0);
break;
default:
- RTE_LOG(ERR, PMD, "handle_async_event id = 0x%x\n",
- async_cmp->event_id);
+ RTE_LOG(ERR, PMD, "handle_async_event id = 0x%x\n", event_id);
break;
}
}
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 1e3519b..2f15791 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -43,6 +43,7 @@
#include "bnxt_cpr.h"
#include "bnxt_filter.h"
#include "bnxt_hwrm.h"
+#include "bnxt_irq.h"
#include "bnxt_ring.h"
#include "bnxt_rxq.h"
#include "bnxt_rxr.h"
@@ -189,6 +190,7 @@ alloc_mem_err:
static int bnxt_init_chip(struct bnxt *bp)
{
unsigned int i, rss_idx, fw_idx;
+ struct rte_eth_link new;
int rc;
rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
@@ -275,6 +277,21 @@ static int bnxt_init_chip(struct bnxt *bp)
goto err_out;
}
+ rc = bnxt_get_hwrm_link_config(bp, &new);
+ if (rc) {
+ RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
+ goto err_out;
+ }
+
+ if (!bp->link_info.link_up) {
+ rc = bnxt_set_hwrm_link_config(bp, true);
+ if (rc) {
+ RTE_LOG(ERR, PMD,
+ "HWRM link config failure rc: %x\n", rc);
+ goto err_out;
+ }
+ }
+
return 0;
err_out:
@@ -366,6 +383,8 @@ static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
ETH_TXQ_FLAGS_NOOFFLOADS,
};
+ eth_dev->data->dev_conf.intr_conf.lsc = 1;
+
/* *INDENT-ON* */
/*
@@ -404,7 +423,6 @@ found:
static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
- int rc;
bp->rx_queues = (void *)eth_dev->data->rx_queues;
bp->tx_queues = (void *)eth_dev->data->tx_queues;
@@ -419,8 +437,56 @@ static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
eth_dev->data->mtu =
eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
- rc = bnxt_set_hwrm_link_config(bp, true);
- return rc;
+ return 0;
+}
+
+static inline int
+rte_bnxt_atomic_read_link_status(struct rte_eth_dev *eth_dev,
+ struct rte_eth_link *link)
+{
+ struct rte_eth_link *dst = link;
+ struct rte_eth_link *src = ð_dev->data->dev_link;
+
+ if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
+ *(uint64_t *)src) == 0)
+ return 1;
+
+ return 0;
+}
+
+static inline int
+rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
+ struct rte_eth_link *link)
+{
+ struct rte_eth_link *dst = ð_dev->data->dev_link;
+ struct rte_eth_link *src = link;
+
+ if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
+ *(uint64_t *)src) == 0)
+ return 1;
+
+ return 0;
+}
+
+static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
+{
+ struct rte_eth_link *link = ð_dev->data->dev_link;
+
+ if (link->link_status)
+ RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
+ (uint8_t)(eth_dev->data->port_id),
+ (uint32_t)link->link_speed,
+ (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
+ ("full-duplex") : ("half-duplex\n"));
+ else
+ RTE_LOG(INFO, PMD, "Port %d Link Down\n",
+ (uint8_t)(eth_dev->data->port_id));
+}
+
+static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
+{
+ bnxt_print_link_info(eth_dev);
+ return 0;
}
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
@@ -436,18 +502,31 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
goto error;
}
+ rc = bnxt_setup_int(bp);
+ if (rc)
+ goto error;
+
rc = bnxt_alloc_mem(bp);
if (rc)
goto error;
+ rc = bnxt_request_int(bp);
+ if (rc)
+ goto error;
+
rc = bnxt_init_nic(bp);
if (rc)
goto error;
+ bnxt_enable_int(bp);
+
+ bnxt_link_update_op(eth_dev, 0);
return 0;
error:
bnxt_shutdown_nic(bp);
+ bnxt_disable_int(bp);
+ bnxt_free_int(bp);
bnxt_free_tx_mbufs(bp);
bnxt_free_rx_mbufs(bp);
bnxt_free_mem(bp);
@@ -482,6 +561,8 @@ static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
eth_dev->data->dev_link.link_status = 0;
}
bnxt_set_hwrm_link_config(bp, false);
+ bnxt_disable_int(bp);
+ bnxt_free_int(bp);
bnxt_shutdown_nic(bp);
bp->dev_stopped = 1;
}
@@ -580,8 +661,7 @@ static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
bnxt_hwrm_set_filter(bp, vnic, filter);
}
-static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
- int wait_to_complete)
+int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
{
int rc = 0;
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -599,21 +679,20 @@ static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
"Failed to retrieve link rc = 0x%x!", rc);
goto out;
}
- if (!wait_to_complete)
- break;
-
rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
+ if (!wait_to_complete)
+ break;
} while (!new.link_status && cnt--);
+out:
/* Timed out or success */
- if (new.link_status) {
- /* Update only if success */
- eth_dev->data->dev_link.link_duplex = new.link_duplex;
- eth_dev->data->dev_link.link_speed = new.link_speed;
+ if (new.link_status != eth_dev->data->dev_link.link_status ||
+ new.link_speed != eth_dev->data->dev_link.link_speed) {
+ rte_bnxt_atomic_write_link_status(eth_dev, &new);
+ bnxt_print_link_info(eth_dev);
}
- eth_dev->data->dev_link.link_status = new.link_status;
-out:
+
return rc;
}
@@ -724,6 +803,11 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
/* EW - need to revisit here copying from u64 to u16 */
memcpy(reta_conf, vnic->rss_table, reta_size);
+ if (rte_intr_allow_others(ð_dev->pci_dev->intr_handle)) {
+ if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
+ bnxt_dev_lsc_intr_setup(eth_dev);
+ }
+
return 0;
}
@@ -1123,7 +1207,7 @@ static struct eth_driver bnxt_rte_pmd = {
.name = "rte_" DRV_MODULE_NAME "_pmd",
.id_table = bnxt_pci_id_map,
.drv_flags = RTE_PCI_DRV_NEED_MAPPING |
- RTE_PCI_DRV_DETACHABLE,
+ RTE_PCI_DRV_DETACHABLE | RTE_PCI_DRV_INTR_LSC,
},
.eth_dev_init = bnxt_dev_init,
.eth_dev_uninit = bnxt_dev_uninit,
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index e10b9cd..cf79fc6 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -342,13 +342,16 @@ int bnxt_hwrm_func_driver_register(struct bnxt *bp, uint32_t flags,
HWRM_PREP(req, FUNC_DRV_RGTR, -1, resp);
req.flags = flags;
- req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER;
+ req.enables = HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
+ HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD;
req.ver_maj = RTE_VER_YEAR;
req.ver_min = RTE_VER_MONTH;
req.ver_upd = RTE_VER_MINOR;
memcpy(req.vf_req_fwd, vf_req_fwd, sizeof(req.vf_req_fwd));
+ req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
+
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
HWRM_CHECK_RESULT;
@@ -470,49 +473,44 @@ int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
{
int rc = 0;
- struct hwrm_port_phy_cfg_input req = {.req_type = 0};
+ struct hwrm_port_phy_cfg_input req = {0};
struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
+ uint32_t enables = 0;
HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
- req.flags = conf->phy_flags;
if (conf->link_up) {
- req.force_link_speed = conf->link_speed;
+ req.flags = rte_cpu_to_le_32(conf->phy_flags);
+ req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
/*
* Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
* any auto mode, even "none".
*/
- if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
- req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
- } else {
- req.auto_mode = conf->auto_mode;
- req.enables |=
- HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
+ if (!conf->link_speed) {
+ req.auto_mode |= conf->auto_mode;
+ enables = HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
req.auto_link_speed_mask = conf->auto_link_speed_mask;
- req.enables |=
+ enables |=
HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
- req.auto_link_speed = conf->auto_link_speed;
- req.enables |=
+ req.auto_link_speed = bp->link_info.auto_link_speed;
+ enables |=
HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
}
req.auto_duplex = conf->duplex;
- req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
+ enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
req.auto_pause = conf->auto_pause;
+ req.force_pause = conf->force_pause;
/* Set force_pause if there is no auto or if there is a force */
- if (req.auto_pause)
- req.enables |=
- HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
+ if (req.auto_pause && !req.force_pause)
+ enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
else
- req.enables |=
- HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
- req.force_pause = conf->force_pause;
- if (req.force_pause)
- req.enables |=
- HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
+ enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
+
+ req.enables = rte_cpu_to_le_32(enables);
} else {
- req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
- req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
- req.force_link_speed = 0;
+ req.flags =
+ rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN);
+ RTE_LOG(INFO, PMD, "Force Link Down\n");
}
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
@@ -526,7 +524,7 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
struct bnxt_link_info *link_info)
{
int rc = 0;
- struct hwrm_port_phy_qcfg_input req = {.req_type = 0};
+ struct hwrm_port_phy_qcfg_input req = {0};
struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
HWRM_PREP(req, PORT_PHY_QCFG, -1, resp);
@@ -536,7 +534,7 @@ static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
HWRM_CHECK_RESULT;
link_info->phy_link_status = resp->link;
- if (link_info->phy_link_status == HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) {
+ if (link_info->phy_link_status != HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK) {
link_info->link_up = 1;
link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
} else {
@@ -811,7 +809,7 @@ int bnxt_hwrm_stat_ctx_free(struct bnxt *bp,
int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
int rc = 0, i, j;
- struct hwrm_vnic_alloc_input req = {.req_type = 0 };
+ struct hwrm_vnic_alloc_input req = { 0 };
struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
/* map ring groups to this vnic */
@@ -1252,42 +1250,42 @@ static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
{
uint16_t eth_link_speed = 0;
- if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
+ if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
return ETH_LINK_SPEED_AUTONEG;
switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
case ETH_LINK_SPEED_100M:
case ETH_LINK_SPEED_100M_HD:
eth_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
break;
case ETH_LINK_SPEED_1G:
eth_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
break;
case ETH_LINK_SPEED_2_5G:
eth_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
break;
case ETH_LINK_SPEED_10G:
eth_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
+ HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
break;
case ETH_LINK_SPEED_20G:
eth_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
break;
case ETH_LINK_SPEED_25G:
eth_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
break;
case ETH_LINK_SPEED_40G:
eth_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
+ HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
break;
case ETH_LINK_SPEED_50G:
eth_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
+ HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
break;
default:
RTE_LOG(ERR, PMD,
@@ -1463,33 +1461,36 @@ int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
goto error;
memset(&link_req, 0, sizeof(link_req));
- speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
link_req.link_up = link_up;
+ if (!link_up)
+ goto port_phy_cfg;
+
+ speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
+ link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
if (speed == 0) {
- link_req.phy_flags =
+ link_req.phy_flags |=
HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
link_req.auto_mode =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
+ HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
link_req.auto_link_speed_mask =
bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
- link_req.auto_link_speed =
- HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
} else {
- link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
- link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
- HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
+ link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
link_req.link_speed = speed;
+ RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
}
link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
link_req.auto_pause = bp->link_info.auto_pause;
link_req.force_pause = bp->link_info.force_pause;
+port_phy_cfg:
rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
if (rc) {
RTE_LOG(ERR, PMD,
"Set link config failed with rc %d\n", rc);
}
+ rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
error:
return rc;
}
diff --git a/drivers/net/bnxt/bnxt_irq.c b/drivers/net/bnxt/bnxt_irq.c
new file mode 100644
index 0000000..e93585a
--- /dev/null
+++ b/drivers/net/bnxt/bnxt_irq.c
@@ -0,0 +1,156 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2014-2015 Broadcom Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <inttypes.h>
+
+#include <rte_malloc.h>
+
+#include "bnxt.h"
+#include "bnxt_cpr.h"
+#include "bnxt_irq.h"
+#include "bnxt_ring.h"
+#include "hsi_struct_def_dpdk.h"
+
+/*
+ * Interrupts
+ */
+
+static void bnxt_int_handler(struct rte_intr_handle *handle __rte_unused,
+ void *param)
+{
+ struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
+ struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
+ struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ struct cmpl_base *cmp;
+
+ while (1) {
+ cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
+ cmp = &cpr->cp_desc_ring[cons];
+
+ if (!CMP_VALID(cmp, raw_cons, cpr->cp_ring_struct))
+ break;
+
+ switch (CMP_TYPE(cmp)) {
+ case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
+ /* Handle any async event */
+ bnxt_handle_async_event(bp, cmp);
+ break;
+ case CMPL_BASE_TYPE_HWRM_FWD_RESP:
+ /* Handle HWRM forwarded responses */
+ bnxt_handle_fwd_req(bp, cmp);
+ break;
+ default:
+ /* Ignore any other events */
+ break;
+ }
+ raw_cons = NEXT_RAW_CMP(raw_cons);
+ }
+ B_CP_DB_REARM(cpr, cpr->cp_raw_cons);
+}
+
+void bnxt_free_int(struct bnxt *bp)
+{
+ struct bnxt_irq *irq;
+
+ irq = bp->irq_tbl;
+ if (irq) {
+ if (irq->requested) {
+ rte_intr_disable(&bp->pdev->intr_handle);
+ rte_intr_callback_unregister(&bp->pdev->intr_handle,
+ irq->handler,
+ (void *)bp->eth_dev);
+ irq->requested = 0;
+ }
+ rte_free((void *)bp->irq_tbl);
+ bp->irq_tbl = NULL;
+ }
+}
+
+void bnxt_disable_int(struct bnxt *bp)
+{
+ struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
+
+ /* Only the default completion ring */
+ B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
+}
+
+void bnxt_enable_int(struct bnxt *bp)
+{
+ struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
+
+ B_CP_DB_REARM(cpr, cpr->cp_raw_cons);
+}
+
+int bnxt_setup_int(struct bnxt *bp)
+{
+ uint16_t total_vecs;
+ const int len = sizeof(bp->irq_tbl[0].name);
+ int i, rc = 0;
+
+ /* DPDK host only supports 1 MSI-X vector */
+ total_vecs = 1;
+ bp->irq_tbl = rte_calloc("bnxt_irq_tbl", total_vecs,
+ sizeof(struct bnxt_irq), 0);
+ if (bp->irq_tbl) {
+ for (i = 0; i < total_vecs; i++) {
+ bp->irq_tbl[i].vector = i;
+ snprintf(bp->irq_tbl[i].name, len,
+ "%s-%d", bp->eth_dev->data->name, i);
+ bp->irq_tbl[i].handler = bnxt_int_handler;
+ }
+ } else {
+ rc = -ENOMEM;
+ goto setup_exit;
+ }
+ return 0;
+
+setup_exit:
+ RTE_LOG(ERR, PMD, "bnxt_irq_tbl setup failed");
+ return rc;
+}
+
+int bnxt_request_int(struct bnxt *bp)
+{
+ int rc = 0;
+
+ struct bnxt_irq *irq = bp->irq_tbl;
+
+ rte_intr_callback_register(&bp->pdev->intr_handle, irq->handler,
+ (void *)bp->eth_dev);
+ rte_intr_enable(&bp->pdev->intr_handle);
+
+ irq->requested = 1;
+ return rc;
+}
diff --git a/drivers/net/bnxt/bnxt_irq.h b/drivers/net/bnxt/bnxt_irq.h
new file mode 100644
index 0000000..e21bec5
--- /dev/null
+++ b/drivers/net/bnxt/bnxt_irq.h
@@ -0,0 +1,51 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2014-2015 Broadcom Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BNXT_IRQ_H_
+#define _BNXT_IRQ_H_
+
+struct bnxt_irq {
+ rte_intr_callback_fn handler;
+ unsigned int vector;
+ uint8_t requested;
+ char name[RTE_ETH_NAME_MAX_LEN + 2];
+};
+
+struct bnxt;
+void bnxt_free_int(struct bnxt *bp);
+void bnxt_disable_int(struct bnxt *bp);
+void bnxt_enable_int(struct bnxt *bp);
+int bnxt_setup_int(struct bnxt *bp);
+int bnxt_request_int(struct bnxt *bp);
+
+#endif
--
2.4.3
^ permalink raw reply related
* [PATCH 4/4] bnxt: Update the Broadcom PMD driver documentation
From: Ajit Khaparde @ 2016-09-29 17:04 UTC (permalink / raw)
To: dev
This patch reformats the Broadcom PMD driver documentation
based on recommendations from previous review referenced below:
http://dpdk.org/dev/patchwork/patch/16144/
Also since the PMD now loads on a VF interface, update the
documentation accordingly.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/nics/bnxt.rst | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/doc/guides/nics/bnxt.rst b/doc/guides/nics/bnxt.rst
index cf7fca8..e9f9c9e 100644
--- a/doc/guides/nics/bnxt.rst
+++ b/doc/guides/nics/bnxt.rst
@@ -31,19 +31,21 @@ bnxt poll mode driver library
=============================
The bnxt poll mode library (**librte_pmd_bnxt**) implements support for:
-**Broadcom NetXtreme-C®/NetXtreme-E® BCM5730X and BCM5740X family of
-Ethernet Network Controllers**. These adapters support Standards compliant
+
+* **Broadcom NetXtreme-C®/NetXtreme-E® BCM5730X and BCM5740X family of
+Ethernet Network Controllers**: These adapters support Standards compliant
10/25/50Gbps 30MPPS full-duplex throughput.
-**Broadcom StrataGX® BCM5871X Series of Communucations Processors**
-These ARM based processors target a broad range of networking applications
-including virtual CPE (vCPE) and NFV appliances, 10G service routers and
-gateways, control plane processing for Ethernet switches and network attached
-storage (NAS).
Information about the NetXtreme family of adapters can be found in the
`NetXtreme® Brand section <https://www.broadcom.com/products/ethernet-communication-and-switching?technology%5B%5D=88>`_
of the `Broadcom website <http://www.broadcom.com/>`_.
+* **Broadcom StrataGX® BCM5871X Series of Communucations Processors**:
+These ARM based processors target a broad range of networking applications
+including virtual CPE (vCPE) and NFV appliances, 10G service routers and
+gateways, control plane processing for Ethernet switches and network
+attached storage (NAS).
+
Information about the StrataGX family of adapters can be found in the
`StrataGX® BCM5871X Series section
<http://www.broadcom.com/products/enterprise-and-network-processors/processors/bcm58712>`_
@@ -56,5 +58,3 @@ With the current driver, allocated mbufs must be large enough to hold
the entire received frame. If the mbufs are not large enough, the
packets will be dropped. This is most limiting when jumbo frames are
used.
-
-SR-IOV is not supported.
--
2.4.3
^ permalink raw reply related
* [PATCH 0/4] bnxt patch series
From: Ajit Khaparde @ 2016-09-29 17:03 UTC (permalink / raw)
To: dev
Please consider applying this patch series.
This series is expected to be applied over the previous patchset
once it is accepted.
Depends on: [v2,15/15] bnxt: Update struct definitions to use the 1.5.1
HWRM API
http://dpdk.org/dev/patchwork/patch/16154/
Ajit Khaparde (4):
testpmd: Add support to configure 25G and 50G speeds
bnxt: Fix a segfault encountered during KNI exit
bnxt: Add support for Async Link Notification
bnxt: Update the Broadcom PMD driver documentation
app/test-pmd/cmdline.c | 14 ++-
doc/guides/nics/bnxt.rst | 18 ++--
doc/guides/testpmd_app_ug/testpmd_funcs.rst | 2 +-
drivers/net/bnxt/Makefile | 1 +
drivers/net/bnxt/bnxt.h | 7 +-
drivers/net/bnxt/bnxt_cpr.c | 21 ++--
drivers/net/bnxt/bnxt_ethdev.c | 148 +++++++++++++++++++++-----
drivers/net/bnxt/bnxt_hwrm.c | 93 +++++++++--------
drivers/net/bnxt/bnxt_irq.c | 156 ++++++++++++++++++++++++++++
drivers/net/bnxt/bnxt_irq.h | 51 +++++++++
10 files changed, 409 insertions(+), 102 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_irq.c
create mode 100644 drivers/net/bnxt/bnxt_irq.h
--
2.4.3
^ permalink raw reply
* [PATCH 2/4] bnxt: Fix a segfault encountered during KNI exit
From: Ajit Khaparde @ 2016-09-29 17:03 UTC (permalink / raw)
To: dev
The bnxt PMD is running into a segfault when exiting out of KNI
in the dev_uninit/close path. This patch fixes that.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 1 +
drivers/net/bnxt/bnxt_ethdev.c | 34 ++++++++++++++++++++++------------
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index c77ecef..07b4cf2 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -175,6 +175,7 @@ struct bnxt {
struct bnxt_pf_info pf;
struct bnxt_vf_info vf;
uint8_t port_partition_type;
+ uint8_t dev_stopped;
};
#endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index bd1ffc0..1e3519b 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -428,6 +428,7 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
int rc;
+ bp->dev_stopped = 0;
rc = bnxt_hwrm_func_reset(bp);
if (rc) {
RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
@@ -471,10 +472,27 @@ static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
return 0;
}
+/* Unload the driver, release resources */
+static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
+{
+ struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
+
+ if (bp->eth_dev->data->dev_started) {
+ /* TBD: STOP HW queues DMA */
+ eth_dev->data->dev_link.link_status = 0;
+ }
+ bnxt_set_hwrm_link_config(bp, false);
+ bnxt_shutdown_nic(bp);
+ bp->dev_stopped = 1;
+}
+
static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
+ if (bp->dev_stopped == 0)
+ bnxt_dev_stop_op(eth_dev);
+
bnxt_free_tx_mbufs(bp);
bnxt_free_rx_mbufs(bp);
bnxt_free_mem(bp);
@@ -488,18 +506,6 @@ static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
}
}
-/* Unload the driver, release resources */
-static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
-{
- struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
-
- if (bp->eth_dev->data->dev_started) {
- /* TBD: STOP HW queues DMA */
- eth_dev->data->dev_link.link_status = 0;
- }
- bnxt_shutdown_nic(bp);
-}
-
static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
uint32_t index)
{
@@ -1078,6 +1084,8 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev)
eth_dev->pci_dev->mem_resource[0].phys_addr,
eth_dev->pci_dev->mem_resource[0].addr);
+ bp->dev_stopped = 0;
+
return 0;
error_free:
@@ -1101,6 +1109,8 @@ bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
}
rc = bnxt_hwrm_func_driver_unregister(bp, 0);
bnxt_free_hwrm_resources(bp);
+ if (bp->dev_stopped == 0)
+ bnxt_dev_close_op(eth_dev);
eth_dev->dev_ops = NULL;
eth_dev->rx_pkt_burst = NULL;
eth_dev->tx_pkt_burst = NULL;
--
2.4.3
^ permalink raw reply related
* [PATCH 1/4] testpmd: Add support to configure 25G and 50G speeds
From: Ajit Khaparde @ 2016-09-29 17:03 UTC (permalink / raw)
To: dev
Support to configure 25G and 50G speeds is missing from testpmd.
This patch also updates the testpmd user guide accordingly.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
app/test-pmd/cmdline.c | 14 +++++++++-----
doc/guides/testpmd_app_ug/testpmd_funcs.rst | 2 +-
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c
index 17d238f..6ffa771 100644
--- a/app/test-pmd/cmdline.c
+++ b/app/test-pmd/cmdline.c
@@ -545,7 +545,7 @@ static void cmd_help_long_parsed(void *parsed_result,
" Detach physical or virtual dev by port_id\n\n"
"port config (port_id|all)"
- " speed (10|100|1000|10000|40000|100000|auto)"
+ " speed (10|100|1000|10000|25000|40000|50000|100000|auto)"
" duplex (half|full|auto)\n"
" Set speed and duplex for all ports or port_id\n\n"
@@ -1016,8 +1016,12 @@ parse_and_check_speed_duplex(char *speedstr, char *duplexstr, uint32_t *speed)
*speed = ETH_LINK_SPEED_1G;
} else if (!strcmp(speedstr, "10000")) {
*speed = ETH_LINK_SPEED_10G;
+ } else if (!strcmp(speedstr, "25000")) {
+ *speed = ETH_LINK_SPEED_25G;
} else if (!strcmp(speedstr, "40000")) {
*speed = ETH_LINK_SPEED_40G;
+ } else if (!strcmp(speedstr, "50000")) {
+ *speed = ETH_LINK_SPEED_50G;
} else if (!strcmp(speedstr, "100000")) {
*speed = ETH_LINK_SPEED_100G;
} else if (!strcmp(speedstr, "auto")) {
@@ -1067,7 +1071,7 @@ cmdline_parse_token_string_t cmd_config_speed_all_item1 =
TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, item1, "speed");
cmdline_parse_token_string_t cmd_config_speed_all_value1 =
TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, value1,
- "10#100#1000#10000#40000#100000#auto");
+ "10#100#1000#10000#25000#40000#50000#100000#auto");
cmdline_parse_token_string_t cmd_config_speed_all_item2 =
TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, item2, "duplex");
cmdline_parse_token_string_t cmd_config_speed_all_value2 =
@@ -1077,7 +1081,7 @@ cmdline_parse_token_string_t cmd_config_speed_all_value2 =
cmdline_parse_inst_t cmd_config_speed_all = {
.f = cmd_config_speed_all_parsed,
.data = NULL,
- .help_str = "port config all speed 10|100|1000|10000|40000|100000|auto duplex "
+ .help_str = "port config all speed 10|100|1000|10000|25000|40000|50000|100000|auto duplex "
"half|full|auto",
.tokens = {
(void *)&cmd_config_speed_all_port,
@@ -1141,7 +1145,7 @@ cmdline_parse_token_string_t cmd_config_speed_specific_item1 =
"speed");
cmdline_parse_token_string_t cmd_config_speed_specific_value1 =
TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, value1,
- "10#100#1000#10000#40000#100000#auto");
+ "10#100#1000#10000#25000#40000#50000#100000#auto");
cmdline_parse_token_string_t cmd_config_speed_specific_item2 =
TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, item2,
"duplex");
@@ -1152,7 +1156,7 @@ cmdline_parse_token_string_t cmd_config_speed_specific_value2 =
cmdline_parse_inst_t cmd_config_speed_specific = {
.f = cmd_config_speed_specific_parsed,
.data = NULL,
- .help_str = "port config X speed 10|100|1000|10000|40000|100000|auto duplex "
+ .help_str = "port config X speed 10|100|1000|10000|25000|40000|50000|100000|auto duplex "
"half|full|auto",
.tokens = {
(void *)&cmd_config_speed_specific_port,
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index f87e0c2..e1eea34 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -1167,7 +1167,7 @@ port config - speed
Set the speed and duplex mode for all ports or a specific port::
- testpmd> port config (port_id|all) speed (10|100|1000|10000|40000|100000|auto) \
+ testpmd> port config (port_id|all) speed (10|100|1000|10000|25000|40000|50000|100000|auto) \
duplex (half|full|auto)
port config - queues/descriptors
--
2.4.3
^ permalink raw reply related
* Re: [PATCH v3 5/6] ixgbe: add Tx preparation
From: Ananyev, Konstantin @ 2016-09-29 17:01 UTC (permalink / raw)
To: Kulasek, TomaszX, dev@dpdk.org
In-Reply-To: <3042915272161B4EB253DA4D77EB373A14F33D37@IRSMSX102.ger.corp.intel.com>
I Tomasz,
> >
> > Just thought about it once again:
> > As now inside rte_eth_tx_prep() we do now:
> > +
> > + if (!dev->tx_pkt_prep)
> > + return nb_pkts;
> >
> > Then there might be a better approach to set
> > dev->tx_pkt_prep = NULL
> > for simple and vector TX functions?
> >
> > After all, prep_simple() does nothing but returns an error if
> > conditions are not met.
> > And if simple TX was already selected, then that means that user
> > deliberately disabled all HW TX offloads in favor of faster TX and
> > there is no point to slow him down with extra checks here.
> > Same for i40e and fm10k.
> > What is your opinion?
> >
> > Konstantin
> >
>
> Yes, if performance is a key, and, while the limitations of vector/simple path are quite well documented, these additional checks are a
> bit overzealous. We may assume that to made tx offloads working, we need to configure driver in a right way, and this is a
> configuration issue if something doesn't work.
>
> I will remove it.
Great, thanks.
Konstantin
^ permalink raw reply
* Re: [PATCH v5 1/3] librte_ether: add API for VF management
From: Thomas Monjalon @ 2016-09-29 16:45 UTC (permalink / raw)
To: Iremonger, Bernard
Cc: dev, Shah, Rahul R, Lu, Wenzhuo, az5157@att.com, azelezniak
In-Reply-To: <8CEF83825BEC744B83065625E567D7C21A08E198@IRSMSX108.ger.corp.intel.com>
2016-09-29 16:38, Iremonger, Bernard:
> Hi Thomas,
>
> > Subject: Re: [dpdk-dev] [PATCH v5 1/3] librte_ether: add API for VF
> > management
> >
> > 2016-09-29 15:16, Iremonger, Bernard:
> > > > 2016-09-29 15:16, Bernard Iremonger:
> > > > > +int
> > > > > +rte_eth_dev_set_vf_vlan_stripq(uint8_t port, uint16_t vf, int
> > > > > +on);
> > > >
> > > > Why keeping this function in ethdev?
> > >
> > > This function is using an existing API in the eth_dev_ops structure.
> > >
> > > dev->dev_ops->vlan_strip_queue_set
> > >
> > > The vlan_strip_queue_set API is used by the i40e, ixgbe and mlx5 PMD's.
> >
> > OK but it was not used to control VF from PF.
> > This line:
> > (*dev->dev_ops->vlan_strip_queue_set)(dev, q + vf *
> > queues_per_pool, on); seems Intel specific.
> > Please keep "VF from PF" outside of ethdev for 16.11.
>
> I will try calling (*dev->dev_ops->vlan_strip_queue_set) from an ixgbe-specific function.
> Will this be acceptable?
I think it is acceptable.
^ permalink raw reply
* Re: [PATCH v5 1/3] librte_ether: add API for VF management
From: Iremonger, Bernard @ 2016-09-29 16:38 UTC (permalink / raw)
To: Thomas Monjalon
Cc: dev@dpdk.org, Shah, Rahul R, Lu, Wenzhuo, az5157@att.com,
azelezniak
In-Reply-To: <1953384.ANuSY1Omf7@xps13>
Hi Thomas,
> Subject: Re: [dpdk-dev] [PATCH v5 1/3] librte_ether: add API for VF
> management
>
> 2016-09-29 15:16, Iremonger, Bernard:
> > > 2016-09-29 15:16, Bernard Iremonger:
> > > > +int
> > > > +rte_eth_dev_set_vf_vlan_stripq(uint8_t port, uint16_t vf, int
> > > > +on);
> > >
> > > Why keeping this function in ethdev?
> >
> > This function is using an existing API in the eth_dev_ops structure.
> >
> > dev->dev_ops->vlan_strip_queue_set
> >
> > The vlan_strip_queue_set API is used by the i40e, ixgbe and mlx5 PMD's.
>
> OK but it was not used to control VF from PF.
> This line:
> (*dev->dev_ops->vlan_strip_queue_set)(dev, q + vf *
> queues_per_pool, on); seems Intel specific.
> Please keep "VF from PF" outside of ethdev for 16.11.
I will try calling (*dev->dev_ops->vlan_strip_queue_set) from an ixgbe-specific function.
Will this be acceptable?
Regards,
Bernard.
^ permalink raw reply
* Re: [PATCH] eal: fix bug in x86 cmpset
From: Thomas Monjalon @ 2016-09-29 16:34 UTC (permalink / raw)
To: Nikhil Rao; +Cc: dev
In-Reply-To: <1475184293-18298-1-git-send-email-nikhil.rao@intel.com>
2016-09-30 02:54, Nikhil Rao:
> The original code used movl instead of xchgl, this caused
> rte_atomic64_cmpset to use ebx as the lower dword of the source
> to cmpxchg8b instead of the lower dword of function argument "src".
Could you please start the explanation with a statement of
what is wrong from an user point of view?
It could help to understand how severe it is.
^ permalink raw reply
* Re: [PATCH v5 2/3] net/ixgbe: add API's for VF management
From: Iremonger, Bernard @ 2016-09-29 16:32 UTC (permalink / raw)
To: Pattan, Reshma, dev@dpdk.org, Shah, Rahul R, Lu, Wenzhuo,
az5157@att.com
Cc: azelezniak
In-Reply-To: <6299e840-0ea7-4dd2-dff0-a3b2fb9640bf@intel.com>
Hi Reshma,
> -----Original Message-----
> From: Pattan, Reshma
> Sent: Thursday, September 29, 2016 5:11 PM
> To: Iremonger, Bernard <bernard.iremonger@intel.com>; dev@dpdk.org;
> Shah, Rahul R <rahul.r.shah@intel.com>; Lu, Wenzhuo
> <wenzhuo.lu@intel.com>; az5157@att.com
> Cc: azelezniak <alexz@att.com>
> Subject: Re: [dpdk-dev] [PATCH v5 2/3] net/ixgbe: add API's for VF
> management
>
> Hi,
>
>
> On 9/29/2016 3:16 PM, Bernard Iremonger wrote:
> > diff --git a/drivers/net/ixgbe/Makefile b/drivers/net/ixgbe/Makefile
> > index a6c71f3..7493b8d 100644
> > --- a/drivers/net/ixgbe/Makefile
> > +++ b/drivers/net/ixgbe/Makefile
> > @@ -119,6 +119,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) +=
> ixgbe_bypass.c
> > SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82599_bypass.c
> > endif
> >
> > +# install this header file
> > +SYMLINK-$(CONFIG_RTE_LIBRTE_ACL)-include := rte_pmd_ixgbe.h
> >
>
> In correct config flag CONFIG_RTE_LIBRTE_ACL , should be
> CONFIG_RTE_LIBRTE_IXGBE_PMD
>
> Thanks,
> Reshma
I will correct this in v6 patchset.
Regards,
Bernard.
^ permalink raw reply
* Re: [PATCH v5 2/3] net/ixgbe: add API's for VF management
From: Iremonger, Bernard @ 2016-09-29 16:30 UTC (permalink / raw)
To: Pattan, Reshma, dev@dpdk.org, Shah, Rahul R, Lu, Wenzhuo,
az5157@att.com
Cc: azelezniak
In-Reply-To: <3AEA2BF9852C6F48A459DA490692831F010A9B49@IRSMSX109.ger.corp.intel.com>
Hi Reshma,
> -----Original Message-----
> From: Pattan, Reshma
> Sent: Thursday, September 29, 2016 5:16 PM
> To: Iremonger, Bernard <bernard.iremonger@intel.com>; dev@dpdk.org;
> Shah, Rahul R <rahul.r.shah@intel.com>; Lu, Wenzhuo
> <wenzhuo.lu@intel.com>; az5157@att.com
> Cc: Iremonger, Bernard <bernard.iremonger@intel.com>; azelezniak
> <alexz@att.com>
> Subject: RE: [dpdk-dev] [PATCH v5 2/3] net/ixgbe: add API's for VF
> management
>
> Hi,
>
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Bernard
> Iremonger
> > Sent: Thursday, September 29, 2016 3:17 PM
> > To: dev@dpdk.org; Shah, Rahul R <rahul.r.shah@intel.com>; Lu, Wenzhuo
> > <wenzhuo.lu@intel.com>; az5157@att.com
> > Cc: Iremonger, Bernard <bernard.iremonger@intel.com>; azelezniak
> > <alexz@att.com>
> > Subject: [dpdk-dev] [PATCH v5 2/3] net/ixgbe: add API's for VF
> > management
> >
> > diff --git a/drivers/net/ixgbe/Makefile b/drivers/net/ixgbe/Makefile
> > index a6c71f3..7493b8d 100644
> > --- a/drivers/net/ixgbe/Makefile
> > +++ b/drivers/net/ixgbe/Makefile
> > @@ -119,6 +119,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) +=
> > ixgbe_bypass.c
> > SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82599_bypass.c
> endif
> >
> > +# install this header file
> > +SYMLINK-$(CONFIG_RTE_LIBRTE_ACL)-include := rte_pmd_ixgbe.h
> >
>
> Config flag should be CONFIG_RTE_LIBRTE_IXGBE_PMD .
>
> Thanks,
> Reshma
I will correct this in v6 patchset.
Regards,
Bernard.
^ permalink raw reply
* Re: [PATCH v5 1/3] librte_ether: add API for VF management
From: Thomas Monjalon @ 2016-09-29 16:19 UTC (permalink / raw)
To: Iremonger, Bernard
Cc: dev, Shah, Rahul R, Lu, Wenzhuo, az5157@att.com, azelezniak
In-Reply-To: <8CEF83825BEC744B83065625E567D7C21A08E0CA@IRSMSX108.ger.corp.intel.com>
2016-09-29 15:16, Iremonger, Bernard:
> > 2016-09-29 15:16, Bernard Iremonger:
> > > +int
> > > +rte_eth_dev_set_vf_vlan_stripq(uint8_t port, uint16_t vf, int on);
> >
> > Why keeping this function in ethdev?
>
> This function is using an existing API in the eth_dev_ops structure.
>
> dev->dev_ops->vlan_strip_queue_set
>
> The vlan_strip_queue_set API is used by the i40e, ixgbe and mlx5 PMD's.
OK but it was not used to control VF from PF.
This line:
(*dev->dev_ops->vlan_strip_queue_set)(dev, q + vf * queues_per_pool, on);
seems Intel specific.
Please keep "VF from PF" outside of ethdev for 16.11.
> > I think it would be more consistent to have also existing VF functions moving
> > from ethdev to rte_pmd_ixgbe.h.
> > You cannot remove them, but you can create their ixgbe-specific version and
> > announce that the ethdev ones are deprecated.
>
> There are 5 existing VF functions which are only used by ixgbe PMD at present.
> It would make sense to create ixgbe-specific versions, however I think this should be done in a separate patchset.
Yes it can be a separate patchset for RC2 of course.
^ permalink raw reply
* Re: [PATCH v5 2/3] net/ixgbe: add API's for VF management
From: Pattan, Reshma @ 2016-09-29 16:16 UTC (permalink / raw)
To: Iremonger, Bernard, dev@dpdk.org, Shah, Rahul R, Lu, Wenzhuo,
az5157@att.com
Cc: Iremonger, Bernard, azelezniak
In-Reply-To: <1475158591-2243-3-git-send-email-bernard.iremonger@intel.com>
Hi,
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Bernard Iremonger
> Sent: Thursday, September 29, 2016 3:17 PM
> To: dev@dpdk.org; Shah, Rahul R <rahul.r.shah@intel.com>; Lu, Wenzhuo
> <wenzhuo.lu@intel.com>; az5157@att.com
> Cc: Iremonger, Bernard <bernard.iremonger@intel.com>; azelezniak
> <alexz@att.com>
> Subject: [dpdk-dev] [PATCH v5 2/3] net/ixgbe: add API's for VF management
>
> diff --git a/drivers/net/ixgbe/Makefile b/drivers/net/ixgbe/Makefile index
> a6c71f3..7493b8d 100644
> --- a/drivers/net/ixgbe/Makefile
> +++ b/drivers/net/ixgbe/Makefile
> @@ -119,6 +119,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) +=
> ixgbe_bypass.c
> SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82599_bypass.c endif
>
> +# install this header file
> +SYMLINK-$(CONFIG_RTE_LIBRTE_ACL)-include := rte_pmd_ixgbe.h
>
Config flag should be CONFIG_RTE_LIBRTE_IXGBE_PMD .
Thanks,
Reshma
^ permalink raw reply
* Re: [PATCH v5 2/3] net/ixgbe: add API's for VF management
From: Reshma Pattan @ 2016-09-29 16:11 UTC (permalink / raw)
To: Bernard Iremonger, dev, rahul.r.shah, wenzhuo.lu, az5157; +Cc: azelezniak
In-Reply-To: <1475158591-2243-3-git-send-email-bernard.iremonger@intel.com>
Hi,
On 9/29/2016 3:16 PM, Bernard Iremonger wrote:
> diff --git a/drivers/net/ixgbe/Makefile b/drivers/net/ixgbe/Makefile
> index a6c71f3..7493b8d 100644
> --- a/drivers/net/ixgbe/Makefile
> +++ b/drivers/net/ixgbe/Makefile
> @@ -119,6 +119,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_bypass.c
> SRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82599_bypass.c
> endif
>
> +# install this header file
> +SYMLINK-$(CONFIG_RTE_LIBRTE_ACL)-include := rte_pmd_ixgbe.h
>
In correct config flag CONFIG_RTE_LIBRTE_ACL , should be
CONFIG_RTE_LIBRTE_IXGBE_PMD
Thanks,
Reshma
^ permalink raw reply
* [PATCH v3 9/9] doc: update ipsec-secgw sample app guide
From: Sergio Gonzalez Monroy @ 2016-09-29 15:44 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch
In-Reply-To: <1475163857-142366-1-git-send-email-sergio.gonzalez.monroy@intel.com>
Update sample guide to reflect support for new algorithms.
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
doc/guides/sample_app_ug/ipsec_secgw.rst | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/doc/guides/sample_app_ug/ipsec_secgw.rst b/doc/guides/sample_app_ug/ipsec_secgw.rst
index 5cce2fe..4f7bd7d 100644
--- a/doc/guides/sample_app_ug/ipsec_secgw.rst
+++ b/doc/guides/sample_app_ug/ipsec_secgw.rst
@@ -79,7 +79,7 @@ Constraints
* No IPv6 options headers.
* No AH mode.
-* Currently only EAS-CBC, HMAC-SHA1 and NULL.
+* Supported algorithms: EAS-CBC, AES-CTR, AES-GCM, HMAC-SHA1 and NULL.
* Each SA must be handle by a unique lcore (*1 RX queue per port*).
* No chained mbufs.
@@ -380,9 +380,6 @@ SA rule syntax
The successfully parsed SA rules will be stored in an array table.
-All SAs configured with AES-CBC and HMAC-SHA1 share the same values for
-cipher block size and key, and authentication digest size and key.
-
The SA rule syntax is shown as follows:
.. code-block:: console
@@ -421,6 +418,8 @@ where each options means:
* *null*: NULL algorithm
* *aes-128-cbc*: AES-CBC 128-bit algorithm
+ * *aes-128-ctr*: AES-CTR 128-bit algorithm
+ * *aes-128-gcm*: AES-GCM 128-bit algorithm
* Syntax: *cipher_algo <your algorithm>*
@@ -447,10 +446,12 @@ where each options means:
* *null*: NULL algorithm
* *sha1-hmac*: HMAC SHA1 algorithm
+ * *aes-128-gcm*: AES-GCM 128-bit algorithm
``<auth_key>``
- * Authentication key, NOT available when 'null' algorithm is used
+ * Authentication key, NOT available when 'null' or 'aes-128-gcm' algorithm
+ is used.
* Optional: No, must followed by <auth_algo> option
@@ -514,6 +515,10 @@ Example SA rules:
src 1111:1111:1111:1111:1111:1111:1111:5555 \
dst 2222:2222:2222:2222:2222:2222:2222:5555
+ sa in 105 cipher_algo aes-128-gcm \
+ cipher_key de:ad:be:ef:de:ad:be:ef:de:ad:be:ef:de:ad:be:ef:de:ad:be:ef \
+ auth_algo aes-128-gcm \
+ mode ipv4-tunnel src 172.16.2.5 dst 172.16.1.5
Routing rule syntax
^^^^^^^^^^^^^^^^^^^
--
2.5.5
^ permalink raw reply related
* [PATCH v3 9/9] examples/ipsec-secgw: update ipsec-secgw guide
From: Sergio Gonzalez Monroy @ 2016-09-29 15:44 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch
In-Reply-To: <1475163857-142366-1-git-send-email-sergio.gonzalez.monroy@intel.com>
Update sample guide to reflect support for new algorithms.
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
doc/guides/sample_app_ug/ipsec_secgw.rst | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/doc/guides/sample_app_ug/ipsec_secgw.rst b/doc/guides/sample_app_ug/ipsec_secgw.rst
index 5cce2fe..4f7bd7d 100644
--- a/doc/guides/sample_app_ug/ipsec_secgw.rst
+++ b/doc/guides/sample_app_ug/ipsec_secgw.rst
@@ -79,7 +79,7 @@ Constraints
* No IPv6 options headers.
* No AH mode.
-* Currently only EAS-CBC, HMAC-SHA1 and NULL.
+* Supported algorithms: EAS-CBC, AES-CTR, AES-GCM, HMAC-SHA1 and NULL.
* Each SA must be handle by a unique lcore (*1 RX queue per port*).
* No chained mbufs.
@@ -380,9 +380,6 @@ SA rule syntax
The successfully parsed SA rules will be stored in an array table.
-All SAs configured with AES-CBC and HMAC-SHA1 share the same values for
-cipher block size and key, and authentication digest size and key.
-
The SA rule syntax is shown as follows:
.. code-block:: console
@@ -421,6 +418,8 @@ where each options means:
* *null*: NULL algorithm
* *aes-128-cbc*: AES-CBC 128-bit algorithm
+ * *aes-128-ctr*: AES-CTR 128-bit algorithm
+ * *aes-128-gcm*: AES-GCM 128-bit algorithm
* Syntax: *cipher_algo <your algorithm>*
@@ -447,10 +446,12 @@ where each options means:
* *null*: NULL algorithm
* *sha1-hmac*: HMAC SHA1 algorithm
+ * *aes-128-gcm*: AES-GCM 128-bit algorithm
``<auth_key>``
- * Authentication key, NOT available when 'null' algorithm is used
+ * Authentication key, NOT available when 'null' or 'aes-128-gcm' algorithm
+ is used.
* Optional: No, must followed by <auth_algo> option
@@ -514,6 +515,10 @@ Example SA rules:
src 1111:1111:1111:1111:1111:1111:1111:5555 \
dst 2222:2222:2222:2222:2222:2222:2222:5555
+ sa in 105 cipher_algo aes-128-gcm \
+ cipher_key de:ad:be:ef:de:ad:be:ef:de:ad:be:ef:de:ad:be:ef:de:ad:be:ef \
+ auth_algo aes-128-gcm \
+ mode ipv4-tunnel src 172.16.2.5 dst 172.16.1.5
Routing rule syntax
^^^^^^^^^^^^^^^^^^^
--
2.5.5
^ permalink raw reply related
* [PATCH v3 8/9] examples/ipsec-secgw: update release notes
From: Sergio Gonzalez Monroy @ 2016-09-29 15:44 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch
In-Reply-To: <1475163857-142366-1-git-send-email-sergio.gonzalez.monroy@intel.com>
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
doc/guides/rel_notes/release_16_11.rst | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst
index cc507a9..168d589 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -59,6 +59,15 @@ New Features
ipsec-secgw sample application now supports configuration file to specify
SP, SA, and routing rules.
+* **ipsec-secgw: AES GCM/CTR mode support**
+
+ Support AES Counter (CTR) and Galois-Counter Mode (GCM) in IPSec ESP.
+
+* **ipsec-secgw: AES CBC IV generation**
+
+ Use cipher forward function on unique counter blocks (same approach as
+ CTR/GCM) to generate the IV instead of a random value.
+
Resolved Issues
---------------
--
2.5.5
^ permalink raw reply related
* [PATCH v3 8/9] doc: ipsec-secgw release notes
From: Sergio Gonzalez Monroy @ 2016-09-29 15:44 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch
In-Reply-To: <1475163857-142366-1-git-send-email-sergio.gonzalez.monroy@intel.com>
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
doc/guides/rel_notes/release_16_11.rst | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst
index cc507a9..168d589 100644
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -59,6 +59,15 @@ New Features
ipsec-secgw sample application now supports configuration file to specify
SP, SA, and routing rules.
+* **ipsec-secgw: AES GCM/CTR mode support**
+
+ Support AES Counter (CTR) and Galois-Counter Mode (GCM) in IPSec ESP.
+
+* **ipsec-secgw: AES CBC IV generation**
+
+ Use cipher forward function on unique counter blocks (same approach as
+ CTR/GCM) to generate the IV instead of a random value.
+
Resolved Issues
---------------
--
2.5.5
^ permalink raw reply related
* [PATCH v3 5/9] examples/ipsec-secgw: check sp only when setup
From: Sergio Gonzalez Monroy @ 2016-09-29 15:44 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch
In-Reply-To: <1475163857-142366-1-git-send-email-sergio.gonzalez.monroy@intel.com>
Application will segfault if there is IPv4 or IPv6 and no SP/ACL rules
for IPv4 or IPv6 respectively.
Avoid checking the ACL/SP in such cases.
Fixes: 906257e965b7 ("examples/ipsec-secgw: support IPv6")
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
examples/ipsec-secgw/ipsec-secgw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c
index 8b55534..9eee96f 100644
--- a/examples/ipsec-secgw/ipsec-secgw.c
+++ b/examples/ipsec-secgw/ipsec-secgw.c
@@ -388,7 +388,7 @@ inbound_sp_sa(struct sp_ctx *sp, struct sa_ctx *sa, struct traffic_type *ip,
struct rte_mbuf *m;
uint32_t i, j, res, sa_idx;
- if (ip->num == 0)
+ if (ip->num == 0 || sp == NULL)
return;
rte_acl_classify((struct rte_acl_ctx *)sp, ip->data, ip->res,
@@ -463,7 +463,7 @@ outbound_sp(struct sp_ctx *sp, struct traffic_type *ip,
struct rte_mbuf *m;
uint32_t i, j, sa_idx;
- if (ip->num == 0)
+ if (ip->num == 0 || sp == NULL)
return;
rte_acl_classify((struct rte_acl_ctx *)sp, ip->data, ip->res,
--
2.5.5
^ permalink raw reply related
* [PATCH v3 4/9] examples/ipsec-secgw: enable AES-CTR mode
From: Sergio Gonzalez Monroy @ 2016-09-29 15:44 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch
In-Reply-To: <1475163857-142366-1-git-send-email-sergio.gonzalez.monroy@intel.com>
RFC3686: Using AES Counter (CTR) Mode With IPsec ESP.`
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
examples/ipsec-secgw/esp.c | 2 ++
examples/ipsec-secgw/sa.c | 7 +++++++
2 files changed, 9 insertions(+)
diff --git a/examples/ipsec-secgw/esp.c b/examples/ipsec-secgw/esp.c
index 7ee53da..ec5a2e6 100644
--- a/examples/ipsec-secgw/esp.c
+++ b/examples/ipsec-secgw/esp.c
@@ -102,6 +102,7 @@ esp_inbound(struct rte_mbuf *m, struct ipsec_sa *sa,
ip_hdr_len + sizeof(struct esp_hdr));
sym_cop->cipher.iv.length = sa->iv_len;
break;
+ case RTE_CRYPTO_CIPHER_AES_CTR:
case RTE_CRYPTO_CIPHER_AES_GCM:
icb = get_cnt_blk(m);
icb->salt = sa->salt;
@@ -320,6 +321,7 @@ esp_outbound(struct rte_mbuf *m, struct ipsec_sa *sa,
sizeof(struct esp_hdr);
sym_cop->cipher.data.length = pad_payload_len + sa->iv_len;
break;
+ case RTE_CRYPTO_CIPHER_AES_CTR:
case RTE_CRYPTO_CIPHER_AES_GCM:
*iv = sa->seq;
sym_cop->cipher.data.offset = ip_hdr_len +
diff --git a/examples/ipsec-secgw/sa.c b/examples/ipsec-secgw/sa.c
index d5ad5af..00c8cce 100644
--- a/examples/ipsec-secgw/sa.c
+++ b/examples/ipsec-secgw/sa.c
@@ -88,6 +88,13 @@ const struct supported_cipher_algo cipher_algos[] = {
.iv_len = 8,
.block_size = 4,
.key_len = 16
+ },
+ {
+ .keyword = "aes-128-ctr",
+ .algo = RTE_CRYPTO_CIPHER_AES_CTR,
+ .iv_len = 8,
+ .block_size = 16, /* XXX AESNI MB limition, should be 4 */
+ .key_len = 16
}
};
--
2.5.5
^ permalink raw reply related
* [PATCH v3 3/9] examples/ipsec-secgw: add AES-GCM support
From: Sergio Gonzalez Monroy @ 2016-09-29 15:44 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch
In-Reply-To: <1475163857-142366-1-git-send-email-sergio.gonzalez.monroy@intel.com>
Add support for AES-GCM (Galois-Counter Mode).
RFC4106: The Use of Galois-Counter Mode (GCM) in IPSec ESP.
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
examples/ipsec-secgw/esp.c | 59 ++++++++++++++++++++++++++++++++++++++------
examples/ipsec-secgw/ipsec.h | 9 +++++++
examples/ipsec-secgw/sa.c | 36 +++++++++++++++++++++------
3 files changed, 90 insertions(+), 14 deletions(-)
diff --git a/examples/ipsec-secgw/esp.c b/examples/ipsec-secgw/esp.c
index 21b2f02..7ee53da 100644
--- a/examples/ipsec-secgw/esp.c
+++ b/examples/ipsec-secgw/esp.c
@@ -90,6 +90,8 @@ esp_inbound(struct rte_mbuf *m, struct ipsec_sa *sa,
sa->iv_len;
sym_cop->cipher.data.length = payload_len;
+ struct cnt_blk *icb;
+ uint8_t *aad;
uint8_t *iv = RTE_PTR_ADD(ip4, ip_hdr_len + sizeof(struct esp_hdr));
switch (sa->cipher_algo) {
@@ -99,14 +101,41 @@ esp_inbound(struct rte_mbuf *m, struct ipsec_sa *sa,
sym_cop->cipher.iv.phys_addr = rte_pktmbuf_mtophys_offset(m,
ip_hdr_len + sizeof(struct esp_hdr));
sym_cop->cipher.iv.length = sa->iv_len;
+ break;
+ case RTE_CRYPTO_CIPHER_AES_GCM:
+ icb = get_cnt_blk(m);
+ icb->salt = sa->salt;
+ memcpy(&icb->iv, iv, 8);
+ icb->cnt = rte_cpu_to_be_32(1);
+ sym_cop->cipher.iv.data = (uint8_t *)icb;
+ sym_cop->cipher.iv.phys_addr = rte_pktmbuf_mtophys_offset(m,
+ (uint8_t *)icb - rte_pktmbuf_mtod(m, uint8_t *));
+ sym_cop->cipher.iv.length = 16;
+ break;
+ default:
+ RTE_LOG(ERR, IPSEC_ESP, "unsupported cipher algorithm %u\n",
+ sa->cipher_algo);
+ return -EINVAL;
+ }
+ switch (sa->auth_algo) {
+ case RTE_CRYPTO_AUTH_NULL:
+ case RTE_CRYPTO_AUTH_SHA1_HMAC:
sym_cop->auth.data.offset = ip_hdr_len;
sym_cop->auth.data.length = sizeof(struct esp_hdr) +
sa->iv_len + payload_len;
break;
+ case RTE_CRYPTO_AUTH_AES_GCM:
+ aad = get_aad(m);
+ memcpy(aad, iv - sizeof(struct esp_hdr), 8);
+ sym_cop->auth.aad.data = aad;
+ sym_cop->auth.aad.phys_addr = rte_pktmbuf_mtophys_offset(m,
+ aad - rte_pktmbuf_mtod(m, uint8_t *));
+ sym_cop->auth.aad.length = 8;
+ break;
default:
- RTE_LOG(ERR, IPSEC_ESP, "unsupported cipher algorithm %u\n",
- sa->cipher_algo);
+ RTE_LOG(ERR, IPSEC_ESP, "unsupported auth algorithm %u\n",
+ sa->auth_algo);
return -EINVAL;
}
@@ -291,6 +320,12 @@ esp_outbound(struct rte_mbuf *m, struct ipsec_sa *sa,
sizeof(struct esp_hdr);
sym_cop->cipher.data.length = pad_payload_len + sa->iv_len;
break;
+ case RTE_CRYPTO_CIPHER_AES_GCM:
+ *iv = sa->seq;
+ sym_cop->cipher.data.offset = ip_hdr_len +
+ sizeof(struct esp_hdr) + sa->iv_len;
+ sym_cop->cipher.data.length = pad_payload_len;
+ break;
default:
RTE_LOG(ERR, IPSEC_ESP, "unsupported cipher algorithm %u\n",
sa->cipher_algo);
@@ -312,16 +347,26 @@ esp_outbound(struct rte_mbuf *m, struct ipsec_sa *sa,
(uint8_t *)icb - rte_pktmbuf_mtod(m, uint8_t *));
sym_cop->cipher.iv.length = 16;
- switch (sa->cipher_algo) {
- case RTE_CRYPTO_CIPHER_NULL:
- case RTE_CRYPTO_CIPHER_AES_CBC:
+ uint8_t *aad;
+
+ switch (sa->auth_algo) {
+ case RTE_CRYPTO_AUTH_NULL:
+ case RTE_CRYPTO_AUTH_SHA1_HMAC:
sym_cop->auth.data.offset = ip_hdr_len;
sym_cop->auth.data.length = sizeof(struct esp_hdr) +
sa->iv_len + pad_payload_len;
break;
+ case RTE_CRYPTO_AUTH_AES_GCM:
+ aad = get_aad(m);
+ memcpy(aad, esp, 8);
+ sym_cop->auth.aad.data = aad;
+ sym_cop->auth.aad.phys_addr = rte_pktmbuf_mtophys_offset(m,
+ aad - rte_pktmbuf_mtod(m, uint8_t *));
+ sym_cop->auth.aad.length = 8;
+ break;
default:
- RTE_LOG(ERR, IPSEC_ESP, "unsupported cipher algorithm %u\n",
- sa->cipher_algo);
+ RTE_LOG(ERR, IPSEC_ESP, "unsupported auth algorithm %u\n",
+ sa->auth_algo);
return -EINVAL;
}
diff --git a/examples/ipsec-secgw/ipsec.h b/examples/ipsec-secgw/ipsec.h
index ad96782..dbc8c2c 100644
--- a/examples/ipsec-secgw/ipsec.h
+++ b/examples/ipsec-secgw/ipsec.h
@@ -113,6 +113,7 @@ struct ipsec_sa {
uint16_t cipher_key_len;
uint8_t auth_key[MAX_KEY_SIZE];
uint16_t auth_key_len;
+ uint16_t aad_len;
struct rte_crypto_sym_xform *xforms;
} __rte_cache_aligned;
@@ -194,6 +195,14 @@ get_cnt_blk(struct rte_mbuf *m)
}
static inline void *
+get_aad(struct rte_mbuf *m)
+{
+ struct ipsec_mbuf_metadata *priv = get_priv(m);
+
+ return &priv->buf[16];
+}
+
+static inline void *
get_sym_cop(struct rte_crypto_op *cop)
{
return (cop + 1);
diff --git a/examples/ipsec-secgw/sa.c b/examples/ipsec-secgw/sa.c
index ee88802..d5ad5af 100644
--- a/examples/ipsec-secgw/sa.c
+++ b/examples/ipsec-secgw/sa.c
@@ -63,6 +63,8 @@ struct supported_auth_algo {
enum rte_crypto_auth_algorithm algo;
uint16_t digest_len;
uint16_t key_len;
+ uint8_t aad_len;
+ uint8_t key_not_req;
};
const struct supported_cipher_algo cipher_algos[] = {
@@ -79,6 +81,13 @@ const struct supported_cipher_algo cipher_algos[] = {
.iv_len = 16,
.block_size = 16,
.key_len = 16
+ },
+ {
+ .keyword = "aes-128-gcm",
+ .algo = RTE_CRYPTO_CIPHER_AES_GCM,
+ .iv_len = 8,
+ .block_size = 4,
+ .key_len = 16
}
};
@@ -87,13 +96,22 @@ const struct supported_auth_algo auth_algos[] = {
.keyword = "null",
.algo = RTE_CRYPTO_AUTH_NULL,
.digest_len = 0,
- .key_len = 0
+ .key_len = 0,
+ .key_not_req = 1
},
{
.keyword = "sha1-hmac",
.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
.digest_len = 12,
.key_len = 20
+ },
+ {
+ .keyword = "aes-128-gcm",
+ .algo = RTE_CRYPTO_AUTH_AES_GCM,
+ .digest_len = 16,
+ .key_len = 16,
+ .aad_len = 8,
+ .key_not_req = 1
}
};
@@ -255,8 +273,7 @@ parse_sa_tokens(char **tokens, uint32_t n_tokens,
rule->iv_len = algo->iv_len;
rule->cipher_key_len = algo->key_len;
- /* for NULL algorithm, no cipher key should
- * exist */
+ /* for NULL algorithm, no cipher key required */
if (rule->cipher_algo == RTE_CRYPTO_CIPHER_NULL) {
cipher_algo_p = 1;
continue;
@@ -307,9 +324,12 @@ parse_sa_tokens(char **tokens, uint32_t n_tokens,
rule->auth_algo = algo->algo;
rule->auth_key_len = algo->key_len;
rule->digest_len = algo->digest_len;
+ rule->aad_len = algo->key_len;
- /* for NULL algorithm, no auth key should exist */
- if (rule->auth_algo == RTE_CRYPTO_AUTH_NULL) {
+ /* NULL algorithm and combined algos do not
+ * require auth key
+ */
+ if (algo->key_not_req) {
auth_algo_p = 1;
continue;
}
@@ -572,7 +592,8 @@ sa_add_rules(struct sa_ctx *sa_ctx, const struct ipsec_sa entries[],
sa_ctx->xf[idx].a.type = RTE_CRYPTO_SYM_XFORM_AUTH;
sa_ctx->xf[idx].a.auth.algo = sa->auth_algo;
- sa_ctx->xf[idx].a.auth.add_auth_data_length = 0;
+ sa_ctx->xf[idx].a.auth.add_auth_data_length =
+ sa->aad_len;
sa_ctx->xf[idx].a.auth.key.data = sa->auth_key;
sa_ctx->xf[idx].a.auth.key.length =
sa->auth_key_len;
@@ -593,7 +614,8 @@ sa_add_rules(struct sa_ctx *sa_ctx, const struct ipsec_sa entries[],
sa_ctx->xf[idx].b.type = RTE_CRYPTO_SYM_XFORM_AUTH;
sa_ctx->xf[idx].b.auth.algo = sa->auth_algo;
- sa_ctx->xf[idx].b.auth.add_auth_data_length = 0;
+ sa_ctx->xf[idx].b.auth.add_auth_data_length =
+ sa->aad_len;
sa_ctx->xf[idx].b.auth.key.data = sa->auth_key;
sa_ctx->xf[idx].b.auth.key.length =
sa->auth_key_len;
--
2.5.5
^ permalink raw reply related
* [PATCH v3 6/9] examples/ipsec-secgw: add cryptodev queue size macro
From: Sergio Gonzalez Monroy @ 2016-09-29 15:44 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch
In-Reply-To: <1475163857-142366-1-git-send-email-sergio.gonzalez.monroy@intel.com>
Introduce a specific cryptodev queue size macro.
Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
---
examples/ipsec-secgw/ipsec-secgw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c
index 9eee96f..5a4c9b7 100644
--- a/examples/ipsec-secgw/ipsec-secgw.c
+++ b/examples/ipsec-secgw/ipsec-secgw.c
@@ -82,6 +82,7 @@
#define NB_MBUF (32000)
+#define CDEV_QUEUE_DESC 2048
#define CDEV_MAP_ENTRIES 1024
#define CDEV_MP_NB_OBJS 2048
#define CDEV_MP_CACHE_SZ 64
@@ -1272,7 +1273,7 @@ cryptodevs_init(void)
rte_panic("Failed to initialize crypodev %u\n",
cdev_id);
- qp_conf.nb_descriptors = CDEV_MP_NB_OBJS;
+ qp_conf.nb_descriptors = CDEV_QUEUE_DESC;
for (qp = 0; qp < dev_conf.nb_queue_pairs; qp++)
if (rte_cryptodev_queue_pair_setup(cdev_id, qp,
&qp_conf, dev_conf.socket_id))
--
2.5.5
^ permalink raw reply related
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