* [PATCH v2] nfp: report link speed using hardware info
From: Alejandro Lucero @ 2016-11-18 16:06 UTC (permalink / raw)
To: dev
Previous reported speed was hardcoded.
Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
---
drivers/net/nfp/nfp_net.c | 28 ++++++++++++++++++++++++++--
drivers/net/nfp/nfp_net_ctrl.h | 13 +++++++++++++
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/drivers/net/nfp/nfp_net.c b/drivers/net/nfp/nfp_net.c
index c6b1587..24f3164 100644
--- a/drivers/net/nfp/nfp_net.c
+++ b/drivers/net/nfp/nfp_net.c
@@ -816,6 +816,17 @@ static void nfp_net_read_mac(struct nfp_net_hw *hw)
struct rte_eth_link link, old;
uint32_t nn_link_status;
+ static const uint32_t ls_to_ethtool[] = {
+ [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
+ [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
+ [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
+ [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
+ [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
+ [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
+ [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
+ [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
+ };
+
PMD_DRV_LOG(DEBUG, "Link update\n");
hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
@@ -831,8 +842,21 @@ static void nfp_net_read_mac(struct nfp_net_hw *hw)
link.link_status = ETH_LINK_UP;
link.link_duplex = ETH_LINK_FULL_DUPLEX;
- /* Other cards can limit the tx and rx rate per VF */
- link.link_speed = ETH_SPEED_NUM_40G;
+
+ nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
+ NFP_NET_CFG_STS_LINK_RATE_MASK;
+
+ if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
+ ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
+ (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
+ link.link_speed = ETH_SPEED_NUM_40G;
+ else {
+ if (nn_link_status == NFP_NET_CFG_STS_LINK_RATE_UNKNOWN ||
+ nn_link_status >= RTE_DIM(ls_to_ethtool))
+ link.link_speed = ETH_SPEED_NUM_NONE;
+ else
+ link.link_speed = ls_to_ethtool[nn_link_status];
+ }
if (old.link_status != link.link_status) {
nfp_net_dev_atomic_write_link_status(dev, &link);
diff --git a/drivers/net/nfp/nfp_net_ctrl.h b/drivers/net/nfp/nfp_net_ctrl.h
index fce8251..f9aaba3 100644
--- a/drivers/net/nfp/nfp_net_ctrl.h
+++ b/drivers/net/nfp/nfp_net_ctrl.h
@@ -157,6 +157,19 @@
#define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0)
#define NFP_NET_CFG_STS 0x0034
#define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */
+/* Link rate */
+#define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
+#define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF
+#define NFP_NET_CFG_STS_LINK_RATE \
+ (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT)
+#define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0
+#define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1
+#define NFP_NET_CFG_STS_LINK_RATE_1G 2
+#define NFP_NET_CFG_STS_LINK_RATE_10G 3
+#define NFP_NET_CFG_STS_LINK_RATE_25G 4
+#define NFP_NET_CFG_STS_LINK_RATE_40G 5
+#define NFP_NET_CFG_STS_LINK_RATE_50G 6
+#define NFP_NET_CFG_STS_LINK_RATE_100G 7
#define NFP_NET_CFG_CAP 0x0038
#define NFP_NET_CFG_MAX_TXRINGS 0x003c
#define NFP_NET_CFG_MAX_RXRINGS 0x0040
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v2] nfp: report link speed using hardware info
From: Thomas Monjalon @ 2016-11-18 16:29 UTC (permalink / raw)
To: Alejandro Lucero; +Cc: dev
In-Reply-To: <1479485218-11931-1-git-send-email-alejandro.lucero@netronome.com>
2016-11-18 16:06, Alejandro Lucero:
> Previous reported speed was hardcoded.
>
> Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
> ---
> drivers/net/nfp/nfp_net.c | 28 ++++++++++++++++++++++++++--
> drivers/net/nfp/nfp_net_ctrl.h | 13 +++++++++++++
> 2 files changed, 39 insertions(+), 2 deletions(-)
You should update the doc in the same patch:
doc/guides/nics/features/nfp.ini
It will be the first feature as the file appears to be empty.
So you will need another patch to fill other existing features.
I have an unrelated question: why nfp is disabled in the default build?
^ permalink raw reply
* [PATCH] vdev: fix missing alias check on uninit
From: Anatoly Burakov @ 2016-11-18 16:32 UTC (permalink / raw)
To: dev
Fixes: d63eed6b2dca ("eal: add driver name alias")
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
lib/librte_eal/common/eal_common_vdev.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/lib/librte_eal/common/eal_common_vdev.c b/lib/librte_eal/common/eal_common_vdev.c
index 0ff2377..7d6e54f 100644
--- a/lib/librte_eal/common/eal_common_vdev.c
+++ b/lib/librte_eal/common/eal_common_vdev.c
@@ -111,6 +111,14 @@ rte_eal_vdev_uninit(const char *name)
return driver->remove(name);
}
+ /* Give new names precedence over aliases. */
+ TAILQ_FOREACH(driver, &vdev_driver_list, next) {
+ if (driver->driver.alias &&
+ !strncmp(driver->driver.alias, name,
+ strlen(driver->driver.alias)))
+ return driver->remove(name);
+ }
+
RTE_LOG(ERR, EAL, "no driver found for %s\n", name);
return -EINVAL;
}
--
2.5.5
^ permalink raw reply related
* Re: pmdinfogen issues: cross compilation for ARM fails with older host compiler
From: Bruce Richardson @ 2016-11-18 16:37 UTC (permalink / raw)
To: Neil Horman
Cc: Hemant Agrawal, Jerin Jacob, dev@dpdk.org, users@dpdk.org,
Jacob, Jerin, Jan Viktorin
In-Reply-To: <20161118135052.GA29049@hmsreliant.think-freely.org>
On Fri, Nov 18, 2016 at 08:50:52AM -0500, Neil Horman wrote:
> On Fri, Nov 18, 2016 at 12:03:19PM +0000, Hemant Agrawal wrote:
> > > -----Original Message-----
> > > From: Neil Horman [mailto:nhorman@tuxdriver.com]
> > > On Tue, Nov 15, 2016 at 09:34:16AM +0000, Hemant Agrawal wrote:
> > > > > On Mon, Nov 14, 2016 at 02:29:24AM +0530, Jerin Jacob wrote:
> > > > > > On Fri, Nov 11, 2016 at 10:34:39AM +0000, Hemant Agrawal wrote:
> > > > > > > Hi Neil,
> > > > > > > Pmdinfogen compiles with host compiler. It usages
> > > rte_byteorder.h
> > > > > of the target platform.
> > > > > > > However, if the host compiler is older than 4.8, it will be an issue during
> > > cross
> > > > > compilation for some platforms.
> > > > > > > e.g. if we are compiling on x86 host for ARM, x86 host compiler will not
> > > > > understand the arm asm instructions.
> > > > > > >
> > > > > > > /* fix missing __builtin_bswap16 for gcc older then 4.8 */ #if
> > > > > > > !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)) static
> > > > > > > inline uint16_t rte_arch_bswap16(uint16_t _x) {
> > > > > > > register uint16_t x = _x;
> > > > > > > asm volatile ("rev16 %0,%1"
> > > > > > > : "=r" (x)
> > > > > > > : "r" (x)
> > > > > > > );
> > > > > > > return x;
> > > > > > > }
> > > > > > > #endif
> > > > > > >
> > > > > > > One easy solution is that we add compiler platform check in this
> > > > > > > code section of rte_byteorder.h e.g #if !(defined __arm__ || defined
> > > > > > > __aarch64__) static inline uint16_t rte_arch_bswap16(uint16_t _x) {
> > > > > > > return (_x >> 8) | ((_x << 8) & 0xff00); } #else ….
> > > > > > >
> > > > > > > Is there a better way to fix it?
> > > > > >
> > > > > > IMO, It is a HOST build infrastructure issue. If a host app is using
> > > > > > the dpdk service then it should compile and link against HOST
> > > > > > target(in this specific case, build/x86_64-native-linuxapp-gcc). I
> > > > > > think, introducing the HOSTTARGET kind of scheme is a clean solution.
> > > > > >
> > > > > > /Jerin
> > > > > >
> > > > > >
> > > > > That would be accurate. That is to say, pmdinfogen is a tool that should only
> > > be
> > > > > run on the host doing the build, by the host doing the build, and so should be
> > > > > compiled to run on the host, not on the target being built for.
> > > > >
> > > > > Yeah, so what we need is a way to get to the host version of rte_byteorder.h
> > > > > when building in a cross environment
> > > > >
> > > > +1
> > > >
> > > > > Neil
> > > >
> > >
> > > Give this a try, I've tested it on linux, but not BSD. From what I read the
> > > functions are not posix compliant, though they should exist on all BSD and Linux
> > > systems in recent history. There may be some fiddling needed for Net and
> > > OpenBSD variants, but I think this is the right general direction.
> >
> > + 1
> > This patch works good for Linux.
> >
> Can someone test it on BSD? I'd like to ensure we don't need to modify it for
> that platform
>
> Neil
>
> > >
> > >
> > > diff --git a/buildtools/pmdinfogen/pmdinfogen.h
> > > b/buildtools/pmdinfogen/pmdinfogen.h
> > > index 1da2966..c5ef89d 100644
> > > --- a/buildtools/pmdinfogen/pmdinfogen.h
> > > +++ b/buildtools/pmdinfogen/pmdinfogen.h
> > > @@ -21,7 +21,6 @@
> > > #include <elf.h>
> > > #include <rte_config.h>
> > > #include <rte_pci.h>
> > > -#include <rte_byteorder.h>
> > >
> > > /* On BSD-alike OSes elf.h defines these according to host's word size */
> > > #undef ELF_ST_BIND
> > > @@ -75,9 +74,9 @@
> > > #define CONVERT_NATIVE(fend, width, x) ({ \
> > > typeof(x) ___x; \
> > > if ((fend) == ELFDATA2LSB) \
> > > - ___x = rte_le_to_cpu_##width(x); \
> > > + ___x = le##width##toh(x); \
> > > else \
> > > - ___x = rte_be_to_cpu_##width(x); \
> > > + ___x = be##width##toh(x); \
> > > ___x; \
> > > })
> > >
For compile on FreeBSD 10 we need "#include <sys/endian.h>" and this
works.
/Bruce
^ permalink raw reply
* Re: [PATCH v2 1/1] mempool: Add sanity check when secondary link in less mempools than primary
From: Jean Tourrilhes @ 2016-11-18 16:39 UTC (permalink / raw)
To: Olivier Matz, dev; +Cc: Thomas Monjalon, David Marchand, Sergio Gonzalez Monroy
In-Reply-To: <e451c41b-6773-975e-9145-2f386237ab49@6wind.com>
On Fri, Nov 18, 2016 at 04:11:12PM +0100, Olivier Matz wrote:
> Hi Jean,
>
>
> Do you mind if we put back this conversation on the ML?
Oh, I forgot to do it ? I intended to. Bummer. Please do so.
> I think your example shows that there is no linker magic: you just
> need the same linker flags for dpdk libraries than in the dpdk
> framework. I suppose we need something in the build framework
> to provide these flags externally,
Good luck integrating that in all foreign build system (I'm
looking at you, Snort).
> but I don't think we need to patch mempool for that.
This sanity check is just that, a sanity check. I don't
understand what's bad about a sanity check, it does not change
functionality, it does not fix anything and just warn users about
those issues.
Please look at the patch itself at face value.
> Regards,
> Olivier
Regards,
Jean
^ permalink raw reply
* Re: [PATCH v2] nfp: report link speed using hardware info
From: Alejandro Lucero @ 2016-11-18 16:50 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: dev
In-Reply-To: <1901770.8floaBijqc@xps13>
On Fri, Nov 18, 2016 at 4:29 PM, Thomas Monjalon <thomas.monjalon@6wind.com>
wrote:
> 2016-11-18 16:06, Alejandro Lucero:
> > Previous reported speed was hardcoded.
> >
> > Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
> > ---
> > drivers/net/nfp/nfp_net.c | 28 ++++++++++++++++++++++++++--
> > drivers/net/nfp/nfp_net_ctrl.h | 13 +++++++++++++
> > 2 files changed, 39 insertions(+), 2 deletions(-)
>
> You should update the doc in the same patch:
> doc/guides/nics/features/nfp.ini
> It will be the first feature as the file appears to be empty.
> So you will need another patch to fill other existing features.
>
Yes. I'm just working on updating that file properly.
May I delay this doc change for including it with that other one?
It will be a bit weird to just have one feature there.
>
> I have an unrelated question: why nfp is disabled in the default build?
>
>
Because NFP PMD can just work if Netronome BSP is installed in the system.
We do not support PF with the PMD, so it requires a Linux PF driver which
comes with the BSP.
The compilation has no dependencies, but we had our own UIO driver before
(now using igb_uio). So basically, we wanted the people aware of this
dependency and to specifically configure this option.
I know what you are surely going to ask about DPDK in Linux distributions,
and that this being a bad idea. The fact is, we have people using NFP PMD
as part of a product, so installing that product implies to (automatically)
install the BSP and a specific DPDK version with the NFP PMD enabled. But
yes, maybe we should modify this and to add some sort of BSP check inside
the PMD.
So, thanks for the heads up. I will think about this.
^ permalink raw reply
* Re: Solarflare PMD submission question
From: Andrew Rybchenko @ 2016-11-18 16:50 UTC (permalink / raw)
To: Thomas Monjalon; +Cc: dev
In-Reply-To: <b0978fcf-1bb1-d454-cc72-364c4b7aa9b0@solarflare.com>
On 10/28/2016 05:43 PM, Andrew Rybchenko wrote:
> On 10/28/2016 03:33 PM, Thomas Monjalon wrote:
>> 2016-10-28 13:50, Andrew Rybchenko:
>>> The only thing which comes to my mind is to split libefx import on
>>> subsystem
>>> basis (few files per subsystem). It is artificial and added files will
>>> be abandoned
>>> until the patch which adds them into build. It could be something like:
>>> 1. External interfaces definition
>>> 2. Internal interfaces definition
>>> 3. Registers definition (hardware interface)
>>> 4. Management CPU interface definition (it is one file, but still
>>> big
>>> 650K)
>>> 5. Management CPU interface implementation
>>> and so on for NIC global controls, interrupts, event queue, transmit,
>>> receive,
>>> filtering etc.
>> Yes it is artificial.
>> The most valuable would be a transversal logical split, kind of feature
>> per feature, in order to explain how the device works.
>
> I'm not the main author of the libefx and personally would consider it
> very useful.
> From the other hand I understand that it is a huge amount of work to
> make it.
>
>> Such commit is also the opportunity to explain acronyms and so on.
>
> Good. We'll go this way and 'll do my best to make it useful to
> understand
> overall structure of the code and how the device works.
Now we have a split of the base driver import in big feature steps. The
base driver is split into 28 patches. Just only 1 patch exceeds 300K
boundary (which add MCDI definitions header).
Before submitting 56 patches I'd like to double-check that checkpatch.pl
errors (for example, because of assignments in the 'if' condition,
parenthesis around return value) is not a show-stopper for base driver
import.
Andrew.
^ permalink raw reply
* [PATCH v1] maintainers: update procinfo maintainer
From: John McNamara @ 2016-11-18 17:09 UTC (permalink / raw)
To: dev; +Cc: John McNamara
Update procinfo maintainer and name of the application.
Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d6bb8f8..c40e9e0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -618,9 +618,9 @@ M: Pablo de Lara <pablo.de.lara.guarch@intel.com>
F: app/test-pmd/
F: doc/guides/testpmd_app_ug/
-Dump tool
+Procinfo tool
M: Maryam Tahhan <maryam.tahhan@intel.com>
-M: John McNamara <john.mcnamara@intel.com>
+M: Reshma Pattan <reshma.pattan@intel.com>
F: app/proc_info/
F: doc/guides/tools/proc_info.rst
--
2.7.4
^ permalink raw reply related
* [PATCH v1] maintainers: update lthreads maintainer
From: John McNamara @ 2016-11-18 17:09 UTC (permalink / raw)
To: dev; +Cc: John McNamara
Signed-off-by: John McNamara <john.mcnamara@intel.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d6bb8f8..2744212 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -677,7 +677,7 @@ F: examples/netmap_compat/
F: doc/guides/sample_app_ug/netmap_compatibility.rst
L-threads - EXPERIMENTAL
-M: Ian Betts <ian.betts@intel.com>
+M: John McNamara <john.mcnamara@intel.com>
F: examples/performance-thread/
F: doc/guides/sample_app_ug/performance_thread.rst
--
2.7.4
^ permalink raw reply related
* Re: Proposal for a new Committer model
From: Neil Horman @ 2016-11-18 18:09 UTC (permalink / raw)
To: Mcnamara, John; +Cc: dev
In-Reply-To: <B27915DBBA3421428155699D51E4CFE202661F22@IRSMSX103.ger.corp.intel.com>
On Thu, Nov 17, 2016 at 09:20:50AM +0000, Mcnamara, John wrote:
> Repost from the moving at dpdk.org mailing list to get a wider audience.
> Original thread: http://dpdk.org/ml/archives/moving/2016-November/000059.html
>
>
> Hi,
>
> I'd like to propose a change to the DPDK committer model. Currently we have one committer for the master branch of the DPDK project.
>
> One committer to master represents a single point of failure and at times can be inefficient. There is also no agreed cover for times when the committer is unavailable such as vacation, public holidays, etc. I propose that we change to a multi-committer model for the DPDK project. We should have three committers for each release that can commit changes to the master branch.
>
> There are a number of benefits:
>
> 1. Greater capacity to commit patches.
> 2. No single points of failure - a committer should always be available if we have three.
> 3. A more timely committing of patches. More committers should equal a faster turnaround - ideally, maintainers should also provide feedback on patches submitted within a 2-3 day period, as much as possible, to facilitate this.
> 4. It follows best practice in creating a successful multi-vendor community - to achieve this we must ensure there is a level playing field for all participants, no single person should be required to make all of the decisions on patches to be included in the release.
>
> Having multiple committers will require some degree of co-ordination but there are a number of other communities successfully following this model such as Apache, OVS, FD.io, OpenStack etc. so the approach is workable.
>
> John
I agree that the problems you are attempting to address exist and are
worth finding a solution for. That said, I don't think the solution you
are proposing is the ideal, or complete fix for any of the issues being
addressed.
If I may, I'd like to ennumerate the issues I think you are trying to
address based on your comments above, then make a counter-proposal for a
solution:
Problems to address:
1) high-availability - There is a desire to make sure that, when patches
are proposed, they are integrated in a timely fashion.
2) high-throughput - DPDK has a large volume of patches, more than one
person can normally integrate. There is a desire to shard that work such
that it is handled by multiple individuals
3) Multi-Vendor fairness - There is a desire for multiple vendors to feel
as though the project tree maintainer isn't biased toward any individual
vendor.
To solve these I would propose the following solution (which is simmilar
to, but not quite identical, to yours).
A) Further promote subtree maintainership. This was a conversation that I
proposed some time ago, but my proposed granularity was discarded in favor
of something that hasn't worked as well (in my opinion). That is to say a
few driver pmds (i40e and fm10k come to mind) have their own tree that
send pull requests to Thomas. We should be sharding that at a much higher
granularity and using it much more consistently. That is to say, that we
should have a maintainer for all the ethernet pmds, and another for the
crypto pmds, another for the core eal layer, another for misc libraries
that have low patch volumes, etc. Each of those subdivisions should have
their own list to communicate on, and each should have a tree that
integrates patches for their own subsystem, and they should on a regular
cycle send pull requests to Thomas. Thomas in turn should by and large,
only be integrating pull requests. This should address our high-
throughput issue, in that it will allow multiple maintainers to share the
workload, and integration should be relatively easy.
B) Designate alternates to serve as backups for the maintainer when they
are unavailable. This provides high-availablility, and sounds very much
like your proposal, but in the interests of clarity, there is still a
single maintainer at any one time, it just may change to ensure the
continued merging of patches, if the primary maintainer isn't available.
Ideally however, those backup alternates arent needed, because most of the
primary maintainers work in merging pull requests, which are done based on
the trust of the submaintainer, and done during a very limited window of
time. This also partially addreses multi-vendor fairness if your subtree
maintainers come from multiple participating companies.
Regards
Neil
^ permalink raw reply
* Re: [PATCH] crypto: remove unused digest-appended feature
From: John Griffin @ 2016-11-18 18:15 UTC (permalink / raw)
To: Fiona Trahe, dev
Cc: pablo.de.lara.guarch, michalx.k.jastrzebski, arkadiuszx.kusztal
In-Reply-To: <1479403997-15437-2-git-send-email-fiona.trahe@intel.com>
On 17/11/16 17:33, Fiona Trahe wrote:
> The cryptodev API had specified that if the digest address field was
> left empty on an authentication operation, then the PMD would assume
> the digest was appended to the source or destination data.
> This case was not handled at all by most PMDs and incorrectly handled
> by the QAT PMD.
> As no bugs were raised, it is assumed to be not needed, so this patch
> removes it, rather than add handling for the case on all PMDs.
> The digest can still be appended to the data, but its
> address must now be provided in the op.
>
> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> ---
> drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 2 ++
> drivers/crypto/qat/qat_crypto.c | 18 +-----------------
> lib/librte_cryptodev/rte_crypto_sym.h | 10 +---------
> 3 files changed, 4 insertions(+), 26 deletions(-)
>
Acked-by: John Griffin <john.griffin@intel.com>
^ permalink raw reply
* Re: pmdinfogen issues: cross compilation for ARM fails with older host compiler
From: Neil Horman @ 2016-11-18 18:39 UTC (permalink / raw)
To: Bruce Richardson
Cc: Hemant Agrawal, Jerin Jacob, dev@dpdk.org, users@dpdk.org,
Jacob, Jerin, Jan Viktorin
In-Reply-To: <20161118163737.GA11072@bricha3-MOBL3.ger.corp.intel.com>
On Fri, Nov 18, 2016 at 04:37:38PM +0000, Bruce Richardson wrote:
> On Fri, Nov 18, 2016 at 08:50:52AM -0500, Neil Horman wrote:
> > On Fri, Nov 18, 2016 at 12:03:19PM +0000, Hemant Agrawal wrote:
> > > > -----Original Message-----
> > > > From: Neil Horman [mailto:nhorman@tuxdriver.com]
> > > > On Tue, Nov 15, 2016 at 09:34:16AM +0000, Hemant Agrawal wrote:
> > > > > > On Mon, Nov 14, 2016 at 02:29:24AM +0530, Jerin Jacob wrote:
> > > > > > > On Fri, Nov 11, 2016 at 10:34:39AM +0000, Hemant Agrawal wrote:
> > > > > > > > Hi Neil,
> > > > > > > > Pmdinfogen compiles with host compiler. It usages
> > > > rte_byteorder.h
> > > > > > of the target platform.
> > > > > > > > However, if the host compiler is older than 4.8, it will be an issue during
> > > > cross
> > > > > > compilation for some platforms.
> > > > > > > > e.g. if we are compiling on x86 host for ARM, x86 host compiler will not
> > > > > > understand the arm asm instructions.
> > > > > > > >
> > > > > > > > /* fix missing __builtin_bswap16 for gcc older then 4.8 */ #if
> > > > > > > > !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)) static
> > > > > > > > inline uint16_t rte_arch_bswap16(uint16_t _x) {
> > > > > > > > register uint16_t x = _x;
> > > > > > > > asm volatile ("rev16 %0,%1"
> > > > > > > > : "=r" (x)
> > > > > > > > : "r" (x)
> > > > > > > > );
> > > > > > > > return x;
> > > > > > > > }
> > > > > > > > #endif
> > > > > > > >
> > > > > > > > One easy solution is that we add compiler platform check in this
> > > > > > > > code section of rte_byteorder.h e.g #if !(defined __arm__ || defined
> > > > > > > > __aarch64__) static inline uint16_t rte_arch_bswap16(uint16_t _x) {
> > > > > > > > return (_x >> 8) | ((_x << 8) & 0xff00); } #else ….
> > > > > > > >
> > > > > > > > Is there a better way to fix it?
> > > > > > >
> > > > > > > IMO, It is a HOST build infrastructure issue. If a host app is using
> > > > > > > the dpdk service then it should compile and link against HOST
> > > > > > > target(in this specific case, build/x86_64-native-linuxapp-gcc). I
> > > > > > > think, introducing the HOSTTARGET kind of scheme is a clean solution.
> > > > > > >
> > > > > > > /Jerin
> > > > > > >
> > > > > > >
> > > > > > That would be accurate. That is to say, pmdinfogen is a tool that should only
> > > > be
> > > > > > run on the host doing the build, by the host doing the build, and so should be
> > > > > > compiled to run on the host, not on the target being built for.
> > > > > >
> > > > > > Yeah, so what we need is a way to get to the host version of rte_byteorder.h
> > > > > > when building in a cross environment
> > > > > >
> > > > > +1
> > > > >
> > > > > > Neil
> > > > >
> > > >
> > > > Give this a try, I've tested it on linux, but not BSD. From what I read the
> > > > functions are not posix compliant, though they should exist on all BSD and Linux
> > > > systems in recent history. There may be some fiddling needed for Net and
> > > > OpenBSD variants, but I think this is the right general direction.
> > >
> > > + 1
> > > This patch works good for Linux.
> > >
> > Can someone test it on BSD? I'd like to ensure we don't need to modify it for
> > that platform
> >
> > Neil
> >
> > > >
> > > >
> > > > diff --git a/buildtools/pmdinfogen/pmdinfogen.h
> > > > b/buildtools/pmdinfogen/pmdinfogen.h
> > > > index 1da2966..c5ef89d 100644
> > > > --- a/buildtools/pmdinfogen/pmdinfogen.h
> > > > +++ b/buildtools/pmdinfogen/pmdinfogen.h
> > > > @@ -21,7 +21,6 @@
> > > > #include <elf.h>
> > > > #include <rte_config.h>
> > > > #include <rte_pci.h>
> > > > -#include <rte_byteorder.h>
> > > >
> > > > /* On BSD-alike OSes elf.h defines these according to host's word size */
> > > > #undef ELF_ST_BIND
> > > > @@ -75,9 +74,9 @@
> > > > #define CONVERT_NATIVE(fend, width, x) ({ \
> > > > typeof(x) ___x; \
> > > > if ((fend) == ELFDATA2LSB) \
> > > > - ___x = rte_le_to_cpu_##width(x); \
> > > > + ___x = le##width##toh(x); \
> > > > else \
> > > > - ___x = rte_be_to_cpu_##width(x); \
> > > > + ___x = be##width##toh(x); \
> > > > ___x; \
> > > > })
> > > >
>
> For compile on FreeBSD 10 we need "#include <sys/endian.h>" and this
> works.
>
Yeah, but that will break linux, because there endian.h is in the base include
directory. I'll have to do some ifdeffing
Neil
> /Bruce
>
^ permalink raw reply
* [PATCH] pmdinfogen: Fix pmdinfogen to select proper endianess on cross-compile
From: Neil Horman @ 2016-11-18 18:47 UTC (permalink / raw)
To: dev
Cc: Neil Horman, Hemant Agrawal, Jerin Jacob, Bruce Richardson,
Thomas Monjalon
pmdinfogen has a bug in which, during build, it pulls in rte_byteorder.h to
obtain the rte macros for byteswapping between the cpu byte order and big or
little endian. Unfortunately, pmdinfogen is a tool that is only meant to be run
during the build of dpdk components, and so, it runs on the host. In cross
compile environments however, the rte_byteorder.h is configured using a target
cpu, who's endianess may differ from that of the host, leading to improper
swapping.
The fix is to use host system defined byte swapping routines rather than the
dpdk provided routines. Note that we are using non posix compliant routines, as
the posix compliant api only addresses 16 and 32 bit swaps, and we also need 64
bit swaps. Those macros exist (via endian.h), but BSD and Linux put that header
in different locations so some ifdeffery is required.
Tested successfully by myself on Linux and BSD systems.
Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
CC: Hemant Agrawal <hemant.agrawal@nxp.com>
CC: Jerin Jacob <Jerin.Jacob@cavium.com>
CC: Bruce Richardson <bruce.richardson@intel.com>
CC: Thomas Monjalon <thomas.monjalon@6wind.com>
---
buildtools/pmdinfogen/pmdinfogen.h | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/buildtools/pmdinfogen/pmdinfogen.h b/buildtools/pmdinfogen/pmdinfogen.h
index 1da2966..7c787c1 100644
--- a/buildtools/pmdinfogen/pmdinfogen.h
+++ b/buildtools/pmdinfogen/pmdinfogen.h
@@ -16,12 +16,16 @@
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
+#ifdef __linux__
+#include <endian.h>
+#else
+#include <sys/endian.h>
+#endif
#include <fcntl.h>
#include <unistd.h>
#include <elf.h>
#include <rte_config.h>
#include <rte_pci.h>
-#include <rte_byteorder.h>
/* On BSD-alike OSes elf.h defines these according to host's word size */
#undef ELF_ST_BIND
@@ -75,9 +79,9 @@
#define CONVERT_NATIVE(fend, width, x) ({ \
typeof(x) ___x; \
if ((fend) == ELFDATA2LSB) \
- ___x = rte_le_to_cpu_##width(x); \
+ ___x = le##width##toh(x); \
else \
- ___x = rte_be_to_cpu_##width(x); \
+ ___x = be##width##toh(x); \
___x; \
})
--
2.7.4
^ permalink raw reply related
* Re: Proposal for a new Committer model
From: Jerin Jacob @ 2016-11-18 19:06 UTC (permalink / raw)
To: Neil Horman; +Cc: Mcnamara, John, dev
In-Reply-To: <20161118161025.GC29049@hmsreliant.think-freely.org>
On Fri, Nov 18, 2016 at 01:09:35PM -0500, Neil Horman wrote:
> On Thu, Nov 17, 2016 at 09:20:50AM +0000, Mcnamara, John wrote:
> > Repost from the moving at dpdk.org mailing list to get a wider audience.
> > Original thread: http://dpdk.org/ml/archives/moving/2016-November/000059.html
> >
> >
> > Hi,
> >
> > I'd like to propose a change to the DPDK committer model. Currently we have one committer for the master branch of the DPDK project.
> >
> > One committer to master represents a single point of failure and at times can be inefficient. There is also no agreed cover for times when the committer is unavailable such as vacation, public holidays, etc. I propose that we change to a multi-committer model for the DPDK project. We should have three committers for each release that can commit changes to the master branch.
> >
> > There are a number of benefits:
> >
> > 1. Greater capacity to commit patches.
> > 2. No single points of failure - a committer should always be available if we have three.
> > 3. A more timely committing of patches. More committers should equal a faster turnaround - ideally, maintainers should also provide feedback on patches submitted within a 2-3 day period, as much as possible, to facilitate this.
> > 4. It follows best practice in creating a successful multi-vendor community - to achieve this we must ensure there is a level playing field for all participants, no single person should be required to make all of the decisions on patches to be included in the release.
> >
> > Having multiple committers will require some degree of co-ordination but there are a number of other communities successfully following this model such as Apache, OVS, FD.io, OpenStack etc. so the approach is workable.
> >
> > John
>
> I agree that the problems you are attempting to address exist and are
> worth finding a solution for. That said, I don't think the solution you
> are proposing is the ideal, or complete fix for any of the issues being
> addressed.
>
> If I may, I'd like to ennumerate the issues I think you are trying to
> address based on your comments above, then make a counter-proposal for a
> solution:
>
> Problems to address:
>
> 1) high-availability - There is a desire to make sure that, when patches
> are proposed, they are integrated in a timely fashion.
>
> 2) high-throughput - DPDK has a large volume of patches, more than one
> person can normally integrate. There is a desire to shard that work such
> that it is handled by multiple individuals
>
> 3) Multi-Vendor fairness - There is a desire for multiple vendors to feel
> as though the project tree maintainer isn't biased toward any individual
> vendor.
>
> To solve these I would propose the following solution (which is simmilar
> to, but not quite identical, to yours).
>
> A) Further promote subtree maintainership. This was a conversation that I
> proposed some time ago, but my proposed granularity was discarded in favor
> of something that hasn't worked as well (in my opinion). That is to say a
> few driver pmds (i40e and fm10k come to mind) have their own tree that
> send pull requests to Thomas. We should be sharding that at a much higher
> granularity and using it much more consistently. That is to say, that we
> should have a maintainer for all the ethernet pmds, and another for the
> crypto pmds, another for the core eal layer, another for misc libraries
> that have low patch volumes, etc. Each of those subdivisions should have
> their own list to communicate on, and each should have a tree that
> integrates patches for their own subsystem, and they should on a regular
> cycle send pull requests to Thomas. Thomas in turn should by and large,
> only be integrating pull requests. This should address our high-
> throughput issue, in that it will allow multiple maintainers to share the
> workload, and integration should be relatively easy.
+1
>
> B) Designate alternates to serve as backups for the maintainer when they
> are unavailable. This provides high-availablility, and sounds very much
> like your proposal, but in the interests of clarity, there is still a
> single maintainer at any one time, it just may change to ensure the
> continued merging of patches, if the primary maintainer isn't available.
> Ideally however, those backup alternates arent needed, because most of the
> primary maintainers work in merging pull requests, which are done based on
> the trust of the submaintainer, and done during a very limited window of
> time. This also partially addreses multi-vendor fairness if your subtree
> maintainers come from multiple participating companies.
+1
>
> Regards
> Neil
>
>
^ permalink raw reply
* Re: [PATCH 0/4] libeventdev API and northbound implementation
From: Jerin Jacob @ 2016-11-18 19:27 UTC (permalink / raw)
To: Bruce Richardson
Cc: dev, harry.van.haaren, hemant.agrawal, gage.eads, thomas.monjalon
In-Reply-To: <20161118160428.GA123692@bricha3-MOBL3.ger.corp.intel.com>
On Fri, Nov 18, 2016 at 04:04:29PM +0000, Bruce Richardson wrote:
> +Thomas
>
> On Fri, Nov 18, 2016 at 03:25:18PM +0000, Bruce Richardson wrote:
> > On Fri, Nov 18, 2016 at 11:14:58AM +0530, Jerin Jacob wrote:
> > > As previously discussed in RFC v1 [1], RFC v2 [2], with changes
> > > described in [3] (also pasted below), here is the first non-draft series
> > > for this new API.
> > >
> > > [1] http://dpdk.org/ml/archives/dev/2016-August/045181.html
> > > [2] http://dpdk.org/ml/archives/dev/2016-October/048592.html
> > > [3] http://dpdk.org/ml/archives/dev/2016-October/048196.html
> > >
> > > Changes since RFC v2:
> > >
> > > - Updated the documentation to define the need for this library[Jerin]
> > > - Added RTE_EVENT_QUEUE_CFG_*_ONLY configuration parameters in
> > > struct rte_event_queue_conf to enable optimized sw implementation [Bruce]
> > > - Introduced RTE_EVENT_OP* ops [Bruce]
> > > - Added nb_event_queue_flows,nb_event_port_dequeue_depth, nb_event_port_enqueue_depth
> > > in rte_event_dev_configure() like ethdev and crypto library[Jerin]
> > > - Removed rte_event_release() and replaced with RTE_EVENT_OP_RELEASE ops to
> > > reduce fast path APIs and it is redundant too[Jerin]
> > > - In the view of better application portability, Removed pin_event
> > > from rte_event_enqueue as it is just hint and Intel/NXP can not support it[Jerin]
> > > - Added rte_event_port_links_get()[Jerin]
> > > - Added rte_event_dev_dump[Harry]
> > >
> > > Notes:
> > >
> > > - This patch set is check-patch clean with an exception that
> > > 02/04 has one WARNING:MACRO_WITH_FLOW_CONTROL
> > > - Looking forward to getting additional maintainers for libeventdev
> > >
> > >
> > > Possible next steps:
> > > 1) Review this patch set
> > > 2) Integrate Intel's SW driver[http://dpdk.org/dev/patchwork/patch/17049/]
> > > 3) Review proposed examples/eventdev_pipeline application[http://dpdk.org/dev/patchwork/patch/17053/]
> > > 4) Review proposed functional tests[http://dpdk.org/dev/patchwork/patch/17051/]
> > > 5) Cavium's HW based eventdev driver
> > >
> > > I am planning to work on (3),(4) and (5)
> > >
> > Thanks Jerin,
> >
> > we'll review and get back to you with any comments or feedback (1), and
> > obviously start working on item (2) also! :-)
> >
> > I'm also wonder whether we should have a staging tree for this work to
> > make interaction between us easier. Although this may not be
> > finalised enough for 17.02 release, do you think having an
> > dpdk-eventdev-next tree would be a help? My thinking is that once we get
> > the eventdev library itself in reasonable shape following our review, we
> > could commit that and make any changes thereafter as new patches, rather
> > than constantly respinning the same set. It also gives us a clean git
> > tree to base the respective driver implementations on from our two sides.
> >
> > Thomas, any thoughts here on your end - or from anyone else?
I was thinking more or less along the same lines. To avoid re-spinning the
same set, it is better to have libeventdev library mark as EXPERIMENTAL
and commit it somewhere on dpdk-eventdev-next or main tree
I think, EXPERIMENTAL status can be changed only when
- At least two event drivers available
- Functional test applications fine with at least two drivers
- Portable example application to showcase the features of the library
- eventdev integration with another dpdk subsystem such as ethdev
Jerin
> >
> > Regards,
> > /Bruce
> >
^ permalink raw reply
* Re: [RFC PATCH 0/7] RFC: EventDev Software PMD
From: Jerin Jacob @ 2016-11-18 22:23 UTC (permalink / raw)
To: Bruce Richardson; +Cc: Harry van Haaren, dev
In-Reply-To: <20161117100507.GA67928@bricha3-MOBL3.ger.corp.intel.com>
On Thu, Nov 17, 2016 at 10:05:07AM +0000, Bruce Richardson wrote:
> > 2) device stats API can be based on capability, HW implementations may not
> > support all the stats
>
> Yes, this is something we were thinking about. It would be nice if we
> could at least come up with a common set of stats - maybe even ones
> tracked at an eventdev API level, e.g. nb enqueues/dequeues. As well as
> that, we think the idea of an xstats API, like in ethdev, might work
> well. For our software implementation, having visibility into the
> scheduler behaviour can be important, so we'd like a way to report out
> things like internal queue depths etc.
>
Since these are not very generic hardware, I am not sure how much sense
to have generic stats API. But, Something similar to ethdev's xstat(any capability based)
the scheme works well. Look forward to seeing API proposal with common code.
Jerin
^ permalink raw reply
* Question about time library
From: 墨 输 @ 2016-11-19 2:32 UTC (permalink / raw)
To: dev@dpdk.org
Hi,everyone
First of all, thank you for reading my email.
When I read the code of time library,I meet one point that I don't understand fully.
In the function rte_timer_manage(),if a periodic timer expire, before calling the function __rte_timer_reset(), its state is changed to RTE_TIMER_PENDING, and all layers of skiplist's pending_head is modified to point to unexpired timers' list, that is , the timer to reset is not involved in the skiplist--priv_timer[tim_lcore].pending_head.
But in the function __rte_timer_reset() called by rte_timer_manage(), if the timer's previous state(after calling timer_set_config_state()) is RTE_TIMER_PENDING, it will call timer_del() to remove the timer from the skiplist -- priv_timer[tim_lcore].pending_head, however, the timer is already not in the skiplist now.
That is what I don't understand fully,if anyone knows about it, please tell me.
Thanks.
Titen
^ permalink raw reply
* [PATCH] ethdev: don't look for devices if none were found
From: Anatoly Burakov @ 2016-11-19 13:10 UTC (permalink / raw)
To: dev
Aside from avoiding doing useless work, this also fixes a segfault
when calling rte_eth_dev_get_port_by_name() whenever no devices
were found yet, and therefore rte_eth_dev_data wasn't yet allocated.
Fixes: 9c5b8d8b9feb ("ethdev: clean port id retrieval when attaching")
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
lib/librte_ether/rte_ethdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/librte_ether/rte_ethdev.c b/lib/librte_ether/rte_ethdev.c
index fde8112..76a6dbf 100644
--- a/lib/librte_ether/rte_ethdev.c
+++ b/lib/librte_ether/rte_ethdev.c
@@ -376,6 +376,9 @@ rte_eth_dev_get_port_by_name(const char *name, uint8_t *port_id)
return -EINVAL;
}
+ if (!nb_ports)
+ return -ENODEV;
+
*port_id = RTE_MAX_ETHPORTS;
for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
--
2.5.5
^ permalink raw reply related
* Re: Proposal for a new Committer model
From: Stephen Hemminger @ 2016-11-20 4:17 UTC (permalink / raw)
To: Jerin Jacob; +Cc: Neil Horman, Mcnamara, John, dev@dpdk.org
In-Reply-To: <20161118190604.GA8335@localhost.localdomain>
why aren't some patches as marked trivial and accepted right away.
On Fri, Nov 18, 2016 at 11:06 AM, Jerin Jacob <
jerin.jacob@caviumnetworks.com> wrote:
> On Fri, Nov 18, 2016 at 01:09:35PM -0500, Neil Horman wrote:
> > On Thu, Nov 17, 2016 at 09:20:50AM +0000, Mcnamara, John wrote:
> > > Repost from the moving at dpdk.org mailing list to get a wider
> audience.
> > > Original thread: http://dpdk.org/ml/archives/
> moving/2016-November/000059.html
> > >
> > >
> > > Hi,
> > >
> > > I'd like to propose a change to the DPDK committer model. Currently we
> have one committer for the master branch of the DPDK project.
> > >
> > > One committer to master represents a single point of failure and at
> times can be inefficient. There is also no agreed cover for times when the
> committer is unavailable such as vacation, public holidays, etc. I propose
> that we change to a multi-committer model for the DPDK project. We should
> have three committers for each release that can commit changes to the
> master branch.
> > >
> > > There are a number of benefits:
> > >
> > > 1. Greater capacity to commit patches.
> > > 2. No single points of failure - a committer should always be
> available if we have three.
> > > 3. A more timely committing of patches. More committers should equal a
> faster turnaround - ideally, maintainers should also provide feedback on
> patches submitted within a 2-3 day period, as much as possible, to
> facilitate this.
> > > 4. It follows best practice in creating a successful multi-vendor
> community - to achieve this we must ensure there is a level playing field
> for all participants, no single person should be required to make all of
> the decisions on patches to be included in the release.
> > >
> > > Having multiple committers will require some degree of co-ordination
> but there are a number of other communities successfully following this
> model such as Apache, OVS, FD.io, OpenStack etc. so the approach is
> workable.
> > >
> > > John
> >
> > I agree that the problems you are attempting to address exist and are
> > worth finding a solution for. That said, I don't think the solution you
> > are proposing is the ideal, or complete fix for any of the issues being
> > addressed.
> >
> > If I may, I'd like to ennumerate the issues I think you are trying to
> > address based on your comments above, then make a counter-proposal for a
> > solution:
> >
> > Problems to address:
> >
> > 1) high-availability - There is a desire to make sure that, when patches
> > are proposed, they are integrated in a timely fashion.
> >
> > 2) high-throughput - DPDK has a large volume of patches, more than one
> > person can normally integrate. There is a desire to shard that work such
> > that it is handled by multiple individuals
> >
> > 3) Multi-Vendor fairness - There is a desire for multiple vendors to feel
> > as though the project tree maintainer isn't biased toward any individual
> > vendor.
> >
> > To solve these I would propose the following solution (which is simmilar
> > to, but not quite identical, to yours).
> >
> > A) Further promote subtree maintainership. This was a conversation that
> I
> > proposed some time ago, but my proposed granularity was discarded in
> favor
> > of something that hasn't worked as well (in my opinion). That is to say
> a
> > few driver pmds (i40e and fm10k come to mind) have their own tree that
> > send pull requests to Thomas. We should be sharding that at a much
> higher
> > granularity and using it much more consistently. That is to say, that we
> > should have a maintainer for all the ethernet pmds, and another for the
> > crypto pmds, another for the core eal layer, another for misc libraries
> > that have low patch volumes, etc. Each of those subdivisions should have
> > their own list to communicate on, and each should have a tree that
> > integrates patches for their own subsystem, and they should on a regular
> > cycle send pull requests to Thomas. Thomas in turn should by and large,
> > only be integrating pull requests. This should address our high-
> > throughput issue, in that it will allow multiple maintainers to share the
> > workload, and integration should be relatively easy.
>
> +1
>
> >
> > B) Designate alternates to serve as backups for the maintainer when they
> > are unavailable. This provides high-availablility, and sounds very much
> > like your proposal, but in the interests of clarity, there is still a
> > single maintainer at any one time, it just may change to ensure the
> > continued merging of patches, if the primary maintainer isn't available.
> > Ideally however, those backup alternates arent needed, because most of
> the
> > primary maintainers work in merging pull requests, which are done based
> on
> > the trust of the submaintainer, and done during a very limited window of
> > time. This also partially addreses multi-vendor fairness if your subtree
> > maintainers come from multiple participating companies.
>
> +1
>
> >
> > Regards
> > Neil
> >
> >
>
^ permalink raw reply
* [PATCH] eal: postpone vdev initialization
From: Jerin Jacob @ 2016-11-20 8:00 UTC (permalink / raw)
To: dev; +Cc: declan.doherty, david.marchand, thomas.monjalon, Jerin Jacob
Some platform like octeontx may use pci and
vdev based combined device to represent a logical
dpdk functional device.In such case, postponing the
vdev initialization after pci device
initialization will provide the better view of
the pci device resources in the system in
vdev's probe function, and it allows better
functional subsystem registration in vdev probe
function.
As a bonus, This patch fixes a bond device
initialization use case.
example command to reproduce the issue:
./testpmd -c 0x2 --vdev 'eth_bond0,mode=0,
slave=0000:02:00.0,slave=0000:03:00.0' --
--port-topology=chained
root cause:
In existing case(vdev initialization and then pci
initialization), creates three Ethernet ports with
following port ids
0 - Bond device
1 - PCI device 0
2 - PCI devive 1
Since testpmd, calls the configure/start on all the ports on
start up,it will translate to following illegal setup sequence
1)bond device configure/start
1.1) pci device0 stop/configure/start
1.2) pci device1 stop/configure/start
2)pci device 0 configure(illegal setup case,
as device in start state)
The fix changes the initialization sequence and
allow initialization in following valid setup order
1) pcie device 0 configure/start
2) pcie device 1 configure/start
3) bond device 2 configure/start
3.1) pcie device 0/stop/configure/start
3.2) pcie device 1/stop/configure/start
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
lib/librte_eal/bsdapp/eal/eal.c | 6 +++---
lib/librte_eal/linuxapp/eal/eal.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/lib/librte_eal/bsdapp/eal/eal.c b/lib/librte_eal/bsdapp/eal/eal.c
index 35e3117..2206277 100644
--- a/lib/librte_eal/bsdapp/eal/eal.c
+++ b/lib/librte_eal/bsdapp/eal/eal.c
@@ -577,9 +577,6 @@ rte_eal_init(int argc, char **argv)
rte_config.master_lcore, thread_id, cpuset,
ret == 0 ? "" : "...");
- if (rte_eal_dev_init() < 0)
- rte_panic("Cannot init pmd devices\n");
-
RTE_LCORE_FOREACH_SLAVE(i) {
/*
@@ -616,6 +613,9 @@ rte_eal_init(int argc, char **argv)
if (rte_eal_pci_probe())
rte_panic("Cannot probe PCI\n");
+ if (rte_eal_dev_init() < 0)
+ rte_panic("Cannot init pmd devices\n");
+
rte_eal_mcfg_complete();
return fctret;
diff --git a/lib/librte_eal/linuxapp/eal/eal.c b/lib/librte_eal/linuxapp/eal/eal.c
index 2075282..16dd5b9 100644
--- a/lib/librte_eal/linuxapp/eal/eal.c
+++ b/lib/librte_eal/linuxapp/eal/eal.c
@@ -841,9 +841,6 @@ rte_eal_init(int argc, char **argv)
rte_config.master_lcore, (int)thread_id, cpuset,
ret == 0 ? "" : "...");
- if (rte_eal_dev_init() < 0)
- rte_panic("Cannot init pmd devices\n");
-
if (rte_eal_intr_init() < 0)
rte_panic("Cannot init interrupt-handling thread\n");
@@ -887,6 +884,9 @@ rte_eal_init(int argc, char **argv)
if (rte_eal_pci_probe())
rte_panic("Cannot probe PCI\n");
+ if (rte_eal_dev_init() < 0)
+ rte_panic("Cannot init pmd devices\n");
+
rte_eal_mcfg_complete();
return fctret;
--
2.5.5
^ permalink raw reply related
* [PATCH 1/7] eal: define container_of macro
From: Jan Blunck @ 2016-11-20 10:05 UTC (permalink / raw)
To: dev; +Cc: shreyansh.jain, Jan Viktorin
This macro is based on Jan Viktorin's original patch but also checks the
type of the passed pointer against the type of the member.
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
[jblunck@infradead.org: add type checking and __extension__]
Signed-off-by: Jan Blunck <jblunck@infradead.org>
---
lib/librte_eal/common/include/rte_common.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/lib/librte_eal/common/include/rte_common.h b/lib/librte_eal/common/include/rte_common.h
index db5ac91..8dda3e2 100644
--- a/lib/librte_eal/common/include/rte_common.h
+++ b/lib/librte_eal/common/include/rte_common.h
@@ -331,6 +331,26 @@ rte_bsf32(uint32_t v)
#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER)
#endif
+/**
+ * Return pointer to the wrapping struct instance.
+ *
+ * Example:
+ *
+ * struct wrapper {
+ * ...
+ * struct child c;
+ * ...
+ * };
+ *
+ * struct child *x = obtain(...);
+ * struct wrapper *w = container_of(x, struct wrapper, c);
+ */
+#ifndef container_of
+#define container_of(ptr, type, member) __extension__ ({ \
+ typeof(((type *)0)->member) *_ptr = (ptr); \
+ (type *)(((char *)_ptr) - offsetof(type, member)); })
+#endif
+
#define _RTE_STR(x) #x
/** Take a macro value and get a string version of it */
#define RTE_STR(x) _RTE_STR(x)
--
2.7.4
^ permalink raw reply related
* [PATCH 2/7] eal: Helper to convert to struct rte_pci_device
From: Jan Blunck @ 2016-11-20 10:05 UTC (permalink / raw)
To: dev; +Cc: shreyansh.jain
In-Reply-To: <1479636327-4166-1-git-send-email-jblunck@infradead.org>
Signed-off-by: Jan Blunck <jblunck@infradead.org>
---
lib/librte_eal/common/include/rte_pci.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h
index 9ce8847..0376160 100644
--- a/lib/librte_eal/common/include/rte_pci.h
+++ b/lib/librte_eal/common/include/rte_pci.h
@@ -160,6 +160,8 @@ struct rte_pci_device {
enum rte_kernel_driver kdrv; /**< Kernel driver passthrough */
};
+#define ETH_DEV_PCI_DEV(ptr) ((ptr)->pci_dev)
+
/** Any PCI device identifier (vendor, device, ...) */
#define PCI_ANY_ID (0xffff)
#define RTE_CLASS_ANY_ID (0xffffff)
--
2.7.4
^ permalink raw reply related
* [PATCH 3/7] drivers: Use ETH_DEV_PCI_DEV() helper
From: Jan Blunck @ 2016-11-20 10:05 UTC (permalink / raw)
To: dev; +Cc: shreyansh.jain
In-Reply-To: <1479636327-4166-1-git-send-email-jblunck@infradead.org>
The drivers should not directly access the rte_eth_dev->pci_dev but use
a macro instead. This is a preparation for replacing the pci_dev with
a struct rte_device member in the future.
Signed-off-by: Jan Blunck <jblunck@infradead.org>
---
drivers/net/bnxt/bnxt_ethdev.c | 19 ++++++-----
drivers/net/bnxt/bnxt_ring.c | 11 +++---
drivers/net/cxgbe/cxgbe_ethdev.c | 2 +-
drivers/net/e1000/em_ethdev.c | 20 ++++++-----
drivers/net/e1000/igb_ethdev.c | 50 +++++++++++++++------------
drivers/net/e1000/igb_pf.c | 3 +-
drivers/net/ena/ena_ethdev.c | 2 +-
drivers/net/enic/enic_ethdev.c | 2 +-
drivers/net/fm10k/fm10k_ethdev.c | 49 ++++++++++++++-------------
drivers/net/i40e/i40e_ethdev.c | 44 ++++++++++++------------
drivers/net/i40e/i40e_ethdev.h | 4 +++
drivers/net/i40e/i40e_ethdev_vf.c | 38 ++++++++++-----------
drivers/net/ixgbe/ixgbe_ethdev.c | 65 +++++++++++++++++++++---------------
drivers/net/ixgbe/ixgbe_pf.c | 2 +-
drivers/net/qede/qede_ethdev.c | 17 +++++-----
drivers/net/vmxnet3/vmxnet3_ethdev.c | 4 +--
16 files changed, 185 insertions(+), 147 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 035fe07..cd50f11 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -743,6 +743,7 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(eth_dev);
/* Retrieve from the default VNIC */
if (!vnic)
@@ -759,7 +760,7 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
/* EW - need to revisit here copying from u64 to u16 */
memcpy(reta_conf, vnic->rss_table, reta_size);
- if (rte_intr_allow_others(ð_dev->pci_dev->intr_handle)) {
+ if (rte_intr_allow_others(&pci_dev->intr_handle)) {
if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
bnxt_dev_lsc_intr_setup(eth_dev);
}
@@ -1011,9 +1012,10 @@ static int bnxt_init_board(struct rte_eth_dev *eth_dev)
{
int rc;
struct bnxt *bp = eth_dev->data->dev_private;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(eth_dev);
/* enable device (incl. PCI PM wakeup), and bus-mastering */
- if (!eth_dev->pci_dev->mem_resource[0].addr) {
+ if (!pci_dev->mem_resource[0].addr) {
RTE_LOG(ERR, PMD,
"Cannot find PCI device base address, aborting\n");
rc = -ENODEV;
@@ -1021,9 +1023,9 @@ static int bnxt_init_board(struct rte_eth_dev *eth_dev)
}
bp->eth_dev = eth_dev;
- bp->pdev = eth_dev->pci_dev;
+ bp->pdev = pci_dev;
- bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
+ bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
if (!bp->bar0) {
RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
rc = -ENOMEM;
@@ -1043,6 +1045,7 @@ static int bnxt_init_board(struct rte_eth_dev *eth_dev)
static int
bnxt_dev_init(struct rte_eth_dev *eth_dev)
{
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(eth_dev);
static int version_printed;
struct bnxt *bp;
int rc;
@@ -1050,10 +1053,10 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev)
if (version_printed++ == 0)
RTE_LOG(INFO, PMD, "%s", bnxt_version);
- rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
+ rte_eth_copy_pci_info(eth_dev, pci_dev);
bp = eth_dev->data->dev_private;
- if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
+ if (bnxt_vf_pciid(pci_dev->id.device_id))
bp->flags |= BNXT_FLAG_VF;
rc = bnxt_init_board(eth_dev);
@@ -1121,8 +1124,8 @@ bnxt_dev_init(struct rte_eth_dev *eth_dev)
RTE_LOG(INFO, PMD,
DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
- eth_dev->pci_dev->mem_resource[0].phys_addr,
- eth_dev->pci_dev->mem_resource[0].addr);
+ pci_dev->mem_resource[0].phys_addr,
+ pci_dev->mem_resource[0].addr);
bp->dev_stopped = 0;
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index 3f81ffc..6793d75 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -209,6 +209,7 @@ int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx,
*/
int bnxt_alloc_hwrm_rings(struct bnxt *bp)
{
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(bp->eth_dev);
unsigned int i;
int rc = 0;
@@ -223,7 +224,7 @@ int bnxt_alloc_hwrm_rings(struct bnxt *bp)
if (rc)
goto err_out;
cpr->cp_doorbell =
- (char *)bp->eth_dev->pci_dev->mem_resource[2].addr;
+ (char *)pci_dev->mem_resource[2].addr;
B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
bp->grp_info[0].cp_fw_ring_id = cp_ring->fw_ring_id;
}
@@ -243,7 +244,7 @@ int bnxt_alloc_hwrm_rings(struct bnxt *bp)
if (rc)
goto err_out;
cpr->cp_doorbell =
- (char *)bp->eth_dev->pci_dev->mem_resource[2].addr +
+ (char *)pci_dev->mem_resource[2].addr +
idx * 0x80;
bp->grp_info[idx].cp_fw_ring_id = cp_ring->fw_ring_id;
B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
@@ -256,7 +257,7 @@ int bnxt_alloc_hwrm_rings(struct bnxt *bp)
goto err_out;
rxr->rx_prod = 0;
rxr->rx_doorbell =
- (char *)bp->eth_dev->pci_dev->mem_resource[2].addr +
+ (char *)pci_dev->mem_resource[2].addr +
idx * 0x80;
bp->grp_info[idx].rx_fw_ring_id = ring->fw_ring_id;
B_RX_DB(rxr->rx_doorbell, rxr->rx_prod);
@@ -284,7 +285,7 @@ int bnxt_alloc_hwrm_rings(struct bnxt *bp)
goto err_out;
cpr->cp_doorbell =
- (char *)bp->eth_dev->pci_dev->mem_resource[2].addr +
+ (char *)pci_dev->mem_resource[2].addr +
idx * 0x80;
bp->grp_info[idx].cp_fw_ring_id = cp_ring->fw_ring_id;
B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
@@ -297,7 +298,7 @@ int bnxt_alloc_hwrm_rings(struct bnxt *bp)
goto err_out;
txr->tx_doorbell =
- (char *)bp->eth_dev->pci_dev->mem_resource[2].addr +
+ (char *)pci_dev->mem_resource[2].addr +
idx * 0x80;
}
diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c
index b7f28eb..8bfdda8 100644
--- a/drivers/net/cxgbe/cxgbe_ethdev.c
+++ b/drivers/net/cxgbe/cxgbe_ethdev.c
@@ -1005,7 +1005,7 @@ static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
adapter = rte_zmalloc(name, sizeof(*adapter), 0);
diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c
index aee3d34..7f2f521 100644
--- a/drivers/net/e1000/em_ethdev.c
+++ b/drivers/net/e1000/em_ethdev.c
@@ -295,7 +295,7 @@ eth_em_dev_init(struct rte_eth_dev *eth_dev)
struct e1000_vfta * shadow_vfta =
E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
eth_dev->dev_ops = ð_em_ops;
eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
@@ -369,7 +369,7 @@ eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return -EPERM;
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
if (adapter->stopped == 0)
eth_em_close(eth_dev);
@@ -556,7 +556,8 @@ eth_em_start(struct rte_eth_dev *dev)
E1000_DEV_PRIVATE(dev->data->dev_private);
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
int ret, mask;
uint32_t intr_vector = 0;
uint32_t *speeds;
@@ -738,7 +739,8 @@ eth_em_stop(struct rte_eth_dev *dev)
{
struct rte_eth_link link;
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
em_rxq_intr_disable(hw);
em_lsc_intr_disable(hw);
@@ -999,9 +1001,10 @@ static int
eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
{
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
em_rxq_intr_enable(hw);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(&pci_dev->intr_handle);
return 0;
}
@@ -1542,6 +1545,7 @@ eth_em_interrupt_action(struct rte_eth_dev *dev)
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct e1000_interrupt *intr =
E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
uint32_t tctl, rctl;
struct rte_eth_link link;
int ret;
@@ -1550,7 +1554,7 @@ eth_em_interrupt_action(struct rte_eth_dev *dev)
return -1;
intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
- rte_intr_enable(&(dev->pci_dev->intr_handle));
+ rte_intr_enable(&pci_dev->intr_handle);
/* set get_link_status to check register later */
hw->mac.get_link_status = 1;
@@ -1571,8 +1575,8 @@ eth_em_interrupt_action(struct rte_eth_dev *dev)
PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
}
PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
- dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
- dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
+ pci_dev->addr.domain, pci_dev->addr.bus,
+ pci_dev->addr.devid, pci_dev->addr.function);
tctl = E1000_READ_REG(hw, E1000_TCTL);
rctl = E1000_READ_REG(hw, E1000_RCTL);
diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index 2fddf0c..b25c66e 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -672,11 +672,11 @@ igb_identify_hardware(struct rte_eth_dev *dev)
{
struct e1000_hw *hw =
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
-
- hw->vendor_id = dev->pci_dev->id.vendor_id;
- hw->device_id = dev->pci_dev->id.device_id;
- hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
- hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
+ hw->vendor_id = pci_dev->id.vendor_id;
+ hw->device_id = pci_dev->id.device_id;
+ hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
+ hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
e1000_set_mac_type(hw);
@@ -755,7 +755,7 @@ eth_igb_dev_init(struct rte_eth_dev *eth_dev)
uint32_t ctrl_ext;
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
eth_dev->dev_ops = ð_igb_ops;
eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
@@ -918,7 +918,7 @@ eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
return -EPERM;
hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
if (adapter->stopped == 0)
eth_igb_close(eth_dev);
@@ -973,7 +973,7 @@ eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
return 0;
}
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
rte_eth_copy_pci_info(eth_dev, pci_dev);
@@ -1050,7 +1050,7 @@ eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
{
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(eth_dev->data->dev_private);
- struct rte_pci_device *pci_dev = eth_dev->pci_dev;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(eth_dev);
PMD_INIT_FUNC_TRACE();
@@ -1217,7 +1217,8 @@ eth_igb_start(struct rte_eth_dev *dev)
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle =
+ Ð_DEV_PCI_DEV(dev)->intr_handle;
int ret, mask;
uint32_t intr_vector = 0;
uint32_t ctrl_ext;
@@ -1429,7 +1430,8 @@ eth_igb_stop(struct rte_eth_dev *dev)
struct e1000_flex_filter *p_flex;
struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle =
+ Ð_DEV_PCI_DEV(dev)->intr_handle;
igb_intr_disable(hw);
@@ -1549,7 +1551,7 @@ eth_igb_close(struct rte_eth_dev *dev)
igb_dev_free_queues(dev);
- pci_dev = dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(dev);
if (pci_dev->intr_handle.intr_vec) {
rte_free(pci_dev->intr_handle.intr_vec);
pci_dev->intr_handle.intr_vec = NULL;
@@ -2639,6 +2641,7 @@ eth_igb_interrupt_action(struct rte_eth_dev *dev)
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct e1000_interrupt *intr =
E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
uint32_t tctl, rctl;
struct rte_eth_link link;
int ret;
@@ -2649,7 +2652,7 @@ eth_igb_interrupt_action(struct rte_eth_dev *dev)
}
igb_intr_enable(dev);
- rte_intr_enable(&(dev->pci_dev->intr_handle));
+ rte_intr_enable(&pci_dev->intr_handle);
if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
@@ -2677,10 +2680,10 @@ eth_igb_interrupt_action(struct rte_eth_dev *dev)
}
PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
- dev->pci_dev->addr.domain,
- dev->pci_dev->addr.bus,
- dev->pci_dev->addr.devid,
- dev->pci_dev->addr.function);
+ pci_dev->addr.domain,
+ pci_dev->addr.bus,
+ pci_dev->addr.devid,
+ pci_dev->addr.function);
tctl = E1000_READ_REG(hw, E1000_TCTL);
rctl = E1000_READ_REG(hw, E1000_RCTL);
if (link.link_status) {
@@ -2770,7 +2773,7 @@ eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
}
igbvf_intr_enable(dev);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(Ð_DEV_PCI_DEV(dev)->intr_handle);
return 0;
}
@@ -3056,7 +3059,8 @@ igbvf_dev_start(struct rte_eth_dev *dev)
struct e1000_adapter *adapter =
E1000_DEV_PRIVATE(dev->data->dev_private);
int ret;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle =
+ Ð_DEV_PCI_DEV(dev)->intr_handle;
uint32_t intr_vector = 0;
PMD_INIT_FUNC_TRACE();
@@ -3110,7 +3114,8 @@ igbvf_dev_start(struct rte_eth_dev *dev)
static void
igbvf_dev_stop(struct rte_eth_dev *dev)
{
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle =
+ Ð_DEV_PCI_DEV(dev)->intr_handle;
PMD_INIT_FUNC_TRACE();
@@ -5102,7 +5107,7 @@ eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
E1000_WRITE_FLUSH(hw);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(Ð_DEV_PCI_DEV(dev)->intr_handle);
return 0;
}
@@ -5167,7 +5172,8 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
uint32_t base = E1000_MISC_VEC_ID;
uint32_t misc_shift = 0;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle =
+ Ð_DEV_PCI_DEV(dev)->intr_handle;
/* won't configure msix register if no mapping is done
* between intr vector and event fd
diff --git a/drivers/net/e1000/igb_pf.c b/drivers/net/e1000/igb_pf.c
index 5845bc2..6a72ee1 100644
--- a/drivers/net/e1000/igb_pf.c
+++ b/drivers/net/e1000/igb_pf.c
@@ -57,7 +57,8 @@
static inline uint16_t
dev_num_vf(struct rte_eth_dev *eth_dev)
{
- return eth_dev->pci_dev->max_vfs;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(eth_dev);
+ return pci_dev->max_vfs;
}
static inline
diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index ab9a178..c17d969 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -1278,7 +1278,7 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
adapter->pdev = pci_dev;
PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
diff --git a/drivers/net/enic/enic_ethdev.c b/drivers/net/enic/enic_ethdev.c
index 2b154ec..553a88e 100644
--- a/drivers/net/enic/enic_ethdev.c
+++ b/drivers/net/enic/enic_ethdev.c
@@ -621,7 +621,7 @@ static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev)
eth_dev->rx_pkt_burst = &enic_recv_pkts;
eth_dev->tx_pkt_burst = &enic_xmit_pkts;
- pdev = eth_dev->pci_dev;
+ pdev = ETH_DEV_PCI_DEV(eth_dev);
rte_eth_copy_pci_info(eth_dev, pdev);
enic->pdev = pdev;
addr = &pdev->addr;
diff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c
index 923690c..e1250f6 100644
--- a/drivers/net/fm10k/fm10k_ethdev.c
+++ b/drivers/net/fm10k/fm10k_ethdev.c
@@ -59,7 +59,8 @@
#define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
/* default 1:1 map from queue ID to interrupt vector ID */
-#define Q2V(dev, queue_id) (dev->pci_dev->intr_handle.intr_vec[queue_id])
+#define D2IH(dev) (Ð_DEV_PCI_DEV(dev)->intr_handle)
+#define Q2V(dev, queue_id) (D2IH(dev)->intr_vec[queue_id])
/* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
#define MAX_LPORT_NUM 128
@@ -711,7 +712,7 @@ fm10k_dev_rx_init(struct rte_eth_dev *dev)
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct fm10k_macvlan_filter_info *macvlan;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = D2IH(dev);
int i, ret;
struct fm10k_rx_queue *rxq;
uint64_t base_addr;
@@ -1171,7 +1172,7 @@ static void
fm10k_dev_stop(struct rte_eth_dev *dev)
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = D2IH(dev);
int i;
PMD_INIT_FUNC_TRACE();
@@ -1387,6 +1388,7 @@ fm10k_dev_infos_get(struct rte_eth_dev *dev,
struct rte_eth_dev_info *dev_info)
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
PMD_INIT_FUNC_TRACE();
@@ -1396,7 +1398,7 @@ fm10k_dev_infos_get(struct rte_eth_dev *dev,
dev_info->max_tx_queues = hw->mac.max_queues;
dev_info->max_mac_addrs = FM10K_MAX_MACADDR_NUM;
dev_info->max_hash_mac_addrs = 0;
- dev_info->max_vfs = dev->pci_dev->max_vfs;
+ dev_info->max_vfs = pci_dev->max_vfs;
dev_info->vmdq_pool_base = 0;
dev_info->vmdq_queue_base = 0;
dev_info->max_vmdq_pools = ETH_32_POOLS;
@@ -2341,7 +2343,7 @@ fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
else
FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(D2IH(dev));
return 0;
}
@@ -2364,7 +2366,7 @@ static int
fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = D2IH(dev);
uint32_t intr_vector, vec;
uint16_t queue_id;
int result = 0;
@@ -2380,7 +2382,7 @@ fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
intr_vector = dev->data->nb_rx_queues;
/* disable interrupt first */
- rte_intr_disable(&dev->pci_dev->intr_handle);
+ rte_intr_disable(intr_handle);
if (hw->mac.type == fm10k_mac_pf)
fm10k_dev_disable_intr_pf(dev);
else
@@ -2415,7 +2417,7 @@ fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
fm10k_dev_enable_intr_pf(dev);
else
fm10k_dev_enable_intr_vf(dev);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(intr_handle);
hw->mac.ops.update_int_moderator(hw);
return result;
}
@@ -2581,7 +2583,7 @@ fm10k_dev_interrupt_handler_pf(
FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
FM10K_ITR_MASK_CLEAR);
/* Re-enable interrupt from host side */
- rte_intr_enable(&(dev->pci_dev->intr_handle));
+ rte_intr_enable(D2IH(dev));
}
/**
@@ -2615,7 +2617,7 @@ fm10k_dev_interrupt_handler_vf(
FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
FM10K_ITR_MASK_CLEAR);
/* Re-enable interrupt from host side */
- rte_intr_enable(&(dev->pci_dev->intr_handle));
+ rte_intr_enable(D2IH(dev));
}
/* Mailbox message handler in VF */
@@ -2827,6 +2829,7 @@ static int
eth_fm10k_dev_init(struct rte_eth_dev *dev)
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
int diag, i;
struct fm10k_macvlan_filter_info *macvlan;
@@ -2840,18 +2843,18 @@ eth_fm10k_dev_init(struct rte_eth_dev *dev)
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
- rte_eth_copy_pci_info(dev, dev->pci_dev);
+ rte_eth_copy_pci_info(dev, pci_dev);
macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
memset(macvlan, 0, sizeof(*macvlan));
/* Vendor and Device ID need to be set before init of shared code */
memset(hw, 0, sizeof(*hw));
- hw->device_id = dev->pci_dev->id.device_id;
- hw->vendor_id = dev->pci_dev->id.vendor_id;
- hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
- hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
+ hw->device_id = pci_dev->id.device_id;
+ hw->vendor_id = pci_dev->id.vendor_id;
+ hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
+ hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
hw->revision_id = 0;
- hw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;
+ hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
if (hw->hw_addr == NULL) {
PMD_INIT_LOG(ERR, "Bad mem resource."
" Try to blacklist unused devices.");
@@ -2921,20 +2924,20 @@ eth_fm10k_dev_init(struct rte_eth_dev *dev)
/*PF/VF has different interrupt handling mechanism */
if (hw->mac.type == fm10k_mac_pf) {
/* register callback func to eal lib */
- rte_intr_callback_register(&(dev->pci_dev->intr_handle),
+ rte_intr_callback_register(D2IH(dev),
fm10k_dev_interrupt_handler_pf, (void *)dev);
/* enable MISC interrupt */
fm10k_dev_enable_intr_pf(dev);
} else { /* VF */
- rte_intr_callback_register(&(dev->pci_dev->intr_handle),
+ rte_intr_callback_register(D2IH(dev),
fm10k_dev_interrupt_handler_vf, (void *)dev);
fm10k_dev_enable_intr_vf(dev);
}
/* Enable intr after callback registered */
- rte_intr_enable(&(dev->pci_dev->intr_handle));
+ rte_intr_enable(D2IH(dev));
hw->mac.ops.update_int_moderator(hw);
@@ -3004,7 +3007,7 @@ static int
eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
{
struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
-
+ struct rte_intr_handle *intr_handle = D2IH(dev);
PMD_INIT_FUNC_TRACE();
/* only uninitialize in the primary process */
@@ -3019,7 +3022,7 @@ eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
dev->tx_pkt_burst = NULL;
/* disable uio/vfio intr */
- rte_intr_disable(&(dev->pci_dev->intr_handle));
+ rte_intr_disable(intr_handle);
/*PF/VF has different interrupt handling mechanism */
if (hw->mac.type == fm10k_mac_pf) {
@@ -3027,13 +3030,13 @@ eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
fm10k_dev_disable_intr_pf(dev);
/* unregister callback func to eal lib */
- rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
+ rte_intr_callback_unregister(intr_handle,
fm10k_dev_interrupt_handler_pf, (void *)dev);
} else {
/* disable interrupt */
fm10k_dev_disable_intr_vf(dev);
- rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
+ rte_intr_callback_unregister(intr_handle,
fm10k_dev_interrupt_handler_vf, (void *)dev);
}
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 67778ba..8a63a8c 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -907,7 +907,7 @@ is_floating_veb_supported(struct rte_devargs *devargs)
static void
config_floating_veb(struct rte_eth_dev *dev)
{
- struct rte_pci_device *pci_dev = dev->pci_dev;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
@@ -952,7 +952,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
i40e_set_tx_function(dev);
return 0;
}
- pci_dev = dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(dev);
rte_eth_copy_pci_info(dev, pci_dev);
@@ -1215,7 +1215,7 @@ eth_i40e_dev_uninit(struct rte_eth_dev *dev)
return 0;
hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- pci_dev = dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(dev);
if (hw->adapter_stopped == 0)
i40e_dev_close(dev);
@@ -1335,7 +1335,7 @@ void
i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
{
struct rte_eth_dev *dev = vsi->adapter->eth_dev;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
uint16_t msix_vect = vsi->msix_intr;
uint16_t i;
@@ -1448,7 +1448,7 @@ void
i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
{
struct rte_eth_dev *dev = vsi->adapter->eth_dev;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
uint16_t msix_vect = vsi->msix_intr;
uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
@@ -1519,7 +1519,7 @@ static void
i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
{
struct rte_eth_dev *dev = vsi->adapter->eth_dev;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
uint16_t interval = i40e_calc_itr_interval(\
RTE_LIBRTE_I40E_ITR_INTERVAL);
@@ -1550,7 +1550,7 @@ static void
i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
{
struct rte_eth_dev *dev = vsi->adapter->eth_dev;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
uint16_t msix_intr, i;
@@ -1675,7 +1675,7 @@ i40e_dev_start(struct rte_eth_dev *dev)
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct i40e_vsi *main_vsi = pf->main_vsi;
int ret, i;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
uint32_t intr_vector = 0;
hw->adapter_stopped = 0;
@@ -1808,7 +1808,7 @@ i40e_dev_stop(struct rte_eth_dev *dev)
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_vsi *main_vsi = pf->main_vsi;
struct i40e_mirror_rule *p_mirror;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
int i;
/* Disable all queues */
@@ -1870,7 +1870,7 @@ i40e_dev_close(struct rte_eth_dev *dev)
/* Disable interrupt */
i40e_pf_disable_irq0(hw);
- rte_intr_disable(&(dev->pci_dev->intr_handle));
+ rte_intr_disable(ETH_DEV_TO_INTR_HANDLE(dev));
/* shutdown and destroy the HMC */
i40e_shutdown_lan_hmc(hw);
@@ -2588,7 +2588,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
dev_info->max_mac_addrs = vsi->max_macaddrs;
- dev_info->max_vfs = dev->pci_dev->max_vfs;
+ dev_info->max_vfs = ETH_DEV_PCI_DEV(dev)->max_vfs;
dev_info->rx_offload_capa =
DEV_RX_OFFLOAD_VLAN_STRIP |
DEV_RX_OFFLOAD_QINQ_STRIP |
@@ -3488,11 +3488,12 @@ i40e_get_cap(struct i40e_hw *hw)
static int
i40e_pf_parameter_init(struct rte_eth_dev *dev)
{
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct i40e_hw *hw = I40E_PF_TO_HW(pf);
uint16_t qp_count = 0, vsi_count = 0;
- if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
+ if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
return -EINVAL;
}
@@ -3533,10 +3534,10 @@ i40e_pf_parameter_init(struct rte_eth_dev *dev)
/* VF queue/VSI allocation */
pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
- if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
+ if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
pf->flags |= I40E_FLAG_SRIOV;
pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
- pf->vf_num = dev->pci_dev->max_vfs;
+ pf->vf_num = pci_dev->max_vfs;
PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
"in total %u queues", pf->vf_num, pf->vf_nb_qps,
pf->vf_nb_qps * pf->vf_num);
@@ -5573,7 +5574,7 @@ i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
done:
/* Enable interrupt */
i40e_pf_enable_irq0(hw);
- rte_intr_enable(&(dev->pci_dev->intr_handle));
+ rte_intr_enable(ETH_DEV_TO_INTR_HANDLE(dev));
}
static int
@@ -8124,10 +8125,11 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
static void
i40e_enable_extended_tag(struct rte_eth_dev *dev)
{
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
uint32_t buf = 0;
int ret;
- ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
+ ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
PCI_DEV_CAP_REG);
if (ret < 0) {
PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
@@ -8140,7 +8142,7 @@ i40e_enable_extended_tag(struct rte_eth_dev *dev)
}
buf = 0;
- ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
+ ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
PCI_DEV_CTRL_REG);
if (ret < 0) {
PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
@@ -8152,7 +8154,7 @@ i40e_enable_extended_tag(struct rte_eth_dev *dev)
return;
}
buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
- ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
+ ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
PCI_DEV_CTRL_REG);
if (ret < 0) {
PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
@@ -9555,7 +9557,7 @@ i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
static int
i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t interval =
i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
@@ -9580,7 +9582,7 @@ i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
I40E_WRITE_FLUSH(hw);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(ETH_DEV_TO_INTR_HANDLE(dev));
return 0;
}
@@ -9588,7 +9590,7 @@ i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
static int
i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
{
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t msix_intr;
diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h
index 298cef4..9d4bea7 100644
--- a/drivers/net/i40e/i40e_ethdev.h
+++ b/drivers/net/i40e/i40e_ethdev.h
@@ -671,6 +671,10 @@ i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
#define I40E_VF_TO_HW(vf) \
(&(((struct i40e_vf *)vf)->adapter->hw))
+/* ETH_DEV_TO_INTR_HANDLE */
+#define ETH_DEV_TO_INTR_HANDLE(ptr) \
+ (&(ETH_DEV_PCI_DEV(ptr)->intr_handle))
+
static inline void
i40e_init_adminq_parameter(struct i40e_hw *hw)
{
diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
index aa306d6..781e658 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -718,7 +718,7 @@ i40evf_config_irq_map(struct rte_eth_dev *dev)
uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
sizeof(struct i40e_virtchnl_vector_map)];
struct i40e_virtchnl_irq_map_info *map_info;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
uint32_t vector_id;
int i, err;
@@ -1431,7 +1431,7 @@ i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
done:
i40evf_enable_irq0(hw);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(ETH_DEV_TO_INTR_HANDLE(dev));
}
static int
@@ -1439,7 +1439,7 @@ i40evf_dev_init(struct rte_eth_dev *eth_dev)
{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
eth_dev->data->dev_private);
- struct rte_pci_device *pci_dev = eth_dev->pci_dev;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(eth_dev);
PMD_INIT_FUNC_TRACE();
@@ -1458,15 +1458,15 @@ i40evf_dev_init(struct rte_eth_dev *eth_dev)
return 0;
}
- rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
+ rte_eth_copy_pci_info(eth_dev, pci_dev);
- hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
- hw->device_id = eth_dev->pci_dev->id.device_id;
- hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
- hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
- hw->bus.device = eth_dev->pci_dev->addr.devid;
- hw->bus.func = eth_dev->pci_dev->addr.function;
- hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
+ hw->vendor_id = pci_dev->id.vendor_id;
+ hw->device_id = pci_dev->id.device_id;
+ hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
+ hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
+ hw->bus.device = pci_dev->addr.devid;
+ hw->bus.func = pci_dev->addr.function;
+ hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
hw->adapter_stopped = 0;
if(i40evf_init_vf(eth_dev) != 0) {
@@ -1853,7 +1853,7 @@ i40evf_enable_queues_intr(struct rte_eth_dev *dev)
{
struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
if (!rte_intr_allow_others(intr_handle)) {
I40E_WRITE_REG(hw,
@@ -1885,7 +1885,7 @@ i40evf_disable_queues_intr(struct rte_eth_dev *dev)
{
struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
if (!rte_intr_allow_others(intr_handle)) {
I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
@@ -1911,7 +1911,7 @@ i40evf_disable_queues_intr(struct rte_eth_dev *dev)
static int
i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t interval =
i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
@@ -1937,7 +1937,7 @@ i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
I40EVF_WRITE_FLUSH(hw);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(ETH_DEV_TO_INTR_HANDLE(dev));
return 0;
}
@@ -1945,7 +1945,7 @@ i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
static int
i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
{
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint16_t msix_intr;
@@ -2025,7 +2025,7 @@ i40evf_dev_start(struct rte_eth_dev *dev)
{
struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
uint32_t intr_vector = 0;
PMD_INIT_FUNC_TRACE();
@@ -2090,7 +2090,7 @@ i40evf_dev_start(struct rte_eth_dev *dev)
static void
i40evf_dev_stop(struct rte_eth_dev *dev)
{
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
PMD_INIT_FUNC_TRACE();
@@ -2285,7 +2285,7 @@ static void
i40evf_dev_close(struct rte_eth_dev *dev)
{
struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_pci_device *pci_dev = dev->pci_dev;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
i40evf_dev_stop(dev);
hw->adapter_stopped = 1;
diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index edc9b22..f17da46 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -427,6 +427,9 @@ static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
(r) = (h)->bitmap[idx] >> bit & 1;\
} while (0)
+#define ETH_DEV_TO_INTR_HANDLE(ptr) \
+ (&(ETH_DEV_PCI_DEV(ptr)->intr_handle))
+
/*
* The set of PCI devices this driver supports
*/
@@ -1127,7 +1130,7 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
return 0;
}
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
rte_eth_copy_pci_info(eth_dev, pci_dev);
@@ -1302,7 +1305,7 @@ eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
return -EPERM;
hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
if (hw->adapter_stopped == 0)
ixgbe_dev_close(eth_dev);
@@ -1419,7 +1422,7 @@ eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
return 0;
}
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
rte_eth_copy_pci_info(eth_dev, pci_dev);
@@ -1532,7 +1535,9 @@ static int
eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
{
struct ixgbe_hw *hw;
- struct rte_pci_device *pci_dev = eth_dev->pci_dev;
+ struct rte_pci_device *pci_dev;
+
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
PMD_INIT_FUNC_TRACE();
@@ -1960,7 +1965,8 @@ ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
}
RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
- RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
+ RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
+ ETH_DEV_PCI_DEV(dev)->max_vfs * nb_rx_q;
return 0;
}
@@ -2191,7 +2197,8 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct ixgbe_vf_info *vfinfo =
*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
uint32_t intr_vector = 0;
int err, link_up = 0, negotiate = 0;
uint32_t speed = 0;
@@ -2291,7 +2298,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev)
/* Restore vf rate limit */
if (vfinfo != NULL) {
- for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
+ for (vf = 0; vf < pci_dev->max_vfs; vf++)
for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
if (vfinfo[vf].tx_rate[idx] != 0)
ixgbe_set_vf_rate_limit(dev, vf,
@@ -2408,7 +2415,8 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
struct ixgbe_filter_info *filter_info =
IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
int vf;
PMD_INIT_FUNC_TRACE();
@@ -2424,7 +2432,7 @@ ixgbe_dev_stop(struct rte_eth_dev *dev)
ixgbe_stop_adapter(hw);
for (vf = 0; vfinfo != NULL &&
- vf < dev->pci_dev->max_vfs; vf++)
+ vf < pci_dev->max_vfs; vf++)
vfinfo[vf].clear_to_send = false;
if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
@@ -3033,6 +3041,7 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
{
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
@@ -3049,7 +3058,7 @@ ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
dev_info->max_mac_addrs = hw->mac.num_rar_entries;
dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
- dev_info->max_vfs = dev->pci_dev->max_vfs;
+ dev_info->max_vfs = pci_dev->max_vfs;
if (hw->mac.type == ixgbe_mac_82598EB)
dev_info->max_vmdq_pools = ETH_16_POOLS;
else
@@ -3164,6 +3173,7 @@ ixgbevf_dev_info_get(struct rte_eth_dev *dev,
struct rte_eth_dev_info *dev_info)
{
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
@@ -3171,7 +3181,7 @@ ixgbevf_dev_info_get(struct rte_eth_dev *dev,
dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
dev_info->max_mac_addrs = hw->mac.num_rar_entries;
dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
- dev_info->max_vfs = dev->pci_dev->max_vfs;
+ dev_info->max_vfs = pci_dev->max_vfs;
if (hw->mac.type == ixgbe_mac_82598EB)
dev_info->max_vmdq_pools = ETH_16_POOLS;
else
@@ -3434,6 +3444,7 @@ static void
ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
{
struct rte_eth_link link;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
memset(&link, 0, sizeof(link));
rte_ixgbe_dev_atomic_read_link_status(dev, &link);
@@ -3448,10 +3459,10 @@ ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
(int)(dev->data->port_id));
}
PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
- dev->pci_dev->addr.domain,
- dev->pci_dev->addr.bus,
- dev->pci_dev->addr.devid,
- dev->pci_dev->addr.function);
+ pci_dev->addr.domain,
+ pci_dev->addr.bus,
+ pci_dev->addr.devid,
+ pci_dev->addr.function);
}
/*
@@ -3515,7 +3526,7 @@ ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
} else {
PMD_DRV_LOG(DEBUG, "enable intr immediately");
ixgbe_enable_intr(dev);
- rte_intr_enable(&(dev->pci_dev->intr_handle));
+ rte_intr_enable(ETH_DEV_TO_INTR_HANDLE(dev));
}
@@ -3564,7 +3575,7 @@ ixgbe_dev_interrupt_delayed_handler(void *param)
PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
ixgbe_enable_intr(dev);
- rte_intr_enable(&(dev->pci_dev->intr_handle));
+ rte_intr_enable(ETH_DEV_TO_INTR_HANDLE(dev));
}
/**
@@ -4196,7 +4207,7 @@ ixgbevf_dev_start(struct rte_eth_dev *dev)
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t intr_vector = 0;
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
int err, mask = 0;
@@ -4259,7 +4270,7 @@ static void
ixgbevf_dev_stop(struct rte_eth_dev *dev)
{
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
PMD_INIT_FUNC_TRACE();
@@ -5070,7 +5081,7 @@ ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
RTE_SET_USED(queue_id);
IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(ETH_DEV_TO_INTR_HANDLE(dev));
return 0;
}
@@ -5112,7 +5123,7 @@ ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
mask &= (1 << (queue_id - 32));
IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
}
- rte_intr_enable(&dev->pci_dev->intr_handle);
+ rte_intr_enable(ETH_DEV_TO_INTR_HANDLE(dev));
return 0;
}
@@ -5216,7 +5227,7 @@ ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
static void
ixgbevf_configure_msix(struct rte_eth_dev *dev)
{
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t q_idx;
@@ -5249,7 +5260,7 @@ ixgbevf_configure_msix(struct rte_eth_dev *dev)
static void
ixgbe_configure_msix(struct rte_eth_dev *dev)
{
- struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
+ struct rte_intr_handle *intr_handle = ETH_DEV_TO_INTR_HANDLE(dev);
struct ixgbe_hw *hw =
IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
@@ -5381,7 +5392,8 @@ static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
return -EINVAL;
if (vfinfo != NULL) {
- for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
+ for (vf_idx = 0; vf_idx < ETH_DEV_PCI_DEV(dev)->max_vfs;
+ vf_idx++) {
if (vf_idx == vf)
continue;
for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
@@ -7197,12 +7209,13 @@ ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
int ret = 0;
uint32_t vmtir, vmvir;
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(dev);
- if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
+ if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
PMD_DRV_LOG(ERR,
"VF id %u should be less than %u",
l2_tunnel->vf_id,
- dev->pci_dev->max_vfs);
+ pci_dev->max_vfs);
return -EINVAL;
}
diff --git a/drivers/net/ixgbe/ixgbe_pf.c b/drivers/net/ixgbe/ixgbe_pf.c
index 26395e4..139d816 100644
--- a/drivers/net/ixgbe/ixgbe_pf.c
+++ b/drivers/net/ixgbe/ixgbe_pf.c
@@ -61,7 +61,7 @@
static inline uint16_t
dev_num_vf(struct rte_eth_dev *eth_dev)
{
- return eth_dev->pci_dev->max_vfs;
+ return ETH_DEV_PCI_DEV(eth_dev)->max_vfs;
}
static inline
diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c
index d106dd0..959ff0f 100644
--- a/drivers/net/qede/qede_ethdev.c
+++ b/drivers/net/qede/qede_ethdev.c
@@ -178,11 +178,12 @@ static void
qede_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param)
{
struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(eth_dev);
struct qede_dev *qdev = eth_dev->data->dev_private;
struct ecore_dev *edev = &qdev->edev;
qede_interrupt_action(ECORE_LEADING_HWFN(edev));
- if (rte_intr_enable(ð_dev->pci_dev->intr_handle))
+ if (rte_intr_enable(&pci_dev->intr_handle))
DP_ERR(edev, "rte_intr_enable failed\n");
}
@@ -809,6 +810,7 @@ static void qede_poll_sp_sb_cb(void *param)
static void qede_dev_close(struct rte_eth_dev *eth_dev)
{
+ struct rte_pci_device *pci_dev = ETH_DEV_PCI_DEV(eth_dev);
struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
int rc;
@@ -835,9 +837,9 @@ static void qede_dev_close(struct rte_eth_dev *eth_dev)
qdev->ops->common->remove(edev);
- rte_intr_disable(ð_dev->pci_dev->intr_handle);
+ rte_intr_disable(&pci_dev->intr_handle);
- rte_intr_callback_unregister(ð_dev->pci_dev->intr_handle,
+ rte_intr_callback_unregister(&pci_dev->intr_handle,
qede_interrupt_handler, (void *)eth_dev);
if (edev->num_hwfns > 1)
@@ -1403,7 +1405,8 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
/* Extract key data structures */
adapter = eth_dev->data->dev_private;
edev = &adapter->edev;
- pci_addr = eth_dev->pci_dev->addr;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
+ pci_addr = pci_dev->addr;
PMD_INIT_FUNC_TRACE(edev);
@@ -1420,8 +1423,6 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
return 0;
}
- pci_dev = eth_dev->pci_dev;
-
rte_eth_copy_pci_info(eth_dev, pci_dev);
qed_ops = qed_get_eth_ops();
@@ -1442,10 +1443,10 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
qede_update_pf_params(edev);
- rte_intr_callback_register(ð_dev->pci_dev->intr_handle,
+ rte_intr_callback_register(&pci_dev->intr_handle,
qede_interrupt_handler, (void *)eth_dev);
- if (rte_intr_enable(ð_dev->pci_dev->intr_handle)) {
+ if (rte_intr_enable(&pci_dev->intr_handle)) {
DP_ERR(edev, "rte_intr_enable() failed\n");
return -ENODEV;
}
diff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c
index 8bb13e5..bcb3751 100644
--- a/drivers/net/vmxnet3/vmxnet3_ethdev.c
+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c
@@ -138,7 +138,7 @@ gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
const struct rte_memzone *mz;
snprintf(z_name, sizeof(z_name), "%s_%d_%s",
- dev->driver->pci_drv.driver.name, dev->data->port_id, post_string);
+ dev->data->drv_name, dev->data->port_id, post_string);
mz = rte_memzone_lookup(z_name);
if (!reuse) {
@@ -237,7 +237,7 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
- pci_dev = eth_dev->pci_dev;
+ pci_dev = ETH_DEV_PCI_DEV(eth_dev);
/*
* for secondary processes, we don't initialize any further as primary
--
2.7.4
^ permalink raw reply related
* [PATCH 4/7] virtio: Don't fill dev_info->driver_name
From: Jan Blunck @ 2016-11-20 10:05 UTC (permalink / raw)
To: dev; +Cc: shreyansh.jain
In-Reply-To: <1479636327-4166-1-git-send-email-jblunck@infradead.org>
This is overwritten in rte_eth_dev_info_get().
Signed-off-by: Jan Blunck <jblunck@infradead.org>
---
drivers/net/virtio/virtio_ethdev.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c
index 079fd6c..741688e 100644
--- a/drivers/net/virtio/virtio_ethdev.c
+++ b/drivers/net/virtio/virtio_ethdev.c
@@ -1624,10 +1624,6 @@ virtio_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
uint64_t tso_mask;
struct virtio_hw *hw = dev->data->dev_private;
- if (dev->pci_dev)
- dev_info->driver_name = dev->driver->pci_drv.driver.name;
- else
- dev_info->driver_name = "virtio_user PMD";
dev_info->max_rx_queues =
RTE_MIN(hw->max_queue_pairs, VIRTIO_MAX_RX_QUEUES);
dev_info->max_tx_queues =
--
2.7.4
^ permalink raw reply related
* [PATCH 5/7] virtio: Add vtpci_intr_handle() helper to get rte_intr_handle
From: Jan Blunck @ 2016-11-20 10:05 UTC (permalink / raw)
To: dev; +Cc: shreyansh.jain
In-Reply-To: <1479636327-4166-1-git-send-email-jblunck@infradead.org>
This adds a helper to get the rte_intr_handle from the virtio_hw. This is
safe to do since the usage of the helper is guarded by RTE_ETH_DEV_INTR_LSC
which is only set if we found a PCI device during initialization.
Signed-off-by: Jan Blunck <jblunck@infradead.org>
---
drivers/net/virtio/virtio_ethdev.c | 12 +++++++-----
drivers/net/virtio/virtio_pci.h | 6 ++++++
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c
index 741688e..da9668e 100644
--- a/drivers/net/virtio/virtio_ethdev.c
+++ b/drivers/net/virtio/virtio_ethdev.c
@@ -1162,7 +1162,7 @@ virtio_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
isr = vtpci_isr(hw);
PMD_DRV_LOG(INFO, "interrupt status = %#x", isr);
- if (rte_intr_enable(&dev->pci_dev->intr_handle) < 0)
+ if (rte_intr_enable(vtpci_intr_handle(hw)) < 0)
PMD_DRV_LOG(ERR, "interrupt enable failed");
if (isr & VIRTIO_PCI_ISR_CONFIG) {
@@ -1334,7 +1334,7 @@ eth_virtio_dev_init(struct rte_eth_dev *eth_dev)
/* Setup interrupt callback */
if (eth_dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
- rte_intr_callback_register(&pci_dev->intr_handle,
+ rte_intr_callback_register(vtpci_intr_handle(hw),
virtio_interrupt_handler, eth_dev);
return 0;
@@ -1344,6 +1344,7 @@ static int
eth_virtio_dev_uninit(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev;
+ struct virtio_hw *hw = eth_dev->data->dev_private;
PMD_INIT_FUNC_TRACE();
@@ -1363,7 +1364,7 @@ eth_virtio_dev_uninit(struct rte_eth_dev *eth_dev)
/* reset interrupt callback */
if (eth_dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
- rte_intr_callback_unregister(&pci_dev->intr_handle,
+ rte_intr_callback_unregister(vtpci_intr_handle(hw),
virtio_interrupt_handler,
eth_dev);
rte_eal_pci_unmap_device(pci_dev);
@@ -1481,7 +1482,7 @@ virtio_dev_start(struct rte_eth_dev *dev)
return -ENOTSUP;
}
- if (rte_intr_enable(&dev->pci_dev->intr_handle) < 0) {
+ if (rte_intr_enable(vtpci_intr_handle(hw)) < 0) {
PMD_DRV_LOG(ERR, "interrupt enable failed");
return -EIO;
}
@@ -1573,12 +1574,13 @@ static void virtio_dev_free_mbufs(struct rte_eth_dev *dev)
static void
virtio_dev_stop(struct rte_eth_dev *dev)
{
+ struct virtio_hw *hw = dev->data->dev_private;
struct rte_eth_link link;
PMD_INIT_LOG(DEBUG, "stop");
if (dev->data->dev_conf.intr_conf.lsc)
- rte_intr_disable(&dev->pci_dev->intr_handle);
+ rte_intr_disable(vtpci_intr_handle(hw));
memset(&link, 0, sizeof(link));
virtio_dev_atomic_write_link_status(dev, &link);
diff --git a/drivers/net/virtio/virtio_pci.h b/drivers/net/virtio/virtio_pci.h
index de271bf..5373e39 100644
--- a/drivers/net/virtio/virtio_pci.h
+++ b/drivers/net/virtio/virtio_pci.h
@@ -317,4 +317,10 @@ uint8_t vtpci_isr(struct virtio_hw *);
uint16_t vtpci_irq_config(struct virtio_hw *, uint16_t);
+static inline struct rte_intr_handle *
+vtpci_intr_handle(struct virtio_hw *hw)
+{
+ return hw->dev ? &hw->dev->intr_handle : NULL;
+}
+
#endif /* _VIRTIO_PCI_H_ */
--
2.7.4
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