* [PATCH 2/3] crypto/qat: add DES capability to Intel QAT driver
From: Arek Kusztal @ 2016-12-02 14:16 UTC (permalink / raw)
To: dev
Cc: fiona.trahe, pablo.de.lara.guarch, john.griffin, deepak.k.jain,
Arek Kusztal
In-Reply-To: <1480688162-27474-1-git-send-email-arkadiuszx.kusztal@intel.com>
This commit adds DES capability to Intel QuickAssist
Technology Driver
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
doc/guides/cryptodevs/qat.rst | 1 +
doc/guides/rel_notes/release_17_02.rst | 6 +++++
drivers/crypto/qat/qat_adf/qat_algs.h | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 16 +++++++++++++
drivers/crypto/qat/qat_crypto.c | 29 +++++++++++++++++++++++-
5 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 607d244..3e97403 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -54,6 +54,7 @@ Cipher algorithms:
* ``RTE_CRYPTO_CIPHER_AES_GCM``
* ``RTE_CRYPTO_CIPHER_NULL``
* ``RTE_CRYPTO_CIPHER_KASUMI_F8``
+* ``RTE_CRYPTO_CIPHER_DES_CBC``
Hash algorithms:
diff --git a/doc/guides/rel_notes/release_17_02.rst b/doc/guides/rel_notes/release_17_02.rst
index 3b65038..8fd67ab 100644
--- a/doc/guides/rel_notes/release_17_02.rst
+++ b/doc/guides/rel_notes/release_17_02.rst
@@ -38,6 +38,12 @@ New Features
Also, make sure to start the actual text at the margin.
=========================================================
+* **Updated the QAT PMD.**
+
+ The QAT PMD was updated with additional support for:
+
+ * DES algorithm.
+
Resolved Issues
---------------
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h
index dcc0df5..5409e1e 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -144,4 +144,5 @@ int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
+int qat_alg_validate_des_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
#endif
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index f4e24b3..fbeef0a 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -518,6 +518,10 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
total_key_size = ICP_QAT_HW_3DES_KEY_SZ;
cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_3DES_BLK_SZ >> 3;
proto = ICP_QAT_FW_LA_PROTO_GET(header->serv_specif_flags);
+ } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_DES) {
+ total_key_size = ICP_QAT_HW_DES_KEY_SZ;
+ cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_DES_BLK_SZ >> 3;
+ proto = ICP_QAT_FW_LA_PROTO_GET(header->serv_specif_flags);
} else {
total_key_size = cipherkeylen;
cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
@@ -858,6 +862,18 @@ int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
return 0;
}
+int qat_alg_validate_des_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
+{
+ switch (key_len) {
+ case ICP_QAT_HW_DES_KEY_SZ:
+ *alg = ICP_QAT_HW_CIPHER_ALGO_DES;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
{
switch (key_len) {
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 6a6bd2e..4ee1ef8 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -496,6 +496,26 @@ static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
}, }
}, }
},
+ { /* DES CBC */
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+ {.sym = {
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+ {.cipher = {
+ .algo = RTE_CRYPTO_CIPHER_DES_CBC,
+ .block_size = 8,
+ .key_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ },
+ .iv_size = {
+ .min = 8,
+ .max = 8,
+ .increment = 0
+ }
+ }, }
+ }, }
+ },
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
@@ -637,6 +657,14 @@ qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
}
session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
break;
+ case RTE_CRYPTO_CIPHER_DES_CBC:
+ if (qat_alg_validate_des_key(cipher_xform->key.length,
+ &session->qat_cipher_alg) != 0) {
+ PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
+ goto error_out;
+ }
+ session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
+ break;
case RTE_CRYPTO_CIPHER_3DES_CTR:
if (qat_alg_validate_3des_key(cipher_xform->key.length,
&session->qat_cipher_alg) != 0) {
@@ -839,7 +867,6 @@ unsigned qat_crypto_sym_get_session_private_size(
return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
}
-
uint16_t
qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
uint16_t nb_ops)
--
2.1.0
^ permalink raw reply related
* [PATCH 1/3] lib/librte_cryptodev: add DES CBC cipher algorithm
From: Arek Kusztal @ 2016-12-02 14:16 UTC (permalink / raw)
To: dev
Cc: fiona.trahe, pablo.de.lara.guarch, john.griffin, deepak.k.jain,
Arek Kusztal
In-Reply-To: <1480688162-27474-1-git-send-email-arkadiuszx.kusztal@intel.com>
This commit adds DES CBC ciper algorithm to available algorithms
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
lib/librte_cryptodev/rte_crypto_sym.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/lib/librte_cryptodev/rte_crypto_sym.h b/lib/librte_cryptodev/rte_crypto_sym.h
index d694723..0e20b30 100644
--- a/lib/librte_cryptodev/rte_crypto_sym.h
+++ b/lib/librte_cryptodev/rte_crypto_sym.h
@@ -105,7 +105,11 @@ enum rte_crypto_cipher_algorithm {
RTE_CRYPTO_CIPHER_ZUC_EEA3,
/**< ZUC algorithm in EEA3 mode */
+ RTE_CRYPTO_CIPHER_DES_CBC,
+ /**< DES algorithm in CBC mode */
+
RTE_CRYPTO_CIPHER_LIST_END
+
};
/** Symmetric Cipher Direction */
--
2.1.0
^ permalink raw reply related
* [PATCH 0/3] Add DES capability to Intel QuickAssist Technology driver
From: Arek Kusztal @ 2016-12-02 14:15 UTC (permalink / raw)
To: dev
Cc: fiona.trahe, pablo.de.lara.guarch, john.griffin, deepak.k.jain,
Arek Kusztal
This patchset adds Data Encryption Standard (DES) capability to Intel QuickAssist
Technology driver and corresponding tests to test files.
Arek Kusztal (3):
lib/librte_cryptodev: add DES CBC cipher algorithm
crypto/qat: add DES capability to Intel QAT driver
app/test: add DES tests to Intel QAT crypto test suite
app/test/test_cryptodev.c | 18 ++++
app/test/test_cryptodev_blockcipher.c | 5 ++
app/test/test_cryptodev_blockcipher.h | 3 +-
app/test/test_cryptodev_des_test_vectors.h | 110 +++++++++++++++++++++++
doc/guides/cryptodevs/qat.rst | 1 +
doc/guides/rel_notes/release_17_02.rst | 6 ++
drivers/crypto/qat/qat_adf/qat_algs.h | 1 +
drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 16 ++++
drivers/crypto/qat/qat_crypto.c | 29 +++++-
lib/librte_cryptodev/rte_crypto_sym.h | 4 +
10 files changed, 191 insertions(+), 2 deletions(-)
--
2.1.0
^ permalink raw reply
* [PATCH] Scheduler: add driver for scheduler crypto pmd
From: Fan Zhang @ 2016-12-02 14:15 UTC (permalink / raw)
To: dev; +Cc: declan.doherty, roy.fan.zhang
This patch provides the initial implementation of the scheduler poll mode
driver using DPDK cryptodev framework.
Scheduler PMD is used to schedule and enqueue the crypto ops to the
hardware and/or software crypto devices attached to it (slaves). The
dequeue operation from the slave(s), and the possible dequeued crypto op
reordering, are then carried out by the scheduler.
The scheduler PMD can be used to fill the throughput gap between the
physical core and the existing cryptodevs to increase the overall
performance. For example, if a physical core has higher crypto op
processing rate than a cryptodev, the scheduler PMD can be introduced to
attach more than one cryptodevs.
This initial implementation is limited to supporting the following
scheduling modes:
- CRYPTO_SCHED_SW_ROUND_ROBIN_MODE (round robin amongst attached software
slave cryptodevs, to set this mode, the scheduler should have been
attached 1 or more software cryptodevs.
- CRYPTO_SCHED_HW_ROUND_ROBIN_MODE (round robin amongst attached hardware
slave cryptodevs (QAT), to set this mode, the scheduler should have
been attached 1 or more QATs.
Build instructions:
To build DPDK with CRYTPO_SCHEDULER_PMD the user is required to set
CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y in config/common_base
Notice:
Scheduler PMD shares same EAL commandline options as other cryptodevs.
In addition, one extra option "enable_reorder" exists. When it is set to
"yes", the dequeued crypto op reorder will take place. This feature can
be disabled by filling "no" in the "enable_reorder" option. For example,
the following EAL commandline fragment creates a scheduler PMD with
crypto op reordering feature enabled:
... --vdev "crypto_scheduler_pmd,enable_reorder=yes" ...
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
---
config/common_base | 6 +
drivers/crypto/Makefile | 1 +
drivers/crypto/scheduler/Makefile | 64 +++
drivers/crypto/scheduler/rte_cryptodev_scheduler.c | 387 +++++++++++++++++
drivers/crypto/scheduler/rte_cryptodev_scheduler.h | 90 ++++
.../scheduler/rte_pmd_crypto_scheduler_version.map | 8 +
drivers/crypto/scheduler/scheduler_pmd.c | 475 +++++++++++++++++++++
drivers/crypto/scheduler/scheduler_pmd_ops.c | 335 +++++++++++++++
drivers/crypto/scheduler/scheduler_pmd_private.h | 137 ++++++
lib/librte_cryptodev/rte_cryptodev.h | 2 +
mk/rte.app.mk | 3 +-
11 files changed, 1507 insertions(+), 1 deletion(-)
create mode 100644 drivers/crypto/scheduler/Makefile
create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.c
create mode 100644 drivers/crypto/scheduler/rte_cryptodev_scheduler.h
create mode 100644 drivers/crypto/scheduler/rte_pmd_crypto_scheduler_version.map
create mode 100644 drivers/crypto/scheduler/scheduler_pmd.c
create mode 100644 drivers/crypto/scheduler/scheduler_pmd_ops.c
create mode 100644 drivers/crypto/scheduler/scheduler_pmd_private.h
diff --git a/config/common_base b/config/common_base
index 4bff83a..79d120d 100644
--- a/config/common_base
+++ b/config/common_base
@@ -400,6 +400,12 @@ CONFIG_RTE_LIBRTE_PMD_KASUMI=n
CONFIG_RTE_LIBRTE_PMD_KASUMI_DEBUG=n
#
+# Compile PMD for Crypto Scheduler device
+#
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=n
+CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n
+
+#
# Compile PMD for ZUC device
#
CONFIG_RTE_LIBRTE_PMD_ZUC=n
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 745c614..cdd3c94 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -38,6 +38,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat
DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
DIRS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += kasumi
DIRS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += zuc
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
DIRS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += null
include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/crypto/scheduler/Makefile b/drivers/crypto/scheduler/Makefile
new file mode 100644
index 0000000..d8e1ff5
--- /dev/null
+++ b/drivers/crypto/scheduler/Makefile
@@ -0,0 +1,64 @@
+# BSD LICENSE
+#
+# Copyright(c) 2015 Intel Corporation. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of Intel Corporation nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_crypto_scheduler.a
+
+# build flags
+CFLAGS += -O3
+CFLAGS += $(WERROR_FLAGS)
+
+# library version
+LIBABIVER := 1
+
+# versioning export map
+EXPORT_MAP := rte_pmd_crypto_scheduler_version.map
+
+#
+# Export include files
+#
+SYMLINK-y-include += rte_cryptodev_scheduler.h
+
+# library source files
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler_pmd.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler_pmd_ops.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += rte_cryptodev_scheduler.c
+
+# library dependencies
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_eal
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_mbuf
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_mempool
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_ring
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_reorder
+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += lib/librte_cryptodev
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.c b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
new file mode 100644
index 0000000..e04596c
--- /dev/null
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.c
@@ -0,0 +1,387 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <rte_jhash.h>
+#include <rte_reorder.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_cryptodev_scheduler.h>
+
+#include "scheduler_pmd_private.h"
+
+static int
+request_qp(uint8_t dev_id) {
+ struct rte_cryptodev_info dev_info;
+ struct slave_info key = {dev_id, 0};
+ uint16_t i;
+
+ if (!dev_qp_map) {
+ struct rte_hash_parameters hash_param = {0};
+
+ hash_param.entries = 1024;
+ hash_param.key_len = sizeof(key);
+ hash_param.hash_func = rte_jhash;
+ hash_param.hash_func_init_val = 0;
+ hash_param.socket_id = SOCKET_ID_ANY;
+
+ dev_qp_map = rte_hash_create(&hash_param);
+ if (!dev_qp_map) {
+ CS_LOG_ERR("not enough memory to create hash table");
+ return -ENOMEM;
+ }
+ }
+
+ rte_cryptodev_info_get(dev_id, &dev_info);
+
+ for (i = 0; i < dev_info.max_nb_queue_pairs; i++) {
+ key.qp_id = i;
+
+ if (rte_hash_lookup_data(dev_qp_map, (void *)&key,
+ NULL) == 0)
+ continue;
+
+ if (rte_hash_add_key(dev_qp_map, &key) < 0) {
+ CS_LOG_ERR("not enough memory to insert hash "
+ "entry");
+ return -ENOMEM;
+ }
+
+ break;
+ }
+
+ if (i == dev_info.max_nb_queue_pairs) {
+ CS_LOG_ERR("all queue pairs of cdev %u has already been "
+ "occupied", dev_id);
+ return -1;
+ }
+
+ return i;
+}
+
+static int
+update_reorder_buff(uint8_t dev_id, struct scheduler_private *internal)
+{
+ char reorder_buff_name[32];
+ uint32_t reorder_buff_size = (internal->nb_slaves[SCHED_HW_CDEV] +
+ internal->nb_slaves[SCHED_SW_CDEV]) *
+ PER_SLAVE_BUFF_SIZE;
+
+ if (!internal->use_reorder)
+ return 0;
+
+ if (reorder_buff_size == 0) {
+ if (internal->reorder_buff)
+ rte_reorder_free(internal->reorder_buff);
+ internal->reorder_buff = NULL;
+ return 0;
+ }
+
+ if (internal->reorder_buff)
+ rte_reorder_free(internal->reorder_buff);
+
+ if (snprintf(reorder_buff_name, RTE_CRYPTODEV_NAME_MAX_LEN,
+ "%s_rb_%u", RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD),
+ dev_id) < 0) {
+ CS_LOG_ERR("failed to create unique reorder buffer name");
+ return -EFAULT;
+ }
+
+ internal->reorder_buff = rte_reorder_create(
+ reorder_buff_name, rte_socket_id(),
+ reorder_buff_size);
+
+ if (internal->reorder_buff == NULL) {
+ CS_LOG_ERR("failed to allocate reorder buffer");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/** update the scheduler pmd's capability with attaching device's
+ * capability.
+ * For each device to be attached, the scheduler's capability should be
+ * the common capability set of all slaves
+ **/
+static int
+update_sched_capabilities(struct scheduler_private *internal,
+ const struct rte_cryptodev_capabilities *attach_caps)
+{
+ struct rte_cryptodev_capabilities *cap;
+ const struct rte_cryptodev_capabilities *a_cap;
+ uint32_t nb_caps = 0;
+ uint32_t nb_attached_caps = 0, nb_common_caps;
+ uint32_t cap_size = sizeof(struct rte_cryptodev_capabilities);
+ uint32_t i;
+
+ /* find out how many caps the scheduler already has */
+ while (internal->capabilities[nb_attached_caps].op !=
+ RTE_CRYPTO_OP_TYPE_UNDEFINED)
+ nb_attached_caps++;
+
+ /* find out how many capabilities the cdev-to-be-attached has */
+ while (attach_caps[nb_caps].op != RTE_CRYPTO_OP_TYPE_UNDEFINED)
+ nb_caps++;
+
+ nb_common_caps = nb_attached_caps;
+
+ /* init, memcpy whole */
+ if (nb_attached_caps == 0) {
+ if (nb_caps > MAX_CAP_NUM) {
+ CS_LOG_ERR("too many capability items");
+ return -ENOMEM;
+ }
+
+ memset(internal->capabilities, 0, cap_size * MAX_CAP_NUM);
+
+ rte_memcpy(internal->capabilities, attach_caps,
+ cap_size * nb_caps);
+ return 0;
+ }
+
+
+ /* find common capabilities between slave-to-be-attached and self */
+ i = 0;
+
+ while (internal->capabilities[i].op != RTE_CRYPTO_OP_TYPE_UNDEFINED) {
+ cap = &internal->capabilities[i];
+ uint32_t j = 0;
+
+ while (attach_caps[j].op != RTE_CRYPTO_OP_TYPE_UNDEFINED) {
+ a_cap = &attach_caps[j];
+
+ if (a_cap->op != cap->op || a_cap->sym.xform_type !=
+ cap->sym.xform_type) {
+ j++;
+ continue;
+ }
+
+ if (a_cap->sym.xform_type == RTE_CRYPTO_SYM_XFORM_AUTH)
+ if (a_cap->sym.auth.algo !=
+ cap->sym.auth.algo) {
+ j++;
+ continue;
+ }
+
+ if (a_cap->sym.xform_type ==
+ RTE_CRYPTO_SYM_XFORM_CIPHER)
+ if (a_cap->sym.cipher.algo !=
+ cap->sym.cipher.algo) {
+ j++;
+ continue;
+ }
+
+ break;
+ }
+
+ if (j >= nb_attached_caps)
+ nb_common_caps--;
+
+ i++;
+ }
+
+ /* no common capabilities, quit */
+ if (nb_common_caps == 0) {
+ CS_LOG_ERR("incompatible capabilities");
+ return -1;
+ }
+
+ /* remove the capabilities of the scheduler not exist in the cdev*/
+ i = 0;
+ while (internal->capabilities[i].op != RTE_CRYPTO_OP_TYPE_UNDEFINED) {
+ cap = &internal->capabilities[i];
+ uint32_t j = 0;
+
+ while (attach_caps[j].op != RTE_CRYPTO_OP_TYPE_UNDEFINED) {
+ a_cap = &attach_caps[j];
+
+ if (a_cap->op != cap->op || a_cap->sym.xform_type !=
+ cap->sym.xform_type) {
+ j++;
+ continue;
+ }
+
+ if (a_cap->sym.xform_type ==
+ RTE_CRYPTO_SYM_XFORM_AUTH) {
+ if (a_cap->sym.auth.algo !=
+ cap->sym.auth.algo) {
+ j++;
+ continue;
+ }
+
+ /* update digest size of the scheduler,
+ * as AESNI-MB PMD only use truncated
+ * digest size.
+ */
+ cap->sym.auth.digest_size.min =
+ a_cap->sym.auth.digest_size.min <
+ cap->sym.auth.digest_size.min ?
+ a_cap->sym.auth.digest_size.min :
+ cap->sym.auth.digest_size.min;
+ cap->sym.auth.digest_size.max =
+ a_cap->sym.auth.digest_size.max <
+ cap->sym.auth.digest_size.max ?
+ a_cap->sym.auth.digest_size.max :
+ cap->sym.auth.digest_size.max;
+
+ break;
+ }
+
+ if (a_cap->sym.xform_type ==
+ RTE_CRYPTO_SYM_XFORM_CIPHER)
+ if (a_cap->sym.cipher.algo !=
+ cap->sym.cipher.algo) {
+ j++;
+ continue;
+ }
+
+ break;
+ }
+
+ if (j == nb_attached_caps) {
+ uint32_t k;
+
+ for (k = i + 1; k < nb_attached_caps; k++)
+ rte_memcpy(&internal->capabilities[k - 1],
+ &internal->capabilities[k], cap_size);
+
+ memset(&internal->capabilities[
+ nb_attached_caps], 0, cap_size);
+
+ nb_attached_caps--;
+ }
+
+ i++;
+ }
+
+ return 0;
+}
+
+/** Attach a device to the scheduler. */
+int
+rte_cryptodev_scheduler_attach_dev(uint8_t dev_id, uint8_t slave_dev_id)
+{
+ struct rte_cryptodev *dev = rte_cryptodev_pmd_get_dev(dev_id);
+ struct rte_cryptodev *slave_dev =
+ rte_cryptodev_pmd_get_dev(slave_dev_id);
+ struct scheduler_private *internal;
+ struct slave_info *slave;
+ struct rte_cryptodev_info dev_info;
+ uint8_t *idx;
+ int status;
+
+ if (dev->dev_type != RTE_CRYPTODEV_SCHEDULER_PMD) {
+ CS_LOG_ERR("Operation not supported");
+ return -ENOTSUP;
+ }
+
+ internal = (struct scheduler_private *)dev->data->dev_private;
+
+ rte_cryptodev_info_get(slave_dev_id, &dev_info);
+
+ if (dev_info.feature_flags & RTE_CRYPTODEV_FF_HW_ACCELERATED) {
+ idx = &internal->nb_slaves[SCHED_HW_CDEV];
+ slave = &internal->slaves[SCHED_HW_CDEV][*idx];
+ } else {
+ idx = &internal->nb_slaves[SCHED_SW_CDEV];
+ slave = &internal->slaves[SCHED_SW_CDEV][*idx];
+ }
+
+ if (*idx + 1 >= MAX_SLAVES_NUM) {
+ CS_LOG_ERR("too many devices attached");
+ return -ENOMEM;
+ }
+
+ if (update_sched_capabilities(internal, dev_info.capabilities) < 0) {
+ CS_LOG_ERR("capabilities update failed");
+ return -ENOTSUP;
+ }
+
+ slave->dev_id = slave_dev_id;
+ status = request_qp(slave_dev_id);
+ if (status < 0)
+ return -EFAULT;
+ slave->qp_id = (uint16_t)status;
+
+ internal->max_nb_sessions = dev_info.sym.max_nb_sessions <
+ internal->max_nb_sessions ?
+ dev_info.sym.max_nb_sessions : internal->max_nb_sessions;
+
+ dev->feature_flags |= slave_dev->feature_flags;
+
+ *idx += 1;
+
+ return update_reorder_buff(dev_id, internal);
+}
+
+
+int
+rte_crpytodev_scheduler_set_mode(uint8_t dev_id,
+ enum crypto_scheduling_mode mode)
+{
+ struct rte_cryptodev *dev = rte_cryptodev_pmd_get_dev(dev_id);
+ struct scheduler_private *internal = dev->data->dev_private;
+
+ if (mode < CRYPTO_SCHED_SW_ROUND_ROBIN_MODE ||
+ mode >= CRYPTO_SCHED_N_MODES)
+ return -1;
+
+ if (mode == CRYPTO_SCHED_SW_ROUND_ROBIN_MODE) {
+ if (internal->nb_slaves[SCHED_SW_CDEV] == 0)
+ return -1;
+ internal->use_dev_type = SCHED_SW_CDEV;
+ }
+
+ if (mode == CRYPTO_SCHED_HW_ROUND_ROBIN_MODE) {
+ if (internal->nb_slaves[SCHED_HW_CDEV] == 0)
+ return -1;
+ internal->use_dev_type = SCHED_HW_CDEV;
+ }
+
+ scheduler_update_rx_tx_ops(dev, mode, internal->use_reorder);
+
+ internal->mode = mode;
+
+ return 0;
+}
+
+void
+rte_crpytodev_scheduler_get_mode(uint8_t dev_id,
+ enum crypto_scheduling_mode *mode)
+{
+ struct rte_cryptodev *dev = rte_cryptodev_pmd_get_dev(dev_id);
+ struct scheduler_private *internal = dev->data->dev_private;
+
+ if (!mode)
+ return;
+
+ *mode = internal->mode;
+}
diff --git a/drivers/crypto/scheduler/rte_cryptodev_scheduler.h b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
new file mode 100644
index 0000000..5775037
--- /dev/null
+++ b/drivers/crypto/scheduler/rte_cryptodev_scheduler.h
@@ -0,0 +1,90 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_CRYPTO_SCHEDULER_H
+#define _RTE_CRYPTO_SCHEDULER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Crypto scheduler PMD operation modes
+ */
+enum crypto_scheduling_mode {
+ /* <Round Robin Mode amongst all software slave cdevs */
+ CRYPTO_SCHED_SW_ROUND_ROBIN_MODE = 1,
+ /* <Round Robin Mode amongst all hardware slave cdevs */
+ CRYPTO_SCHED_HW_ROUND_ROBIN_MODE,
+ CRYPTO_SCHED_N_MODES /* number of modes */
+};
+
+/**
+ * Attach a pre-configured crypto device to the scheduler
+ *
+ * @param dev_id The target scheduler device ID
+ * slave_dev_id crypto device ID to be attached
+ *
+ * @return
+ * 0 if attaching successful, negative int if otherwise.
+ */
+int
+rte_cryptodev_scheduler_attach_dev(uint8_t dev_id, uint8_t slave_dev_id);
+
+/**
+ * Set the scheduling mode
+ *
+ * @param dev_id The target scheduler device ID
+ * mode The scheduling mode
+ *
+ * @return
+ * 0 if attaching successful, negative integer if otherwise.
+ */
+int
+rte_crpytodev_scheduler_set_mode(uint8_t dev_id,
+ enum crypto_scheduling_mode mode);
+
+/**
+ * Get the current scheduling mode
+ *
+ * @param dev_id The target scheduler device ID
+ * mode Pointer to write the scheduling mode
+ */
+void
+rte_crpytodev_scheduler_get_mode(uint8_t dev_id,
+ enum crypto_scheduling_mode *mode);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _RTE_CRYPTO_SCHEDULER_H */
diff --git a/drivers/crypto/scheduler/rte_pmd_crypto_scheduler_version.map b/drivers/crypto/scheduler/rte_pmd_crypto_scheduler_version.map
new file mode 100644
index 0000000..dab1bfe
--- /dev/null
+++ b/drivers/crypto/scheduler/rte_pmd_crypto_scheduler_version.map
@@ -0,0 +1,8 @@
+DPDK_17.02 {
+ global:
+
+ rte_cryptodev_scheduler_attach_dev;
+ rte_crpytodev_scheduler_set_mode;
+ rte_crpytodev_scheduler_get_mode;
+
+} DPDK_17.02;
\ No newline at end of file
diff --git a/drivers/crypto/scheduler/scheduler_pmd.c b/drivers/crypto/scheduler/scheduler_pmd.c
new file mode 100644
index 0000000..37a8b64
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_pmd.c
@@ -0,0 +1,475 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <rte_common.h>
+#include <rte_hexdump.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_vdev.h>
+#include <rte_malloc.h>
+#include <rte_cpuflags.h>
+#include <rte_reorder.h>
+#include <rte_cryptodev_scheduler.h>
+
+#include "scheduler_pmd_private.h"
+
+#define SCHEDULER_MAX_NB_QP_ARG "max_nb_queue_pairs"
+#define SCHEDULER_MAX_NB_SESS_ARG "max_nb_sessions"
+#define SCHEDULER_SOCKET_ID "socket_id"
+#define SCHEDULER_ENABLE_REORDER_ARG "enable_reorder"
+
+const char *scheduler_vdev_valid_params[] = {
+ SCHEDULER_MAX_NB_QP_ARG,
+ SCHEDULER_MAX_NB_SESS_ARG,
+ SCHEDULER_SOCKET_ID,
+ SCHEDULER_ENABLE_REORDER_ARG,
+};
+
+/** Round robin mode burst enqueue */
+static uint16_t
+scheduler_enqueue_burst_rr(void *queue_pair,
+ struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+ uint16_t i, processed_ops;
+ struct scheduler_qp *qp = (struct scheduler_qp *)queue_pair;
+ struct scheduler_private *internal = qp->dev_priv;
+ struct scheduler_session *sess0, *sess1, *sess2, *sess3;
+ uint8_t dev_type_idx = internal->use_dev_type;
+ uint8_t dev_idx = internal->last_enq_idx[dev_type_idx];
+
+ for (i = 0; i < nb_ops && i < 4; i++)
+ rte_prefetch0(ops[i]->sym->session);
+
+ for (i = 0; i < nb_ops - 8; i += 4) {
+ sess0 = (struct scheduler_session *)
+ ops[i]->sym->session->_private;
+ sess1 = (struct scheduler_session *)
+ ops[i + 1]->sym->session->_private;
+ sess2 = (struct scheduler_session *)
+ ops[i + 2]->sym->session->_private;
+ sess3 = (struct scheduler_session *)
+ ops[i + 3]->sym->session->_private;
+
+ ops[i]->sym->session =
+ sess0->slave_sesses[dev_type_idx][dev_idx];
+ ops[i + 1]->sym->session =
+ sess1->slave_sesses[dev_type_idx][dev_idx];
+ ops[i + 2]->sym->session =
+ sess2->slave_sesses[dev_type_idx][dev_idx];
+ ops[i + 3]->sym->session =
+ sess3->slave_sesses[dev_type_idx][dev_idx];
+
+ rte_prefetch0(ops[i + 4]->sym->session);
+ rte_prefetch0(ops[i + 5]->sym->session);
+ rte_prefetch0(ops[i + 6]->sym->session);
+ rte_prefetch0(ops[i + 7]->sym->session);
+ }
+
+ for (; i < nb_ops; i++) {
+ sess0 = (struct scheduler_session *)
+ ops[i]->sym->session->_private;
+ ops[i]->sym->session =
+ sess0->slave_sesses[dev_type_idx][dev_idx];
+ }
+
+ processed_ops = rte_cryptodev_enqueue_burst(
+ internal->slaves[dev_type_idx][dev_idx].dev_id,
+ internal->slaves[dev_type_idx][dev_idx].qp_id,
+ ops, nb_ops);
+
+ internal->last_enq_idx[dev_type_idx] += 1;
+
+ if (unlikely(internal->last_enq_idx[dev_type_idx] >=
+ internal->nb_slaves[dev_type_idx]))
+ internal->last_enq_idx[dev_type_idx] = 0;
+
+ qp->stats.enqueued_count += processed_ops;
+
+ return processed_ops;
+}
+
+/** Round robin mode burst dequeue without post-reorder */
+static uint16_t
+scheduler_dequeue_burst_rr_no_reorder(void *queue_pair,
+ struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+ uint16_t nb_deq_ops;
+ struct scheduler_qp *qp = (struct scheduler_qp *)queue_pair;
+ struct scheduler_private *internal = qp->dev_priv;
+ uint8_t dev_type_idx = internal->use_dev_type;
+ uint8_t dev_idx = internal->last_deq_idx[dev_type_idx];
+
+ nb_deq_ops = rte_cryptodev_dequeue_burst(
+ internal->slaves[dev_type_idx][dev_idx].dev_id,
+ internal->slaves[dev_type_idx][dev_idx].qp_id,
+ ops, nb_ops);
+
+ internal->last_deq_idx[dev_type_idx] += 1;
+ if (unlikely(internal->last_deq_idx[dev_type_idx] >=
+ internal->nb_slaves[dev_type_idx]))
+ internal->last_deq_idx[dev_type_idx] = 0;
+
+ qp->stats.dequeued_count += nb_deq_ops;
+
+ return nb_deq_ops;
+}
+
+/** Round robin mode burst dequeue with post-reorder */
+static uint16_t
+scheduler_dequeue_burst_rr_reorder(void *queue_pair,
+ struct rte_crypto_op **ops, uint16_t nb_ops)
+{
+ uint16_t i, nb_deq_ops;
+ const uint16_t nb_op_ops = nb_ops;
+ struct scheduler_qp *qp = (struct scheduler_qp *)queue_pair;
+ struct scheduler_private *internal = qp->dev_priv;
+ struct rte_mbuf *reorder_mbufs[nb_op_ops];
+ struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;
+ struct rte_crypto_op *op_ops[nb_op_ops];
+ struct rte_reorder_buffer *reorder_buff =
+ (struct rte_reorder_buffer *)internal->reorder_buff;
+ uint8_t dev_type_idx = internal->use_dev_type;
+ uint8_t dev_idx = internal->last_deq_idx[dev_type_idx];
+
+ nb_deq_ops = rte_cryptodev_dequeue_burst(
+ internal->slaves[dev_type_idx][dev_idx].dev_id,
+ internal->slaves[dev_type_idx][dev_idx].qp_id,
+ op_ops, nb_ops);
+
+ internal->last_deq_idx[dev_type_idx] += 1;
+ if (unlikely(internal->last_deq_idx[dev_type_idx] >=
+ internal->nb_slaves[dev_type_idx]))
+ internal->last_deq_idx[dev_type_idx] = 0;
+
+ for (i = 0; i < nb_deq_ops && i < 4; i++)
+ rte_prefetch0(op_ops[i]->sym->m_src);
+
+ for (i = 0; i < nb_deq_ops - 8; i += 4) {
+ mbuf0 = op_ops[i]->sym->m_src;
+ mbuf1 = op_ops[i + 1]->sym->m_src;
+ mbuf2 = op_ops[i + 2]->sym->m_src;
+ mbuf3 = op_ops[i + 3]->sym->m_src;
+
+ rte_memcpy(mbuf0->buf_addr, &op_ops[i], sizeof(op_ops[i]));
+ rte_memcpy(mbuf1->buf_addr, &op_ops[i + 1],
+ sizeof(op_ops[i + 1]));
+ rte_memcpy(mbuf2->buf_addr, &op_ops[i + 2],
+ sizeof(op_ops[i + 2]));
+ rte_memcpy(mbuf3->buf_addr, &op_ops[i + 3],
+ sizeof(op_ops[i + 3]));
+
+ mbuf0->seqn = internal->seqn++;
+ mbuf1->seqn = internal->seqn++;
+ mbuf2->seqn = internal->seqn++;
+ mbuf3->seqn = internal->seqn++;
+
+ rte_reorder_insert(reorder_buff, mbuf0);
+ rte_reorder_insert(reorder_buff, mbuf1);
+ rte_reorder_insert(reorder_buff, mbuf2);
+ rte_reorder_insert(reorder_buff, mbuf3);
+
+ rte_prefetch0(op_ops[i + 4]->sym->m_src);
+ rte_prefetch0(op_ops[i + 5]->sym->m_src);
+ rte_prefetch0(op_ops[i + 6]->sym->m_src);
+ rte_prefetch0(op_ops[i + 7]->sym->m_src);
+ }
+
+ for (; i < nb_deq_ops; i++) {
+ mbuf0 = op_ops[i]->sym->m_src;
+
+ rte_memcpy(mbuf0->buf_addr, &op_ops[i], sizeof(op_ops[i]));
+
+ mbuf0->seqn = internal->seqn++;
+
+ rte_reorder_insert(reorder_buff, mbuf0);
+ }
+
+ nb_deq_ops = rte_reorder_drain(reorder_buff, reorder_mbufs,
+ nb_ops);
+
+ for (i = 0; i < nb_deq_ops && i < 4; i++)
+ rte_prefetch0(reorder_mbufs[i]);
+
+ for (i = 0; i < nb_deq_ops - 8; i += 4) {
+ ops[i] = *(struct rte_crypto_op **)
+ reorder_mbufs[i]->buf_addr;
+ ops[i + 1] = *(struct rte_crypto_op **)
+ reorder_mbufs[i + 1]->buf_addr;
+ ops[i + 2] = *(struct rte_crypto_op **)
+ reorder_mbufs[i + 2]->buf_addr;
+ ops[i + 3] = *(struct rte_crypto_op **)
+ reorder_mbufs[i + 3]->buf_addr;
+
+ *(struct rte_crypto_op **)reorder_mbufs[i]->buf_addr = NULL;
+ *(struct rte_crypto_op **)reorder_mbufs[i + 1]->buf_addr = NULL;
+ *(struct rte_crypto_op **)reorder_mbufs[i + 2]->buf_addr = NULL;
+ *(struct rte_crypto_op **)reorder_mbufs[i + 3]->buf_addr = NULL;
+
+ rte_prefetch0(reorder_mbufs[i + 4]);
+ rte_prefetch0(reorder_mbufs[i + 5]);
+ rte_prefetch0(reorder_mbufs[i + 6]);
+ rte_prefetch0(reorder_mbufs[i + 7]);
+ }
+
+ for (; i < nb_deq_ops; i++) {
+ ops[i] = *(struct rte_crypto_op **)
+ reorder_mbufs[i]->buf_addr;
+ *(struct rte_crypto_op **)reorder_mbufs[i]->buf_addr = NULL;
+ }
+
+ qp->stats.dequeued_count += nb_deq_ops;
+
+ return nb_deq_ops;
+}
+
+int
+scheduler_update_rx_tx_ops(struct rte_cryptodev *dev,
+ enum crypto_scheduling_mode mode, uint32_t use_reorder)
+{
+ switch (mode) {
+ case CRYPTO_SCHED_SW_ROUND_ROBIN_MODE:
+ case CRYPTO_SCHED_HW_ROUND_ROBIN_MODE:
+ dev->enqueue_burst = scheduler_enqueue_burst_rr;
+ if (use_reorder)
+ dev->dequeue_burst =
+ scheduler_dequeue_burst_rr_reorder;
+ else
+ dev->dequeue_burst =
+ scheduler_dequeue_burst_rr_no_reorder;
+ break;
+ default:
+ return -1;
+ }
+
+ return 0;
+}
+
+static uint32_t unique_name_id;
+
+static int
+cryptodev_scheduler_create(const char *name,
+ struct rte_crypto_vdev_init_params *init_params,
+ const uint8_t enable_reorder)
+{
+ char crypto_dev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
+ struct scheduler_private *internal;
+ struct rte_cryptodev *dev;
+
+ if (snprintf(crypto_dev_name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%u",
+ RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD), unique_name_id++) < 0) {
+ CS_LOG_ERR("driver %s: failed to create unique cryptodev "
+ "name", name);
+ return -EFAULT;
+ }
+
+ dev = rte_cryptodev_pmd_virtual_dev_init(crypto_dev_name,
+ sizeof(struct scheduler_private),
+ init_params->socket_id);
+ if (dev == NULL) {
+ CS_LOG_ERR("driver %s: failed to create cryptodev vdev",
+ name);
+ return -EFAULT;
+ }
+
+ dev->dev_type = RTE_CRYPTODEV_SCHEDULER_PMD;
+ dev->dev_ops = rte_crypto_scheduler_pmd_ops;
+
+ dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO;
+
+ internal = dev->data->dev_private;
+ internal->max_nb_queue_pairs = init_params->max_nb_queue_pairs;
+ internal->max_nb_sessions = UINT32_MAX;
+ internal->use_reorder = enable_reorder;
+
+ /* register rx/tx burst functions for data path
+ * by default the software round robin mode is adopted
+ */
+ return scheduler_update_rx_tx_ops(dev, CRYPTO_SCHED_SW_ROUND_ROBIN_MODE,
+ internal->use_reorder);
+}
+
+static int
+cryptodev_scheduler_remove(const char *name)
+{
+ struct rte_cryptodev *dev;
+ struct scheduler_private *internal;
+
+ if (name == NULL)
+ return -EINVAL;
+
+ dev = rte_cryptodev_pmd_get_named_dev(name);
+ if (dev == NULL)
+ return -EINVAL;
+
+ internal = dev->data->dev_private;
+
+ if (internal->reorder_buff)
+ rte_reorder_free(internal->reorder_buff);
+
+ RTE_LOG(INFO, PMD, "Closing Crypto Scheduler device %s on numa "
+ "socket %u\n", name, rte_socket_id());
+
+ return 0;
+}
+
+/** Parse integer from integer argument */
+static int
+parse_integer_arg(const char *key __rte_unused,
+ const char *value, void *extra_args)
+{
+ int *i = (int *) extra_args;
+
+ *i = atoi(value);
+ if (*i < 0) {
+ CDEV_LOG_ERR("Argument has to be positive.");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Parse reorder enable/disable argument */
+static int
+scheduler_parse_enable_reorder_kvarg(const char *key __rte_unused,
+ const char *value, void *extra_args)
+{
+ if (value == NULL || extra_args == NULL)
+ return -1;
+
+ if (strcmp(value, "yes") == 0)
+ *(uint8_t *)extra_args = 1;
+ else if (strcmp(value, "no") == 0)
+ *(uint8_t *)extra_args = 0;
+ else
+ return -1;
+
+ return 0;
+}
+
+static uint8_t
+number_of_sockets(void)
+{
+ int sockets = 0;
+ int i;
+ const struct rte_memseg *ms = rte_eal_get_physmem_layout();
+
+ for (i = 0; ((i < RTE_MAX_MEMSEG) && (ms[i].addr != NULL)); i++) {
+ if (sockets < ms[i].socket_id)
+ sockets = ms[i].socket_id;
+ }
+
+ /* Number of sockets = maximum socket_id + 1 */
+ return ++sockets;
+}
+
+static int
+scheduler_parse_init_params(struct rte_crypto_vdev_init_params *params,
+ uint8_t *enable_reorder, const char *input_args)
+{
+ struct rte_kvargs *kvlist = NULL;
+ int ret = 0;
+
+ if (params == NULL)
+ return -EINVAL;
+
+ if (!input_args)
+ return 0;
+
+ kvlist = rte_kvargs_parse(input_args,
+ scheduler_vdev_valid_params);
+ if (kvlist == NULL)
+ return -1;
+
+ ret = rte_kvargs_process(kvlist, SCHEDULER_MAX_NB_QP_ARG,
+ &parse_integer_arg, ¶ms->max_nb_queue_pairs);
+ if (ret < 0)
+ goto free_kvlist;
+
+ ret = rte_kvargs_process(kvlist, SCHEDULER_MAX_NB_SESS_ARG,
+ &parse_integer_arg, ¶ms->max_nb_sessions);
+ if (ret < 0)
+ goto free_kvlist;
+
+ ret = rte_kvargs_process(kvlist, SCHEDULER_SOCKET_ID,
+ &parse_integer_arg, ¶ms->socket_id);
+ if (ret < 0)
+ goto free_kvlist;
+
+ if (params->socket_id >= number_of_sockets()) {
+ CDEV_LOG_ERR("Invalid socket id specified to create "
+ "the virtual crypto device on");
+ goto free_kvlist;
+ }
+
+ ret = rte_kvargs_process(kvlist, SCHEDULER_ENABLE_REORDER_ARG,
+ &scheduler_parse_enable_reorder_kvarg, enable_reorder);
+ if (ret < 0)
+ goto free_kvlist;
+
+free_kvlist:
+ rte_kvargs_free(kvlist);
+ return ret;
+}
+
+static int
+cryptodev_scheduler_probe(const char *name, const char *input_args)
+{
+ struct rte_crypto_vdev_init_params init_params = {
+ RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_QUEUE_PAIRS,
+ RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_SESSIONS,
+ rte_socket_id()
+ };
+ uint8_t enable_reorder = 0;
+
+ scheduler_parse_init_params(&init_params, &enable_reorder, input_args);
+
+ RTE_LOG(INFO, PMD, "Initialising %s on NUMA node %d\n", name,
+ init_params.socket_id);
+ RTE_LOG(INFO, PMD, " Max number of queue pairs = %d\n",
+ init_params.max_nb_queue_pairs);
+ RTE_LOG(INFO, PMD, " Max number of sessions = %d\n",
+ init_params.max_nb_sessions);
+
+ return cryptodev_scheduler_create(name, &init_params, enable_reorder);
+}
+
+static struct rte_vdev_driver cryptodev_scheduler_pmd_drv = {
+ .probe = cryptodev_scheduler_probe,
+ .remove = cryptodev_scheduler_remove
+};
+
+RTE_PMD_REGISTER_VDEV(CRYPTODEV_NAME_SCHEDULER_PMD,
+ cryptodev_scheduler_pmd_drv);
+RTE_PMD_REGISTER_PARAM_STRING(CRYPTODEV_NAME_SCHEDULER_PMD,
+ "max_nb_queue_pairs=<int> "
+ "max_nb_sessions=<int> "
+ "socket_id=<int> "
+ "enable_reorder=yes/no");
diff --git a/drivers/crypto/scheduler/scheduler_pmd_ops.c b/drivers/crypto/scheduler/scheduler_pmd_ops.c
new file mode 100644
index 0000000..a98a127
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_pmd_ops.c
@@ -0,0 +1,335 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <string.h>
+
+#include <rte_config.h>
+#include <rte_common.h>
+#include <rte_malloc.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_reorder.h>
+
+#include "../scheduler/scheduler_pmd_private.h"
+
+/** Configure device */
+static int
+scheduler_pmd_config(__rte_unused struct rte_cryptodev *dev)
+{
+ return 0;
+}
+
+/** Start device */
+static int
+scheduler_pmd_start(struct rte_cryptodev *dev)
+{
+ struct scheduler_private *internal = dev->data->dev_private;
+ uint32_t i, j;
+
+ /* TODO: this may cause one dev being started multiple times,
+ * so far as all dev's start functions only returns 0, so it doesn't
+ * matter yet. However whenever a new dev driver is added and doesn't
+ * allow its start func being called more than once, this need to
+ * be updated.
+ */
+ for (i = 0; i < 2; i++)
+ for (j = 0; j < internal->nb_slaves[i]; j++) {
+ int status = rte_cryptodev_start(
+ internal->slaves[i][j].dev_id);
+ if (status < 0) {
+ CS_LOG_ERR("cannot start device %u",
+ internal->slaves[i][j].dev_id);
+ return status;
+ }
+ }
+
+ return 0;
+}
+
+/** Stop device */
+static void
+scheduler_pmd_stop(struct rte_cryptodev *dev)
+{
+ struct scheduler_private *internal = dev->data->dev_private;
+ uint32_t i, j;
+
+ for (i = 0; i < 2; i++)
+ for (j = 0; j < internal->nb_slaves[i]; j++)
+ rte_cryptodev_stop(internal->slaves[i][j].dev_id);
+}
+
+/** Close device */
+static int
+scheduler_pmd_close(struct rte_cryptodev *dev)
+{
+ struct scheduler_private *internal = dev->data->dev_private;
+ uint32_t i, j;
+
+ for (i = 0; i < 2; i++)
+ for (j = 0; j < internal->nb_slaves[i]; j++) {
+ int status = rte_cryptodev_close(
+ internal->slaves[i][j].dev_id);
+ if (status < 0) {
+ CS_LOG_ERR("cannot close device %u",
+ internal->slaves[i][j].dev_id);
+ return status;
+ }
+ }
+
+ return 0;
+}
+
+/** Get device statistics */
+static void
+scheduler_pmd_stats_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_stats *stats)
+{
+ int qp_id;
+
+ for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
+ struct scheduler_qp *qp = dev->data->queue_pairs[qp_id];
+
+ stats->enqueued_count += qp->stats.enqueued_count;
+ stats->dequeued_count += qp->stats.dequeued_count;
+
+ stats->enqueue_err_count += qp->stats.enqueue_err_count;
+ stats->dequeue_err_count += qp->stats.dequeue_err_count;
+ }
+}
+
+/** Reset device statistics */
+static void
+scheduler_pmd_stats_reset(struct rte_cryptodev *dev)
+{
+ int qp_id;
+
+ for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
+ struct scheduler_qp *qp = dev->data->queue_pairs[qp_id];
+
+ memset(&qp->stats, 0, sizeof(qp->stats));
+ }
+}
+
+/** Get device info */
+static void
+scheduler_pmd_info_get(struct rte_cryptodev *dev,
+ struct rte_cryptodev_info *dev_info)
+{
+ struct scheduler_private *internal = dev->data->dev_private;
+
+ if (dev_info != NULL) {
+ dev_info->dev_type = dev->dev_type;
+ dev_info->feature_flags = dev->feature_flags;
+ dev_info->capabilities = internal->capabilities;
+ dev_info->max_nb_queue_pairs = internal->max_nb_queue_pairs;
+ dev_info->sym.max_nb_sessions = internal->max_nb_sessions;
+ }
+}
+
+/** Release queue pair */
+static int
+scheduler_pmd_qp_release(struct rte_cryptodev *dev, uint16_t qp_id)
+{
+ if (dev->data->queue_pairs[qp_id] != NULL) {
+ rte_free(dev->data->queue_pairs[qp_id]);
+ dev->data->queue_pairs[qp_id] = NULL;
+ }
+ return 0;
+}
+
+/** Setup a queue pair */
+static int
+scheduler_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
+ __rte_unused const struct rte_cryptodev_qp_conf *qp_conf, int socket_id)
+{
+ struct scheduler_qp *qp = NULL;
+
+ /* Free memory prior to re-allocation if needed. */
+ if (dev->data->queue_pairs[qp_id] != NULL)
+ scheduler_pmd_qp_release(dev, qp_id);
+
+ /* Allocate the queue pair data structure. */
+ qp = rte_zmalloc_socket("CRYPTO-SCHEDULER PMD Queue Pair",
+ sizeof(*qp), RTE_CACHE_LINE_SIZE, socket_id);
+ if (qp == NULL)
+ return -ENOMEM;
+
+ qp->id = qp_id;
+ dev->data->queue_pairs[qp_id] = qp;
+ memset(&qp->stats, 0, sizeof(qp->stats));
+
+ if (snprintf(qp->name, sizeof(qp->name),
+ "scheduler_pmd_%u_qp_%u", dev->data->dev_id,
+ qp->id) > (int)sizeof(qp->name)) {
+ CS_LOG_ERR("unable to create unique name for queue pair");
+ rte_free(qp);
+ return -EFAULT;
+ }
+
+ qp->dev_priv = dev->data->dev_private;
+
+ return 0;
+}
+
+/** Start queue pair */
+static int
+scheduler_pmd_qp_start(__rte_unused struct rte_cryptodev *dev,
+ __rte_unused uint16_t queue_pair_id)
+{
+ return -ENOTSUP;
+}
+
+/** Stop queue pair */
+static int
+scheduler_pmd_qp_stop(__rte_unused struct rte_cryptodev *dev,
+ __rte_unused uint16_t queue_pair_id)
+{
+ return -ENOTSUP;
+}
+
+/** Return the number of allocated queue pairs */
+static uint32_t
+scheduler_pmd_qp_count(struct rte_cryptodev *dev)
+{
+ return dev->data->nb_queue_pairs;
+}
+
+static unsigned
+scheduler_pmd_session_get_size(struct rte_cryptodev *dev __rte_unused)
+{
+ return sizeof(struct scheduler_session);
+}
+
+static int
+config_slave_sessions(struct scheduler_private *internal,
+ struct rte_crypto_sym_xform *xform,
+ struct scheduler_session *sess,
+ uint32_t create)
+{
+
+ uint32_t i, j;
+
+ for (i = 0; i < 2; i++) {
+ for (j = 0; j < internal->nb_slaves[i]; j++) {
+ uint8_t dev_id = internal->slaves[i][j].dev_id;
+ struct rte_cryptodev *dev = &rte_cryptodev_globals->
+ devs[dev_id];
+
+ /* clear */
+ if (!create) {
+ if (!sess->slave_sesses[i][j])
+ continue;
+
+ dev->dev_ops->session_clear(dev,
+ (void *)sess->slave_sesses[i][j]);
+ sess->slave_sesses[i][j] = NULL;
+
+ continue;
+ }
+
+ /* configure */
+ if (sess->slave_sesses[i][j] == NULL)
+ sess->slave_sesses[i][j] =
+ rte_cryptodev_sym_session_create(
+ dev_id, xform);
+ else
+ sess->slave_sesses[i][j] =
+ dev->dev_ops->session_configure(dev,
+ xform,
+ sess->slave_sesses[i][j]);
+
+ if (!sess->slave_sesses[i][j]) {
+ CS_LOG_ERR("unabled to config sym session");
+ config_slave_sessions(internal, NULL, sess, 0);
+ return -1;
+ }
+ }
+
+ for (j = internal->nb_slaves[i]; j < MAX_SLAVES_NUM; j++)
+ sess->slave_sesses[i][j] = NULL;
+ }
+
+ return 0;
+}
+
+/** Clear the memory of session so it doesn't leave key material behind */
+static void
+scheduler_pmd_session_clear(struct rte_cryptodev *dev,
+ void *sess)
+{
+ struct scheduler_private *internal = dev->data->dev_private;
+
+ config_slave_sessions(internal, NULL, sess, 0);
+
+ memset(sess, 0, sizeof(struct scheduler_session));
+}
+
+
+
+static void *
+scheduler_pmd_session_configure(struct rte_cryptodev *dev,
+ struct rte_crypto_sym_xform *xform, void *sess)
+{
+ struct scheduler_private *internal = dev->data->dev_private;
+
+ if (config_slave_sessions(internal, xform, sess, 1) < 0) {
+ CS_LOG_ERR("unabled to config sym session");
+ scheduler_pmd_session_clear(dev, sess);
+ return NULL;
+ }
+
+ return sess;
+}
+
+
+struct rte_cryptodev_ops scheduler_pmd_ops = {
+ .dev_configure = scheduler_pmd_config,
+ .dev_start = scheduler_pmd_start,
+ .dev_stop = scheduler_pmd_stop,
+ .dev_close = scheduler_pmd_close,
+
+ .stats_get = scheduler_pmd_stats_get,
+ .stats_reset = scheduler_pmd_stats_reset,
+
+ .dev_infos_get = scheduler_pmd_info_get,
+
+ .queue_pair_setup = scheduler_pmd_qp_setup,
+ .queue_pair_release = scheduler_pmd_qp_release,
+ .queue_pair_start = scheduler_pmd_qp_start,
+ .queue_pair_stop = scheduler_pmd_qp_stop,
+ .queue_pair_count = scheduler_pmd_qp_count,
+
+ .session_get_size = scheduler_pmd_session_get_size,
+ .session_configure = scheduler_pmd_session_configure,
+ .session_clear = scheduler_pmd_session_clear,
+};
+
+struct rte_cryptodev_ops *rte_crypto_scheduler_pmd_ops = &scheduler_pmd_ops;
diff --git a/drivers/crypto/scheduler/scheduler_pmd_private.h b/drivers/crypto/scheduler/scheduler_pmd_private.h
new file mode 100644
index 0000000..db605b8
--- /dev/null
+++ b/drivers/crypto/scheduler/scheduler_pmd_private.h
@@ -0,0 +1,137 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SCHEDULER_PMD_PRIVATE_H
+#define _SCHEDULER_PMD_PRIVATE_H
+
+#include <rte_hash.h>
+#include <rte_cryptodev_scheduler.h>
+
+/**< Maximum number of bonded devices per devices */
+#ifndef MAX_SLAVES_NUM
+#define MAX_SLAVES_NUM (8)
+#endif
+
+/**< Maximum number of bonded capabilities */
+#ifndef MAX_CAP_NUM
+#define MAX_CAP_NUM (32)
+#endif
+
+/**< Maximum Crypto OP burst number */
+#ifndef MAX_OP_BURST_NUM
+#define MAX_OP_BURST_NUM (32)
+#endif
+
+#define PER_SLAVE_BUFF_SIZE (256)
+
+#define CS_LOG_ERR(fmt, args...) \
+ RTE_LOG(ERR, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
+ RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD), \
+ __func__, __LINE__, ## args)
+
+#ifdef RTE_LIBRTE_CRYPTO_SCHEDULER_DEBUG
+#define CS_LOG_INFO(fmt, args...) \
+ RTE_LOG(INFO, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
+ RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD), \
+ __func__, __LINE__, ## args)
+
+#define CS_LOG_DBG(fmt, args...) \
+ RTE_LOG(DEBUG, CRYPTODEV, "[%s] %s() line %u: " fmt "\n", \
+ RTE_STR(CRYPTODEV_NAME_SCHEDULER_PMD), \
+ __func__, __LINE__, ## args)
+#else
+#define CS_LOG_INFO(fmt, args...)
+#define CS_LOG_DBG(fmt, args...)
+#endif
+
+/* global hash table storing occupied cdev/qp info */
+struct rte_hash *dev_qp_map;
+
+struct slave_info {
+ uint8_t dev_id;
+ uint16_t qp_id;
+};
+
+#define SCHED_SW_CDEV 0
+#define SCHED_HW_CDEV 1
+
+/* function pointer for different modes' enqueue/dequeue ops */
+typedef uint16_t (*sched_enq_deq_t)(void *queue_pair,
+ struct rte_crypto_op **ops, uint16_t nb_ops);
+
+struct scheduler_private {
+ struct slave_info slaves[2][MAX_SLAVES_NUM];
+ uint8_t nb_slaves[2];
+ uint8_t last_enq_idx[2];
+ uint8_t last_deq_idx[2];
+
+ void *reorder_buff;
+
+ sched_enq_deq_t enqueue;
+ sched_enq_deq_t dequeue;
+
+ enum crypto_scheduling_mode mode;
+
+ uint32_t seqn;
+ uint8_t use_dev_type;
+
+ uint8_t use_reorder;
+
+ struct rte_cryptodev_capabilities
+ capabilities[MAX_CAP_NUM];
+ uint32_t max_nb_queue_pairs;
+ uint32_t max_nb_sessions;
+} __rte_cache_aligned;
+
+struct scheduler_qp {
+ uint16_t id;
+ /**< Queue Pair Identifier */
+ char name[RTE_CRYPTODEV_NAME_LEN];
+ /**< Unique Queue Pair Name */
+ struct rte_cryptodev_stats stats;
+ /**< Queue pair statistics */
+ struct scheduler_private *dev_priv;
+} __rte_cache_aligned;
+
+struct scheduler_session {
+ struct rte_cryptodev_sym_session *slave_sesses[2][MAX_SLAVES_NUM];
+};
+
+/** device specific operations function pointer structure */
+extern struct rte_cryptodev_ops *rte_crypto_scheduler_pmd_ops;
+
+int
+scheduler_update_rx_tx_ops(struct rte_cryptodev *dev,
+ enum crypto_scheduling_mode mode, uint32_t use_reorder);
+
+#endif /* _SCHEDULER_PMD_PRIVATE_H */
diff --git a/lib/librte_cryptodev/rte_cryptodev.h b/lib/librte_cryptodev/rte_cryptodev.h
index 8f63e8f..3aa70af 100644
--- a/lib/librte_cryptodev/rte_cryptodev.h
+++ b/lib/librte_cryptodev/rte_cryptodev.h
@@ -66,6 +66,7 @@ extern "C" {
/**< KASUMI PMD device name */
#define CRYPTODEV_NAME_ZUC_PMD crypto_zuc
/**< KASUMI PMD device name */
+#define CRYPTODEV_NAME_SCHEDULER_PMD crypto_scheduler
/** Crypto device type */
enum rte_cryptodev_type {
@@ -77,6 +78,7 @@ enum rte_cryptodev_type {
RTE_CRYPTODEV_KASUMI_PMD, /**< KASUMI PMD */
RTE_CRYPTODEV_ZUC_PMD, /**< ZUC PMD */
RTE_CRYPTODEV_OPENSSL_PMD, /**< OpenSSL PMD */
+ RTE_CRYPTODEV_SCHEDULER_PMD, /**< Crypto Scheduler PMD */
};
extern const char **rte_cyptodev_names;
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index f75f0e2..ee34688 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -70,7 +70,6 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PORT) += -lrte_port
_LDLIBS-$(CONFIG_RTE_LIBRTE_PDUMP) += -lrte_pdump
_LDLIBS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += -lrte_distributor
-_LDLIBS-$(CONFIG_RTE_LIBRTE_REORDER) += -lrte_reorder
_LDLIBS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += -lrte_ip_frag
_LDLIBS-$(CONFIG_RTE_LIBRTE_METER) += -lrte_meter
_LDLIBS-$(CONFIG_RTE_LIBRTE_SCHED) += -lrte_sched
@@ -98,6 +97,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_RING) += -lrte_ring
_LDLIBS-$(CONFIG_RTE_LIBRTE_EAL) += -lrte_eal
_LDLIBS-$(CONFIG_RTE_LIBRTE_CMDLINE) += -lrte_cmdline
_LDLIBS-$(CONFIG_RTE_LIBRTE_CFGFILE) += -lrte_cfgfile
+_LDLIBS-$(CONFIG_RTE_LIBRTE_REORDER) += -lrte_reorder
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += -lrte_pmd_bond
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += -lrte_pmd_xenvirt -lxenstore
@@ -145,6 +145,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += -lrte_pmd_kasumi
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_KASUMI) += -L$(LIBSSO_KASUMI_PATH)/build -lsso_kasumi
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += -lrte_pmd_zuc
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += -L$(LIBSSO_ZUC_PATH)/build -lsso_zuc
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
endif # CONFIG_RTE_LIBRTE_CRYPTODEV
endif # !CONFIG_RTE_BUILD_SHARED_LIBS
--
2.7.4
^ permalink raw reply related
* [PATCH] net/i40evf: fix reporting of imissed packets
From: Tom Crugnale @ 2016-12-02 13:57 UTC (permalink / raw)
To: helin.zhang@intel.com, jingjing.wu@intel.com; +Cc: dev@dpdk.org, Tom Crugnale
In-Reply-To: <1480616446-23644-1-git-send-email-tcrugnale@sandvine.com>
Missed packets on RX were erroneously being assigned to the ierrors struct member. Change it to be assigned to imissed.
Fixes: 4861cde4 ("i40e: new poll mode driver")
Signed-off-by: Tom Crugnale <tcrugnale@sandvine.com>
---
drivers/net/i40e/i40e_ethdev_vf.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
index aa306d6..90876c8 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -952,7 +952,7 @@ struct rte_i40evf_xstats_name_off { }
static int
-i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
+i40evf_get_stats(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
{
int ret;
struct i40e_eth_stats *pstats = NULL;
@@ -965,7 +965,7 @@ struct rte_i40evf_xstats_name_off {
pstats->rx_broadcast;
stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
pstats->tx_unicast;
- stats->ierrors = pstats->rx_discards;
+ stats->imissed = pstats->rx_discards;
stats->oerrors = pstats->tx_errors + pstats->tx_discards;
stats->ibytes = pstats->rx_bytes;
stats->obytes = pstats->tx_bytes;
@@ -2277,8 +2277,8 @@ static int i40evf_dev_xstats_get(struct rte_eth_dev *dev, static void i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) {
- if (i40evf_get_statics(dev, stats))
- PMD_DRV_LOG(ERR, "Get statics failed");
+ if (i40evf_get_stats(dev, stats))
+ PMD_DRV_LOG(ERR, "Get stats failed");
}
static void
--
1.8.3.1
^ permalink raw reply related
* [PATCH] crypto/aesni_gcm: migration from MB library to ISA-L
From: Michal Jastrzebski @ 2016-12-02 13:04 UTC (permalink / raw)
To: dev; +Cc: pablo.de.lara.guarch, Piotr Azarewicz
From: Piotr Azarewicz <piotrx.t.azarewicz@intel.com>
Current Cryptodev AESNI-GCM PMD is implemented using AESNI-MB
library.This patch reimplement Cryptodev AESni-GCM using ISA-L Crypto
library: https://github.com/01org/isa-l_crypto.
In new version 256-bit key support and AAD variable lenght is available.
Verified current unit tests and added new unit tests to verify new
functionalities.
Signed-off-by: Piotr Azarewicz <piotrx.t.azarewicz@intel.com>
---
app/test/test_cryptodev.c | 337 +++++++++++-----
app/test/test_cryptodev_gcm_test_vectors.h | 481 ++++++++++++++++++++++-
doc/guides/cryptodevs/aesni_gcm.rst | 18 +-
drivers/crypto/aesni_gcm/Makefile | 8 +-
drivers/crypto/aesni_gcm/aesni_gcm_ops.h | 91 +----
drivers/crypto/aesni_gcm/aesni_gcm_pmd.c | 110 ++----
drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c | 24 +-
drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h | 15 +-
mk/rte.app.mk | 3 +-
9 files changed, 776 insertions(+), 311 deletions(-)
diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 872f8b4..fdf800a 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -3916,15 +3916,13 @@ create_gcm_session(uint8_t dev_id, enum rte_crypto_cipher_operation op,
static int
create_gcm_operation(enum rte_crypto_cipher_operation op,
- const uint8_t *auth_tag, const unsigned auth_tag_len,
- const uint8_t *iv, const unsigned iv_len,
- const uint8_t *aad, const unsigned aad_len,
- const unsigned data_len, unsigned data_pad_len)
+ const struct gcm_test_data *tdata)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
struct crypto_unittest_params *ut_params = &unittest_params;
- unsigned iv_pad_len = 0, aad_buffer_len;
+ uint8_t *plaintext;
+ unsigned int iv_pad_len, aad_pad_len, plaintext_pad_len;
/* Generate Crypto op data structure */
ut_params->op = rte_crypto_op_alloc(ts_params->op_mpool,
@@ -3934,63 +3932,79 @@ create_gcm_operation(enum rte_crypto_cipher_operation op,
struct rte_crypto_sym_op *sym_op = ut_params->op->sym;
- sym_op->auth.digest.data = (uint8_t *)rte_pktmbuf_append(
- ut_params->ibuf, auth_tag_len);
- TEST_ASSERT_NOT_NULL(sym_op->auth.digest.data,
- "no room to append digest");
- sym_op->auth.digest.phys_addr = rte_pktmbuf_mtophys_offset(
- ut_params->ibuf, data_pad_len);
- sym_op->auth.digest.length = auth_tag_len;
-
- if (op == RTE_CRYPTO_CIPHER_OP_DECRYPT) {
- rte_memcpy(sym_op->auth.digest.data, auth_tag, auth_tag_len);
- TEST_HEXDUMP(stdout, "digest:",
- sym_op->auth.digest.data,
- sym_op->auth.digest.length);
- }
+ /* Append aad data */
+ aad_pad_len = RTE_ALIGN_CEIL(tdata->aad.len, 16);
+ sym_op->auth.aad.data = (uint8_t *)rte_pktmbuf_append(ut_params->ibuf,
+ aad_pad_len);
+ TEST_ASSERT_NOT_NULL(sym_op->auth.aad.data,
+ "no room to append aad");
- /* iv */
- iv_pad_len = RTE_ALIGN_CEIL(iv_len, 16);
+ sym_op->auth.aad.length = tdata->aad.len;
+ sym_op->auth.aad.phys_addr =
+ rte_pktmbuf_mtophys(ut_params->ibuf);
+ memcpy(sym_op->auth.aad.data, tdata->aad.data, tdata->aad.len);
+ TEST_HEXDUMP(stdout, "aad:", sym_op->auth.aad.data,
+ sym_op->auth.aad.length);
+ /* Prepend iv */
+ iv_pad_len = RTE_ALIGN_CEIL(tdata->iv.len, 16);
sym_op->cipher.iv.data = (uint8_t *)rte_pktmbuf_prepend(
ut_params->ibuf, iv_pad_len);
TEST_ASSERT_NOT_NULL(sym_op->cipher.iv.data, "no room to prepend iv");
memset(sym_op->cipher.iv.data, 0, iv_pad_len);
sym_op->cipher.iv.phys_addr = rte_pktmbuf_mtophys(ut_params->ibuf);
- sym_op->cipher.iv.length = iv_len;
+ sym_op->cipher.iv.length = tdata->iv.len;
- rte_memcpy(sym_op->cipher.iv.data, iv, iv_len);
+ rte_memcpy(sym_op->cipher.iv.data, tdata->iv.data, tdata->iv.len);
+ TEST_HEXDUMP(stdout, "iv:", sym_op->cipher.iv.data,
+ sym_op->cipher.iv.length);
- /*
- * Always allocate the aad up to the block size.
- * The cryptodev API calls out -
- * - the array must be big enough to hold the AAD, plus any
- * space to round this up to the nearest multiple of the
- * block size (16 bytes).
- */
- aad_buffer_len = ALIGN_POW2_ROUNDUP(aad_len, 16);
+ /* Append plaintext/ciphertext */
+ if (op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) {
+ plaintext_pad_len = RTE_ALIGN_CEIL(tdata->plaintext.len, 16);
+ plaintext = (uint8_t *)rte_pktmbuf_append(ut_params->ibuf,
+ plaintext_pad_len);
+ TEST_ASSERT_NOT_NULL(plaintext, "no room to append plaintext");
- sym_op->auth.aad.data = (uint8_t *)rte_pktmbuf_prepend(
- ut_params->ibuf, aad_buffer_len);
- TEST_ASSERT_NOT_NULL(sym_op->auth.aad.data,
- "no room to prepend aad");
- sym_op->auth.aad.phys_addr = rte_pktmbuf_mtophys(
- ut_params->ibuf);
- sym_op->auth.aad.length = aad_len;
+ memcpy(plaintext, tdata->plaintext.data, tdata->plaintext.len);
+ TEST_HEXDUMP(stdout, "plaintext:", plaintext,
+ tdata->plaintext.len);
+ } else {
+ plaintext_pad_len = RTE_ALIGN_CEIL(tdata->ciphertext.len, 16);
+ plaintext = (uint8_t *)rte_pktmbuf_append(ut_params->ibuf,
+ plaintext_pad_len);
+ TEST_ASSERT_NOT_NULL(plaintext, "no room to append ciphertext");
- memset(sym_op->auth.aad.data, 0, aad_buffer_len);
- rte_memcpy(sym_op->auth.aad.data, aad, aad_len);
+ memcpy(plaintext, tdata->ciphertext.data,
+ tdata->ciphertext.len);
+ TEST_HEXDUMP(stdout, "ciphertext:", plaintext,
+ tdata->ciphertext.len);
+ }
- TEST_HEXDUMP(stdout, "iv:", sym_op->cipher.iv.data, iv_pad_len);
- TEST_HEXDUMP(stdout, "aad:",
- sym_op->auth.aad.data, aad_len);
+ /* Append digest data */
+ sym_op->auth.digest.data = (uint8_t *)rte_pktmbuf_append(
+ ut_params->ibuf, tdata->auth_tag.len);
+ TEST_ASSERT_NOT_NULL(sym_op->auth.digest.data,
+ "no room to append digest");
+ sym_op->auth.digest.phys_addr = rte_pktmbuf_mtophys_offset(
+ ut_params->ibuf,
+ plaintext_pad_len + aad_pad_len + iv_pad_len);
+ sym_op->auth.digest.length = tdata->auth_tag.len;
+
+ if (op == RTE_CRYPTO_CIPHER_OP_DECRYPT) {
+ rte_memcpy(sym_op->auth.digest.data, tdata->auth_tag.data,
+ tdata->auth_tag.len);
+ TEST_HEXDUMP(stdout, "digest:",
+ sym_op->auth.digest.data,
+ sym_op->auth.digest.length);
+ }
- sym_op->cipher.data.length = data_len;
- sym_op->cipher.data.offset = aad_buffer_len + iv_pad_len;
+ sym_op->cipher.data.length = tdata->plaintext.len;
+ sym_op->cipher.data.offset = aad_pad_len + iv_pad_len;
- sym_op->auth.data.offset = aad_buffer_len + iv_pad_len;
- sym_op->auth.data.length = data_len;
+ sym_op->auth.data.length = tdata->plaintext.len;
+ sym_op->auth.data.offset = aad_pad_len + iv_pad_len;
return 0;
}
@@ -4002,9 +4016,9 @@ test_mb_AES_GCM_authenticated_encryption(const struct gcm_test_data *tdata)
struct crypto_unittest_params *ut_params = &unittest_params;
int retval;
-
- uint8_t *plaintext, *ciphertext, *auth_tag;
+ uint8_t *ciphertext, *auth_tag;
uint16_t plaintext_pad_len;
+ uint32_t i;
/* Create GCM session */
retval = create_gcm_session(ts_params->valid_devs[0],
@@ -4015,31 +4029,20 @@ test_mb_AES_GCM_authenticated_encryption(const struct gcm_test_data *tdata)
if (retval < 0)
return retval;
-
- ut_params->ibuf = rte_pktmbuf_alloc(ts_params->mbuf_pool);
+ if (tdata->aad.len > MBUF_SIZE) {
+ ut_params->ibuf = rte_pktmbuf_alloc(ts_params->large_mbuf_pool);
+ /* Populate full size of add data */
+ for (i = 32; i < GMC_MAX_AAD_LENGTH; i += 32)
+ memcpy(&tdata->aad.data[i], &tdata->aad.data[0], 32);
+ } else
+ ut_params->ibuf = rte_pktmbuf_alloc(ts_params->mbuf_pool);
/* clear mbuf payload */
memset(rte_pktmbuf_mtod(ut_params->ibuf, uint8_t *), 0,
rte_pktmbuf_tailroom(ut_params->ibuf));
- /*
- * Append data which is padded to a multiple
- * of the algorithms block size
- */
- plaintext_pad_len = RTE_ALIGN_CEIL(tdata->plaintext.len, 16);
-
- plaintext = (uint8_t *)rte_pktmbuf_append(ut_params->ibuf,
- plaintext_pad_len);
- memcpy(plaintext, tdata->plaintext.data, tdata->plaintext.len);
-
- TEST_HEXDUMP(stdout, "plaintext:", plaintext, tdata->plaintext.len);
-
- /* Create GCM opertaion */
- retval = create_gcm_operation(RTE_CRYPTO_CIPHER_OP_ENCRYPT,
- tdata->auth_tag.data, tdata->auth_tag.len,
- tdata->iv.data, tdata->iv.len,
- tdata->aad.data, tdata->aad.len,
- tdata->plaintext.len, plaintext_pad_len);
+ /* Create GCM operation */
+ retval = create_gcm_operation(RTE_CRYPTO_CIPHER_OP_ENCRYPT, tdata);
if (retval < 0)
return retval;
@@ -4054,14 +4057,18 @@ test_mb_AES_GCM_authenticated_encryption(const struct gcm_test_data *tdata)
TEST_ASSERT_EQUAL(ut_params->op->status, RTE_CRYPTO_OP_STATUS_SUCCESS,
"crypto op processing failed");
+ plaintext_pad_len = RTE_ALIGN_CEIL(tdata->plaintext.len, 16);
+
if (ut_params->op->sym->m_dst) {
ciphertext = rte_pktmbuf_mtod(ut_params->op->sym->m_dst,
uint8_t *);
auth_tag = rte_pktmbuf_mtod_offset(ut_params->op->sym->m_dst,
uint8_t *, plaintext_pad_len);
} else {
- ciphertext = plaintext;
- auth_tag = plaintext + plaintext_pad_len;
+ ciphertext = rte_pktmbuf_mtod_offset(ut_params->op->sym->m_src,
+ uint8_t *,
+ ut_params->op->sym->cipher.data.offset);
+ auth_tag = ciphertext + plaintext_pad_len;
}
TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, tdata->ciphertext.len);
@@ -4127,15 +4134,68 @@ test_mb_AES_GCM_authenticated_encryption_test_case_7(void)
}
static int
+test_mb_AES_GCM_auth_encryption_test_case_256_1(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_256_1);
+}
+
+static int
+test_mb_AES_GCM_auth_encryption_test_case_256_2(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_256_2);
+}
+
+static int
+test_mb_AES_GCM_auth_encryption_test_case_256_3(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_256_3);
+}
+
+static int
+test_mb_AES_GCM_auth_encryption_test_case_256_4(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_256_4);
+}
+
+static int
+test_mb_AES_GCM_auth_encryption_test_case_256_5(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_256_5);
+}
+
+static int
+test_mb_AES_GCM_auth_encryption_test_case_256_6(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_256_6);
+}
+
+static int
+test_mb_AES_GCM_auth_encryption_test_case_256_7(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_256_7);
+}
+
+static int
+test_mb_AES_GCM_auth_encryption_test_case_aad_1(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_aad_1);
+}
+
+static int
+test_mb_AES_GCM_auth_encryption_test_case_aad_2(void)
+{
+ return test_mb_AES_GCM_authenticated_encryption(&gcm_test_case_aad_2);
+}
+
+static int
test_mb_AES_GCM_authenticated_decryption(const struct gcm_test_data *tdata)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
struct crypto_unittest_params *ut_params = &unittest_params;
int retval;
-
- uint8_t *plaintext, *ciphertext;
- uint16_t ciphertext_pad_len;
+ uint8_t *plaintext;
+ uint32_t i;
/* Create GCM session */
retval = create_gcm_session(ts_params->valid_devs[0],
@@ -4146,31 +4206,23 @@ test_mb_AES_GCM_authenticated_decryption(const struct gcm_test_data *tdata)
if (retval < 0)
return retval;
-
/* alloc mbuf and set payload */
- ut_params->ibuf = rte_pktmbuf_alloc(ts_params->mbuf_pool);
+ if (tdata->aad.len > MBUF_SIZE) {
+ ut_params->ibuf = rte_pktmbuf_alloc(ts_params->large_mbuf_pool);
+ /* Populate full size of add data */
+ for (i = 32; i < GMC_MAX_AAD_LENGTH; i += 32)
+ memcpy(&tdata->aad.data[i], &tdata->aad.data[0], 32);
+ } else
+ ut_params->ibuf = rte_pktmbuf_alloc(ts_params->mbuf_pool);
memset(rte_pktmbuf_mtod(ut_params->ibuf, uint8_t *), 0,
rte_pktmbuf_tailroom(ut_params->ibuf));
- ciphertext_pad_len = RTE_ALIGN_CEIL(tdata->ciphertext.len, 16);
-
- ciphertext = (uint8_t *)rte_pktmbuf_append(ut_params->ibuf,
- ciphertext_pad_len);
- memcpy(ciphertext, tdata->ciphertext.data, tdata->ciphertext.len);
-
- TEST_HEXDUMP(stdout, "ciphertext:", ciphertext, tdata->ciphertext.len);
-
- /* Create GCM opertaion */
- retval = create_gcm_operation(RTE_CRYPTO_CIPHER_OP_DECRYPT,
- tdata->auth_tag.data, tdata->auth_tag.len,
- tdata->iv.data, tdata->iv.len,
- tdata->aad.data, tdata->aad.len,
- tdata->ciphertext.len, ciphertext_pad_len);
+ /* Create GCM operation */
+ retval = create_gcm_operation(RTE_CRYPTO_CIPHER_OP_DECRYPT, tdata);
if (retval < 0)
return retval;
-
rte_crypto_op_attach_sym_session(ut_params->op, ut_params->sess);
ut_params->op->sym->m_src = ut_params->ibuf;
@@ -4186,7 +4238,9 @@ test_mb_AES_GCM_authenticated_decryption(const struct gcm_test_data *tdata)
plaintext = rte_pktmbuf_mtod(ut_params->op->sym->m_dst,
uint8_t *);
else
- plaintext = ciphertext;
+ plaintext = rte_pktmbuf_mtod_offset(ut_params->op->sym->m_src,
+ uint8_t *,
+ ut_params->op->sym->cipher.data.offset);
TEST_HEXDUMP(stdout, "plaintext:", plaintext, tdata->ciphertext.len);
@@ -4246,6 +4300,60 @@ test_mb_AES_GCM_authenticated_decryption_test_case_7(void)
}
static int
+test_mb_AES_GCM_auth_decryption_test_case_256_1(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_256_1);
+}
+
+static int
+test_mb_AES_GCM_auth_decryption_test_case_256_2(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_256_2);
+}
+
+static int
+test_mb_AES_GCM_auth_decryption_test_case_256_3(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_256_3);
+}
+
+static int
+test_mb_AES_GCM_auth_decryption_test_case_256_4(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_256_4);
+}
+
+static int
+test_mb_AES_GCM_auth_decryption_test_case_256_5(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_256_5);
+}
+
+static int
+test_mb_AES_GCM_auth_decryption_test_case_256_6(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_256_6);
+}
+
+static int
+test_mb_AES_GCM_auth_decryption_test_case_256_7(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_256_7);
+}
+
+static int
+test_mb_AES_GCM_auth_decryption_test_case_aad_1(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_aad_1);
+}
+
+static int
+test_mb_AES_GCM_auth_decryption_test_case_aad_2(void)
+{
+ return test_mb_AES_GCM_authenticated_decryption(&gcm_test_case_aad_2);
+}
+
+static int
test_stats(void)
{
struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -6283,6 +6391,7 @@ static struct unit_test_suite cryptodev_aesni_gcm_testsuite = {
.teardown = testsuite_teardown,
.unit_test_cases = {
/** AES GCM Authenticated Encryption */
+
TEST_CASE_ST(ut_setup, ut_teardown,
test_mb_AES_GCM_authenticated_encryption_test_case_1),
TEST_CASE_ST(ut_setup, ut_teardown,
@@ -6314,6 +6423,50 @@ static struct unit_test_suite cryptodev_aesni_gcm_testsuite = {
TEST_CASE_ST(ut_setup, ut_teardown,
test_mb_AES_GCM_authenticated_decryption_test_case_7),
+ /** AES GCM Authenticated Encryption 256bites key */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_256_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_256_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_256_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_256_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_256_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_256_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_256_7),
+
+ /** AES GCM Authenticated Decryption 256bites key */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_256_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_256_2),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_256_3),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_256_4),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_256_5),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_256_6),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_256_7),
+
+ /** AES GCM Authenticated Encryption big aad size */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_aad_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_encryption_test_case_aad_2),
+
+ /** AES GCM Authenticated Encryption big aad size */
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_aad_1),
+ TEST_CASE_ST(ut_setup, ut_teardown,
+ test_mb_AES_GCM_auth_decryption_test_case_aad_2),
+
TEST_CASES_END() /**< NULL terminate unit test array */
}
};
diff --git a/app/test/test_cryptodev_gcm_test_vectors.h b/app/test/test_cryptodev_gcm_test_vectors.h
index b404242..b6f81f3 100644
--- a/app/test/test_cryptodev_gcm_test_vectors.h
+++ b/app/test/test_cryptodev_gcm_test_vectors.h
@@ -34,6 +34,16 @@
#define TEST_CRYPTODEV_GCM_TEST_VECTORS_H_
#define GMAC_LARGE_PLAINTEXT_LENGTH 65376
+#define GMC_MAX_AAD_LENGTH 65536
+#define GMC_LARGE_AAD_LENGTH 65296
+
+static uint8_t gcm_aad_zero_text[GMC_MAX_AAD_LENGTH] = { 0 };
+
+static uint8_t gcm_aad_text[GMC_MAX_AAD_LENGTH] = {
+ 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
+ 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
+ 0x00, 0xf1, 0xe2, 0xd3, 0xc4, 0xb5, 0xa6, 0x97,
+ 0x88, 0x79, 0x6a, 0x5b, 0x4c, 0x3d, 0x2e, 0x1f };
struct gcm_test_data {
struct {
@@ -47,7 +57,7 @@ struct gcm_test_data {
} iv;
struct {
- uint8_t data[64];
+ uint8_t *data;
unsigned len;
} aad;
@@ -111,7 +121,7 @@ static const struct gcm_test_data gcm_test_case_1 = {
.len = 12
},
.aad = {
- .data = { 0 },
+ .data = gcm_aad_zero_text,
.len = 0
},
.plaintext = {
@@ -148,7 +158,7 @@ static const struct gcm_test_data gcm_test_case_2 = {
.len = 12
},
.aad = {
- .data = { 0 },
+ .data = gcm_aad_zero_text,
.len = 0
},
.plaintext = {
@@ -186,7 +196,7 @@ static const struct gcm_test_data gcm_test_case_3 = {
.len = 12
},
.aad = {
- .data = { 0 },
+ .data = gcm_aad_zero_text,
.len = 0
},
.plaintext = {
@@ -238,8 +248,7 @@ static const struct gcm_test_data gcm_test_case_4 = {
.len = 12
},
.aad = {
- .data = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .data = gcm_aad_zero_text,
.len = 8
},
.plaintext = {
@@ -294,8 +303,7 @@ static const struct gcm_test_data gcm_test_case_5 = {
.len = 12
},
.aad = {
- .data = {
- 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef },
+ .data = gcm_aad_text,
.len = 8
},
.plaintext = {
@@ -346,15 +354,11 @@ static const struct gcm_test_data gcm_test_case_6 = {
.iv = {
.data = {
0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
- 0xde, 0xca, 0xf8, 0x88
- },
+ 0xde, 0xca, 0xf8, 0x88 },
.len = 12
},
.aad = {
- .data = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
- },
+ .data = gcm_aad_zero_text,
.len = 12
},
.plaintext = {
@@ -409,10 +413,7 @@ static const struct gcm_test_data gcm_test_case_7 = {
.len = 12
},
.aad = {
- .data = {
- 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
- 0xfe, 0xed, 0xfa, 0xce
- },
+ .data = gcm_aad_text,
.len = 12
},
.plaintext = {
@@ -450,6 +451,450 @@ static const struct gcm_test_data gcm_test_case_7 = {
}
};
+/** AES-256 Test Vectors */
+static const struct gcm_test_data gcm_test_case_256_1 = {
+ .key = {
+ .data = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .len = 32
+ },
+ .iv = {
+ .data = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_zero_text,
+ .len = 0
+ },
+ .plaintext = {
+ .data = { 0x00 },
+ .len = 0
+ },
+ .ciphertext = {
+ .data = { 0x00 },
+ .len = 0
+ },
+ .auth_tag = {
+ .data = {
+ 0x53, 0x0F, 0x8A, 0xFB, 0xC7, 0x45, 0x36, 0xB9,
+ 0xA9, 0x63, 0xB4, 0xF1, 0xC4, 0xCB, 0x73, 0x8B },
+ .len = 16
+ }
+};
+
+/** AES-256 Test Vectors */
+static const struct gcm_test_data gcm_test_case_256_2 = {
+ .key = {
+ .data = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .len = 32
+ },
+ .iv = {
+ .data = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_zero_text,
+ .len = 0
+ },
+ .plaintext = {
+ .data = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ .len = 16
+ },
+ .ciphertext = {
+ .data = {
+ 0xCE, 0xA7, 0x40, 0x3D, 0x4D, 0x60, 0x6B, 0x6E,
+ 0x07, 0x4E, 0xC5, 0xD3, 0xBA, 0xF3, 0x9D, 0x18 },
+ .len = 16
+ },
+ .auth_tag = {
+ .data = {
+ 0xD0, 0xD1, 0xC8, 0xA7, 0x99, 0x99, 0x6B, 0xF0,
+ 0x26, 0x5B, 0x98, 0xB5, 0xD4, 0x8A, 0xB9, 0x19 },
+ .len = 16
+ }
+};
+
+/** AES-256 Test Vectors */
+static const struct gcm_test_data gcm_test_case_256_3 = {
+ .key = {
+ .data = {
+ 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+ 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a },
+ .len = 32
+ },
+ .iv = {
+ .data = {
+ 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+ 0xde, 0xca, 0xf8, 0x88 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_zero_text,
+ .len = 0
+ },
+ .plaintext = {
+ .data = {
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+ 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+ 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+ 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+ 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+ 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+ 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 },
+ .len = 64
+ },
+ .ciphertext = {
+ .data = {
+ 0x05, 0xA2, 0x39, 0xA5, 0xE1, 0x1A, 0x74, 0xEA,
+ 0x6B, 0x2A, 0x55, 0xF6, 0xD7, 0x88, 0x44, 0x7E,
+ 0x93, 0x7E, 0x23, 0x64, 0x8D, 0xF8, 0xD4, 0x04,
+ 0x3B, 0x40, 0xEF, 0x6D, 0x7C, 0x6B, 0xF3, 0xB9,
+ 0x50, 0x15, 0x97, 0x5D, 0xB8, 0x28, 0xA1, 0xD5,
+ 0x22, 0xDE, 0x36, 0x26, 0xD0, 0x6A, 0x7A, 0xC0,
+ 0xB5, 0x14, 0x36, 0xAF, 0x3A, 0xC6, 0x50, 0xAB,
+ 0xFA, 0x47, 0xC8, 0x2E, 0xF0, 0x68, 0xE1, 0x3E },
+ .len = 64
+ },
+ .auth_tag = {
+ .data = {
+ 0x64, 0xAF, 0x1D, 0xFB, 0xE8, 0x0D, 0x37, 0xD8,
+ 0x92, 0xC3, 0xB9, 0x1D, 0xD3, 0x08, 0xAB, 0xFC },
+ .len = 16
+ }
+};
+
+/** AES-256 Test Vectors */
+static const struct gcm_test_data gcm_test_case_256_4 = {
+ .key = {
+ .data = {
+ 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+ 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a },
+ .len = 32
+ },
+ .iv = {
+ .data = {
+ 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+ 0xde, 0xca, 0xf8, 0x88 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_zero_text,
+ .len = 8
+ },
+ .plaintext = {
+ .data = {
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+ 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+ 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+ 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+ 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+ 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+ 0xba, 0x63, 0x7b, 0x39 },
+ .len = 60
+ },
+ .ciphertext = {
+ .data = {
+ 0x05, 0xA2, 0x39, 0xA5, 0xE1, 0x1A, 0x74, 0xEA,
+ 0x6B, 0x2A, 0x55, 0xF6, 0xD7, 0x88, 0x44, 0x7E,
+ 0x93, 0x7E, 0x23, 0x64, 0x8D, 0xF8, 0xD4, 0x04,
+ 0x3B, 0x40, 0xEF, 0x6D, 0x7C, 0x6B, 0xF3, 0xB9,
+ 0x50, 0x15, 0x97, 0x5D, 0xB8, 0x28, 0xA1, 0xD5,
+ 0x22, 0xDE, 0x36, 0x26, 0xD0, 0x6A, 0x7A, 0xC0,
+ 0xB5, 0x14, 0x36, 0xAF, 0x3A, 0xC6, 0x50, 0xAB,
+ 0xFA, 0x47, 0xC8, 0x2E },
+ .len = 60
+ },
+ .auth_tag = {
+ .data = {
+ 0x63, 0x16, 0x91, 0xAE, 0x17, 0x05, 0x5E, 0xA6,
+ 0x6D, 0x0A, 0x51, 0xE2, 0x50, 0x21, 0x85, 0x4A },
+ .len = 16
+ }
+
+};
+
+/** AES-256 Test Vectors */
+static const struct gcm_test_data gcm_test_case_256_5 = {
+ .key = {
+ .data = {
+ 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+ 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a },
+ .len = 32
+ },
+ .iv = {
+ .data = {
+ 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+ 0xde, 0xca, 0xf8, 0x88 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_text,
+ .len = 8
+ },
+ .plaintext = {
+ .data = {
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+ 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+ 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+ 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+ 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+ 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+ 0xba, 0x63, 0x7b, 0x39 },
+ .len = 60
+ },
+ .ciphertext = {
+ .data = {
+ 0x05, 0xA2, 0x39, 0xA5, 0xE1, 0x1A, 0x74, 0xEA,
+ 0x6B, 0x2A, 0x55, 0xF6, 0xD7, 0x88, 0x44, 0x7E,
+ 0x93, 0x7E, 0x23, 0x64, 0x8D, 0xF8, 0xD4, 0x04,
+ 0x3B, 0x40, 0xEF, 0x6D, 0x7C, 0x6B, 0xF3, 0xB9,
+ 0x50, 0x15, 0x97, 0x5D, 0xB8, 0x28, 0xA1, 0xD5,
+ 0x22, 0xDE, 0x36, 0x26, 0xD0, 0x6A, 0x7A, 0xC0,
+ 0xB5, 0x14, 0x36, 0xAF, 0x3A, 0xC6, 0x50, 0xAB,
+ 0xFA, 0x47, 0xC8, 0x2E },
+ .len = 60
+ },
+ .auth_tag = {
+ .data = {
+ 0xA7, 0x99, 0xAC, 0xB8, 0x27, 0xDA, 0xB1, 0x82,
+ 0x79, 0xFD, 0x83, 0x73, 0x52, 0x4D, 0xDB, 0xF1 },
+ .len = 16
+ }
+
+};
+
+/** AES-256 Test Vectors */
+static const struct gcm_test_data gcm_test_case_256_6 = {
+ .key = {
+ .data = {
+ 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+ 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a },
+ .len = 32
+ },
+ .iv = {
+ .data = {
+ 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+ 0xde, 0xca, 0xf8, 0x88 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_zero_text,
+ .len = 12
+ },
+ .plaintext = {
+ .data = {
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+ 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+ 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+ 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+ 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+ 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+ 0xba, 0x63, 0x7b, 0x39 },
+ .len = 60
+ },
+ .ciphertext = {
+ .data = {
+ 0x05, 0xA2, 0x39, 0xA5, 0xE1, 0x1A, 0x74, 0xEA,
+ 0x6B, 0x2A, 0x55, 0xF6, 0xD7, 0x88, 0x44, 0x7E,
+ 0x93, 0x7E, 0x23, 0x64, 0x8D, 0xF8, 0xD4, 0x04,
+ 0x3B, 0x40, 0xEF, 0x6D, 0x7C, 0x6B, 0xF3, 0xB9,
+ 0x50, 0x15, 0x97, 0x5D, 0xB8, 0x28, 0xA1, 0xD5,
+ 0x22, 0xDE, 0x36, 0x26, 0xD0, 0x6A, 0x7A, 0xC0,
+ 0xB5, 0x14, 0x36, 0xAF, 0x3A, 0xC6, 0x50, 0xAB,
+ 0xFA, 0x47, 0xC8, 0x2E },
+ .len = 60
+ },
+ .auth_tag = {
+ .data = {
+ 0x5D, 0xA5, 0x0E, 0x53, 0x64, 0x7F, 0x3F, 0xAE,
+ 0x1A, 0x1F, 0xC0, 0xB0, 0xD8, 0xBE, 0xF2, 0x64 },
+ .len = 16
+ }
+};
+
+/** AES-256 Test Vectors */
+static const struct gcm_test_data gcm_test_case_256_7 = {
+ .key = {
+ .data = {
+ 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+ 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a },
+ .len = 32
+ },
+ .iv = {
+ .data = {
+ 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+ 0xde, 0xca, 0xf8, 0x88 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_text,
+ .len = 12
+ },
+ .plaintext = {
+ .data = {
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+ 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+ 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+ 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+ 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+ 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+ 0xba, 0x63, 0x7b, 0x39 },
+ .len = 60
+ },
+ .ciphertext = {
+ .data = {
+ 0x05, 0xA2, 0x39, 0xA5, 0xE1, 0x1A, 0x74, 0xEA,
+ 0x6B, 0x2A, 0x55, 0xF6, 0xD7, 0x88, 0x44, 0x7E,
+ 0x93, 0x7E, 0x23, 0x64, 0x8D, 0xF8, 0xD4, 0x04,
+ 0x3B, 0x40, 0xEF, 0x6D, 0x7C, 0x6B, 0xF3, 0xB9,
+ 0x50, 0x15, 0x97, 0x5D, 0xB8, 0x28, 0xA1, 0xD5,
+ 0x22, 0xDE, 0x36, 0x26, 0xD0, 0x6A, 0x7A, 0xC0,
+ 0xB5, 0x14, 0x36, 0xAF, 0x3A, 0xC6, 0x50, 0xAB,
+ 0xFA, 0x47, 0xC8, 0x2E },
+ .len = 60
+ },
+ .auth_tag = {
+ .data = {
+ 0x4E, 0xD0, 0x91, 0x95, 0x83, 0xA9, 0x38, 0x72,
+ 0x09, 0xA9, 0xCE, 0x5F, 0x89, 0x06, 0x4E, 0xC8 },
+ .len = 16
+ }
+};
+
+/** variable AAD AES-128 Test Vectors */
+static const struct gcm_test_data gcm_test_case_aad_1 = {
+ .key = {
+ .data = {
+ 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+ 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 },
+ .len = 16
+ },
+ .iv = {
+ .data = {
+ 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+ 0xde, 0xca, 0xf8, 0x88 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_text,
+ .len = GMC_LARGE_AAD_LENGTH
+ },
+ .plaintext = {
+ .data = {
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+ 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+ 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+ 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+ 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+ 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+ 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 },
+ .len = 64
+ },
+ .ciphertext = {
+ .data = {
+ 0x42, 0x83, 0x1E, 0xC2, 0x21, 0x77, 0x74, 0x24,
+ 0x4B, 0x72, 0x21, 0xB7, 0x84, 0xD0, 0xD4, 0x9C,
+ 0xE3, 0xAA, 0x21, 0x2F, 0x2C, 0x02, 0xA4, 0xE0,
+ 0x35, 0xC1, 0x7E, 0x23, 0x29, 0xAC, 0xA1, 0x2E,
+ 0x21, 0xD5, 0x14, 0xB2, 0x54, 0x66, 0x93, 0x1C,
+ 0x7D, 0x8F, 0x6A, 0x5A, 0xAC, 0x84, 0xAA, 0x05,
+ 0x1B, 0xA3, 0x0B, 0x39, 0x6A, 0x0A, 0xAC, 0x97,
+ 0x3D, 0x58, 0xE0, 0x91, 0x47, 0x3F, 0x59, 0x85
+ },
+ .len = 64
+ },
+ .auth_tag = {
+ .data = {
+ 0xCA, 0x70, 0xAF, 0x96, 0xA8, 0x5D, 0x40, 0x47,
+ 0x0C, 0x3C, 0x48, 0xF5, 0xF0, 0xF5, 0xA5, 0x7D
+ },
+ .len = 16
+ }
+};
+
+/** variable AAD AES-256 Test Vectors */
+static const struct gcm_test_data gcm_test_case_aad_2 = {
+ .key = {
+ .data = {
+ 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+ 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a },
+ .len = 32
+ },
+ .iv = {
+ .data = {
+ 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+ 0xde, 0xca, 0xf8, 0x88 },
+ .len = 12
+ },
+ .aad = {
+ .data = gcm_aad_text,
+ .len = GMC_LARGE_AAD_LENGTH
+ },
+ .plaintext = {
+ .data = {
+ 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+ 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+ 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+ 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+ 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+ 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+ 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+ 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55 },
+ .len = 64
+ },
+ .ciphertext = {
+ .data = {
+ 0x05, 0xA2, 0x39, 0xA5, 0xE1, 0x1A, 0x74, 0xEA,
+ 0x6B, 0x2A, 0x55, 0xF6, 0xD7, 0x88, 0x44, 0x7E,
+ 0x93, 0x7E, 0x23, 0x64, 0x8D, 0xF8, 0xD4, 0x04,
+ 0x3B, 0x40, 0xEF, 0x6D, 0x7C, 0x6B, 0xF3, 0xB9,
+ 0x50, 0x15, 0x97, 0x5D, 0xB8, 0x28, 0xA1, 0xD5,
+ 0x22, 0xDE, 0x36, 0x26, 0xD0, 0x6A, 0x7A, 0xC0,
+ 0xB5, 0x14, 0x36, 0xAF, 0x3A, 0xC6, 0x50, 0xAB,
+ 0xFA, 0x47, 0xC8, 0x2E, 0xF0, 0x68, 0xE1, 0x3E
+ },
+ .len = 64
+ },
+ .auth_tag = {
+ .data = {
+ 0xBA, 0x06, 0xDA, 0xA1, 0x91, 0xE1, 0xFE, 0x22,
+ 0x59, 0xDA, 0x67, 0xAF, 0x9D, 0xA5, 0x43, 0x94
+ },
+ .len = 16
+ }
+};
+
/** GMAC Test Vectors */
static uint8_t gmac_plaintext[GMAC_LARGE_PLAINTEXT_LENGTH] = {
0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
diff --git a/doc/guides/cryptodevs/aesni_gcm.rst b/doc/guides/cryptodevs/aesni_gcm.rst
index 04bf43c..3d43fad 100644
--- a/doc/guides/cryptodevs/aesni_gcm.rst
+++ b/doc/guides/cryptodevs/aesni_gcm.rst
@@ -32,10 +32,8 @@ AES-NI GCM Crypto Poll Mode Driver
The AES-NI GCM PMD (**librte_pmd_aesni_gcm**) provides poll mode crypto driver
-support for utilizing Intel multi buffer library (see AES-NI Multi-buffer PMD documentation
-to learn more about it, including installation).
-
-The AES-NI GCM PMD has current only been tested on Fedora 21 64-bit with gcc.
+support for utilizing Intel ISA-L crypto library, which provides operation acceleration
+through the AES-NI instruction sets for AES-GCM authenticated cipher algorithm.
Features
--------
@@ -50,15 +48,19 @@ Authentication algorithms:
* RTE_CRYPTO_AUTH_AES_GCM
+Installation
+------------
+
+To build DPDK with the AESNI_GCM_PMD the user is required to install
+the ``libisal_crypto`` library in the build environment.
+For download and more details please visit `<https://github.com/01org/isa-l_crypto>`_.
+
Initialization
--------------
In order to enable this virtual crypto PMD, user must:
-* Export the environmental variable AESNI_MULTI_BUFFER_LIB_PATH with the path where
- the library was extracted.
-
-* Build the multi buffer library (go to Installation section in AES-NI MB PMD documentation).
+* Install the ISA-L crypto library (explained in Installation section).
* Set CONFIG_RTE_LIBRTE_PMD_AESNI_GCM=y in config/common_base.
diff --git a/drivers/crypto/aesni_gcm/Makefile b/drivers/crypto/aesni_gcm/Makefile
index 5898cae..fb17fbf 100644
--- a/drivers/crypto/aesni_gcm/Makefile
+++ b/drivers/crypto/aesni_gcm/Makefile
@@ -31,9 +31,6 @@
include $(RTE_SDK)/mk/rte.vars.mk
ifneq ($(MAKECMDGOALS),clean)
-ifeq ($(AESNI_MULTI_BUFFER_LIB_PATH),)
-$(error "Please define AESNI_MULTI_BUFFER_LIB_PATH environment variable")
-endif
endif
# library name
@@ -50,10 +47,7 @@ LIBABIVER := 1
EXPORT_MAP := rte_pmd_aesni_gcm_version.map
# external library dependencies
-CFLAGS += -I$(AESNI_MULTI_BUFFER_LIB_PATH)
-CFLAGS += -I$(AESNI_MULTI_BUFFER_LIB_PATH)/include
-LDLIBS += -L$(AESNI_MULTI_BUFFER_LIB_PATH) -lIPSec_MB
-LDLIBS += -lcrypto
+LDLIBS += -lisal_crypto
# library source files
SRCS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += aesni_gcm_pmd.c
diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_ops.h b/drivers/crypto/aesni_gcm/aesni_gcm_ops.h
index c399068..ea8a155 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_ops.h
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_ops.h
@@ -37,91 +37,12 @@
#define LINUX
#endif
-#include <gcm_defines.h>
-#include <aux_funcs.h>
-
-/** Supported vector modes */
-enum aesni_gcm_vector_mode {
- RTE_AESNI_GCM_NOT_SUPPORTED = 0,
- RTE_AESNI_GCM_SSE,
- RTE_AESNI_GCM_AVX,
- RTE_AESNI_GCM_AVX2
-};
-
-typedef void (*aes_keyexp_128_enc_t)(void *key, void *enc_exp_keys);
-
-typedef void (*aesni_gcm_t)(gcm_data *my_ctx_data, u8 *out, const u8 *in,
- u64 plaintext_len, u8 *iv, const u8 *aad, u64 aad_len,
- u8 *auth_tag, u64 auth_tag_len);
-
-typedef void (*aesni_gcm_precomp_t)(gcm_data *my_ctx_data, u8 *hash_subkey);
-
-/** GCM library function pointer table */
-struct aesni_gcm_ops {
- struct {
- struct {
- aes_keyexp_128_enc_t aes128_enc;
- /**< AES128 enc key expansion */
- } keyexp;
- /**< Key expansion functions */
- } aux; /**< Auxiliary functions */
-
- struct {
- aesni_gcm_t enc; /**< GCM encode function pointer */
- aesni_gcm_t dec; /**< GCM decode function pointer */
- aesni_gcm_precomp_t precomp; /**< GCM pre-compute */
- } gcm; /**< GCM functions */
-};
-
-
-static const struct aesni_gcm_ops gcm_ops[] = {
- [RTE_AESNI_GCM_NOT_SUPPORTED] = {
- .aux = {
- .keyexp = {
- NULL
- }
- },
- .gcm = {
- NULL
- }
- },
- [RTE_AESNI_GCM_SSE] = {
- .aux = {
- .keyexp = {
- aes_keyexp_128_enc_sse
- }
- },
- .gcm = {
- aesni_gcm_enc_sse,
- aesni_gcm_dec_sse,
- aesni_gcm_precomp_sse
- }
- },
- [RTE_AESNI_GCM_AVX] = {
- .aux = {
- .keyexp = {
- aes_keyexp_128_enc_avx,
- }
- },
- .gcm = {
- aesni_gcm_enc_avx_gen2,
- aesni_gcm_dec_avx_gen2,
- aesni_gcm_precomp_avx_gen2
- }
- },
- [RTE_AESNI_GCM_AVX2] = {
- .aux = {
- .keyexp = {
- aes_keyexp_128_enc_avx2,
- }
- },
- .gcm = {
- aesni_gcm_enc_avx_gen4,
- aesni_gcm_dec_avx_gen4,
- aesni_gcm_precomp_avx_gen4
- }
- }
-};
+#include <isa-l_crypto/aes_gcm.h>
+typedef void (*aesni_gcm_t)(struct gcm_data *my_ctx_data,
+ uint8_t *out, uint8_t const *in, uint64_t plaintext_len,
+ uint8_t *iv,
+ uint8_t const *aad, uint64_t aad_len,
+ uint8_t *auth_tag, uint64_t auth_tag_len);
#endif /* _AESNI_GCM_OPS_H_ */
diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
index dba5e15..f5627f5 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd.c
@@ -30,8 +30,6 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include <openssl/aes.h>
-
#include <rte_common.h>
#include <rte_config.h>
#include <rte_hexdump.h>
@@ -43,6 +41,18 @@
#include "aesni_gcm_pmd_private.h"
+/** GCM encode function pointer table */
+static const aesni_gcm_t aesni_gcm_enc[] = {
+ [AESNI_GCM_KEY_128] = aesni_gcm128_enc,
+ [AESNI_GCM_KEY_256] = aesni_gcm256_enc
+};
+
+/** GCM decode function pointer table */
+static const aesni_gcm_t aesni_gcm_dec[] = {
+ [AESNI_GCM_KEY_128] = aesni_gcm128_dec,
+ [AESNI_GCM_KEY_256] = aesni_gcm256_dec
+};
+
/**
* Global static parameter used to create a unique name for each AES-NI multi
* buffer crypto device.
@@ -64,26 +74,6 @@ create_unique_device_name(char *name, size_t size)
return 0;
}
-static int
-aesni_gcm_calculate_hash_sub_key(uint8_t *hsubkey, unsigned hsubkey_length,
- uint8_t *aeskey, unsigned aeskey_length)
-{
- uint8_t key[aeskey_length] __rte_aligned(16);
- AES_KEY enc_key;
-
- if (hsubkey_length % 16 != 0 && aeskey_length % 16 != 0)
- return -EFAULT;
-
- memcpy(key, aeskey, aeskey_length);
-
- if (AES_set_encrypt_key(key, aeskey_length << 3, &enc_key) != 0)
- return -EFAULT;
-
- AES_encrypt(hsubkey, hsubkey, &enc_key);
-
- return 0;
-}
-
/** Get xform chain order */
static int
aesni_gcm_get_mode(const struct rte_crypto_sym_xform *xform)
@@ -111,15 +101,12 @@ aesni_gcm_get_mode(const struct rte_crypto_sym_xform *xform)
/** Parse crypto xform chain and set private session parameters */
int
-aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,
- struct aesni_gcm_session *sess,
+aesni_gcm_set_session_parameters(struct aesni_gcm_session *sess,
const struct rte_crypto_sym_xform *xform)
{
const struct rte_crypto_sym_xform *auth_xform = NULL;
const struct rte_crypto_sym_xform *cipher_xform = NULL;
- uint8_t hsubkey[16] __rte_aligned(16) = { 0 };
-
/* Select Crypto operation - hash then cipher / cipher then hash */
switch (aesni_gcm_get_mode(xform)) {
case AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION:
@@ -159,17 +146,22 @@ aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,
return -EINVAL;
}
- /* Expand GCM AES128 key */
- (*gcm_ops->aux.keyexp.aes128_enc)(cipher_xform->cipher.key.data,
- sess->gdata.expanded_keys);
+ /* Check key length, calculate GCM pre-compute. */
+ switch (cipher_xform->cipher.key.length) {
+ case 16:
+ aesni_gcm128_pre(cipher_xform->cipher.key.data, &sess->gdata);
+ sess->key = AESNI_GCM_KEY_128;
- /* Calculate hash sub key here */
- aesni_gcm_calculate_hash_sub_key(hsubkey, sizeof(hsubkey),
- cipher_xform->cipher.key.data,
- cipher_xform->cipher.key.length);
+ break;
+ case 32:
+ aesni_gcm256_pre(cipher_xform->cipher.key.data, &sess->gdata);
+ sess->key = AESNI_GCM_KEY_256;
- /* Calculate GCM pre-compute */
- (*gcm_ops->gcm.precomp)(&sess->gdata, hsubkey);
+ break;
+ default:
+ GCM_LOG_ERR("Unsupported cipher key length");
+ return -1;
+ }
return 0;
}
@@ -195,8 +187,8 @@ aesni_gcm_get_session(struct aesni_gcm_qp *qp, struct rte_crypto_sym_op *op)
sess = (struct aesni_gcm_session *)
((struct rte_cryptodev_session *)_sess)->_private;
- if (unlikely(aesni_gcm_set_session_parameters(qp->ops,
- sess, op->xform) != 0)) {
+ if (unlikely(aesni_gcm_set_session_parameters(sess,
+ op->xform) != 0)) {
rte_mempool_put(qp->sess_mp, _sess);
sess = NULL;
}
@@ -216,7 +208,7 @@ aesni_gcm_get_session(struct aesni_gcm_qp *qp, struct rte_crypto_sym_op *op)
*
*/
static int
-process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_sym_op *op,
+process_gcm_crypto_op(struct rte_crypto_sym_op *op,
struct aesni_gcm_session *session)
{
uint8_t *src, *dst;
@@ -244,12 +236,6 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_sym_op *op,
op->cipher.iv.data[15] = 1;
}
- if (op->auth.aad.length != 12 && op->auth.aad.length != 8 &&
- op->auth.aad.length != 0) {
- GCM_LOG_ERR("iv");
- return -1;
- }
-
if (op->auth.digest.length != 16 &&
op->auth.digest.length != 12 &&
op->auth.digest.length != 8 &&
@@ -260,7 +246,7 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_sym_op *op,
if (session->op == AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION) {
- (*qp->ops->gcm.enc)(&session->gdata, dst, src,
+ aesni_gcm_enc[session->key](&session->gdata, dst, src,
(uint64_t)op->cipher.data.length,
op->cipher.iv.data,
op->auth.aad.data,
@@ -276,7 +262,7 @@ process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_sym_op *op,
return -1;
}
- (*qp->ops->gcm.dec)(&session->gdata, dst, src,
+ aesni_gcm_dec[session->key](&session->gdata, dst, src,
(uint64_t)op->cipher.data.length,
op->cipher.iv.data,
op->auth.aad.data,
@@ -375,7 +361,7 @@ aesni_gcm_pmd_enqueue_burst(void *queue_pair,
break;
}
- retval = process_gcm_crypto_op(qp, ops[i]->sym, sess);
+ retval = process_gcm_crypto_op(ops[i]->sym, sess);
if (retval < 0) {
ops[i]->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
qp->qp_stats.enqueue_err_count++;
@@ -413,7 +399,6 @@ aesni_gcm_create(const char *name,
struct rte_cryptodev *dev;
char crypto_dev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
struct aesni_gcm_private *internals;
- enum aesni_gcm_vector_mode vector_mode;
/* Check CPU for support for AES instruction set */
if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) {
@@ -421,18 +406,6 @@ aesni_gcm_create(const char *name,
return -EFAULT;
}
- /* Check CPU for supported vector instruction set */
- if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
- vector_mode = RTE_AESNI_GCM_AVX2;
- else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))
- vector_mode = RTE_AESNI_GCM_AVX;
- else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
- vector_mode = RTE_AESNI_GCM_SSE;
- else {
- GCM_LOG_ERR("Vector instructions are not supported by CPU");
- return -EFAULT;
- }
-
/* create a unique device name */
if (create_unique_device_name(crypto_dev_name,
RTE_CRYPTODEV_NAME_MAX_LEN) != 0) {
@@ -459,25 +432,8 @@ aesni_gcm_create(const char *name,
RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
RTE_CRYPTODEV_FF_CPU_AESNI;
- switch (vector_mode) {
- case RTE_AESNI_GCM_SSE:
- dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_SSE;
- break;
- case RTE_AESNI_GCM_AVX:
- dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX;
- break;
- case RTE_AESNI_GCM_AVX2:
- dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX2;
- break;
- default:
- break;
- }
-
- /* Set vector instructions mode supported */
internals = dev->data->dev_private;
- internals->vector_mode = vector_mode;
-
internals->max_nb_queue_pairs = init_params->max_nb_queue_pairs;
internals->max_nb_sessions = init_params->max_nb_sessions;
diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c
index e824d4b..e3ea58b 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_ops.c
@@ -48,8 +48,8 @@ static const struct rte_cryptodev_capabilities aesni_gcm_pmd_capabilities[] = {
.block_size = 16,
.key_size = {
.min = 16,
- .max = 16,
- .increment = 0
+ .max = 32,
+ .increment = 16
},
.digest_size = {
.min = 8,
@@ -57,9 +57,9 @@ static const struct rte_cryptodev_capabilities aesni_gcm_pmd_capabilities[] = {
.increment = 4
},
.aad_size = {
- .min = 8,
- .max = 12,
- .increment = 4
+ .min = 0,
+ .max = 65535,
+ .increment = 1
}
}, }
}, }
@@ -73,8 +73,8 @@ static const struct rte_cryptodev_capabilities aesni_gcm_pmd_capabilities[] = {
.block_size = 16,
.key_size = {
.min = 16,
- .max = 16,
- .increment = 0
+ .max = 32,
+ .increment = 16
},
.iv_size = {
.min = 16,
@@ -221,7 +221,6 @@ aesni_gcm_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
int socket_id)
{
struct aesni_gcm_qp *qp = NULL;
- struct aesni_gcm_private *internals = dev->data->dev_private;
/* Free memory prior to re-allocation if needed. */
if (dev->data->queue_pairs[qp_id] != NULL)
@@ -239,8 +238,6 @@ aesni_gcm_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
if (aesni_gcm_pmd_qp_set_unique_name(dev, qp))
goto qp_setup_cleanup;
- qp->ops = &gcm_ops[internals->vector_mode];
-
qp->processed_pkts = aesni_gcm_pmd_qp_create_processed_pkts_ring(qp,
qp_conf->nb_descriptors, socket_id);
if (qp->processed_pkts == NULL)
@@ -291,18 +288,15 @@ aesni_gcm_pmd_session_get_size(struct rte_cryptodev *dev __rte_unused)
/** Configure a aesni gcm session from a crypto xform chain */
static void *
-aesni_gcm_pmd_session_configure(struct rte_cryptodev *dev,
+aesni_gcm_pmd_session_configure(struct rte_cryptodev *dev __rte_unused,
struct rte_crypto_sym_xform *xform, void *sess)
{
- struct aesni_gcm_private *internals = dev->data->dev_private;
-
if (unlikely(sess == NULL)) {
GCM_LOG_ERR("invalid session struct");
return NULL;
}
- if (aesni_gcm_set_session_parameters(&gcm_ops[internals->vector_mode],
- sess, xform) != 0) {
+ if (aesni_gcm_set_session_parameters(sess, xform) != 0) {
GCM_LOG_ERR("failed configure session parameters");
return NULL;
}
diff --git a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h
index 9878d6e..0496b44 100644
--- a/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h
+++ b/drivers/crypto/aesni_gcm/aesni_gcm_pmd_private.h
@@ -58,8 +58,6 @@
/** private data structure for each virtual AESNI GCM device */
struct aesni_gcm_private {
- enum aesni_gcm_vector_mode vector_mode;
- /**< Vector mode */
unsigned max_nb_queue_pairs;
/**< Max number of queue pairs supported by device */
unsigned max_nb_sessions;
@@ -71,8 +69,6 @@ struct aesni_gcm_qp {
/**< Queue Pair Identifier */
char name[RTE_CRYPTODEV_NAME_LEN];
/**< Unique Queue Pair Name */
- const struct aesni_gcm_ops *ops;
- /**< Architecture dependent function pointer table of the gcm APIs */
struct rte_ring *processed_pkts;
/**< Ring for placing process packets */
struct rte_mempool *sess_mp;
@@ -87,10 +83,17 @@ enum aesni_gcm_operation {
AESNI_GCM_OP_AUTHENTICATED_DECRYPTION
};
+enum aesni_gcm_key {
+ AESNI_GCM_KEY_128,
+ AESNI_GCM_KEY_256
+};
+
/** AESNI GCM private session structure */
struct aesni_gcm_session {
enum aesni_gcm_operation op;
/**< GCM operation type */
+ enum aesni_gcm_key key;
+ /**< GCM key type */
struct gcm_data gdata __rte_cache_aligned;
/**< GCM parameters */
};
@@ -98,7 +101,6 @@ struct aesni_gcm_session {
/**
* Setup GCM session parameters
- * @param ops gcm ops function pointer table
* @param sess aesni gcm session structure
* @param xform crypto transform chain
*
@@ -107,8 +109,7 @@ struct aesni_gcm_session {
* - On failure returns error code < 0
*/
extern int
-aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *ops,
- struct aesni_gcm_session *sess,
+aesni_gcm_set_session_parameters(struct aesni_gcm_session *sess,
const struct rte_crypto_sym_xform *xform);
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index f75f0e2..ed3eab5 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -134,8 +134,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += -lrte_pmd_vmxnet3_uio
ifeq ($(CONFIG_RTE_LIBRTE_CRYPTODEV),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += -lrte_pmd_aesni_mb
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += -L$(AESNI_MULTI_BUFFER_LIB_PATH) -lIPSec_MB
-_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += -lrte_pmd_aesni_gcm -lcrypto
-_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += -L$(AESNI_MULTI_BUFFER_LIB_PATH) -lIPSec_MB
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += -lrte_pmd_aesni_gcm -lisal_crypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += -lrte_pmd_openssl -lcrypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO) += -lrte_pmd_null_crypto
_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat -lcrypto
--
2.7.0
^ permalink raw reply related
* Re: [PATCH 00/31] Support VFD and DPDK PF + kernel VF on i40e
From: Andrew Rybchenko @ 2016-12-02 12:09 UTC (permalink / raw)
To: Iremonger, Bernard, Lu, Wenzhuo, dev@dpdk.org
In-Reply-To: <8CEF83825BEC744B83065625E567D7C21A0B3B41@IRSMSX108.ger.corp.intel.com>
Hi Bernard,
On 12/02/2016 01:58 PM, Iremonger, Bernard wrote:
>> -----Original Message-----
>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Andrew Rybchenko
>> Sent: Friday, December 2, 2016 9:00 AM
>> To: Lu, Wenzhuo <wenzhuo.lu@intel.com>; dev@dpdk.org
>> Subject: Re: [dpdk-dev] [PATCH 00/31] Support VFD and DPDK PF + kernel VF
>> on i40e
>>
>> On 12/02/2016 03:11 AM, Wenzhuo Lu wrote:
>>> 1, VF Daemon (VFD)
>>> VFD is an idea to control all the VFs from PF.
>>> As we need to support the scenario kernel PF + DPDK VF, DPDK follows
>>> the interface between kernel PF + kernel VF. We don't want to
>>> introduce too many new messages between PF and VF. So this patch set
>>> adds some new APIs to control VFs directly from PF.
>>> The new APIs include,
>>> 1) set VF MAC anti-spoofing
>>> 2) set VF VLAN anti-spoofing
>>> 3) set TX loopback
>>> 4) set VF unicast promiscuous mode
>>> 5) set VF multicast promiscuous mode
>>> 6) set VF MTU
>>> 7) get/reset VF stats
>>> 8) set VF MAC address
>>> 9) set VF VLAN stripping
>>> 10) VF VLAN insertion
>>> 12) set VF broadcast mode
>>> 12) set VF VLAN tag
>>> 13) set VF VLAN filter
>>> VFD also includes VF to PF mailbox message management by APP. When PF
>>> receives mailbox messages from VF, PF should call the callback
>>> provided by APP to know if they're permitted to be processed.
>> The patch series adds i40e-specific API functions for VF control (advertise link
>> status change, MAC anti-spoofing, VLAN anti-spoofing, promiscuous mode,
>> MAC change, VLAN controls), but RTE API is added to get VF stats. I'm
>> wondering why.
>> Corresponding patches do not explain why i40e-specific API is added instead
>> of generic RTE API. IMHO, it is hardly convenient for applications.
>> (I guess it was a discussion and decision, but I've failed to find in the archive).
>>
>> Andrew.
> There was a discussion previously in DPDK 16.11 about this approach being used for the ixgbe PMD.
> I have attached the email thread.
Many thanks. I see that it is a staging area waiting for a later
generalization.
Andrew.
^ permalink raw reply
* Re: [PATCH] app/testpmd: supported offload capabilities query
From: Mcnamara, John @ 2016-12-02 11:42 UTC (permalink / raw)
To: Yang, Qiming, dev@dpdk.org; +Cc: Yang, Qiming
In-Reply-To: <B27915DBBA3421428155699D51E4CFE20266D3EF@IRSMSX103.ger.corp.intel.com>
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Mcnamara, John
> Sent: Friday, December 2, 2016 11:41 AM
> To: Yang, Qiming <qiming.yang@intel.com>; dev@dpdk.org
> Cc: Yang, Qiming <qiming.yang@intel.com>
> Subject: Re: [dpdk-dev] [PATCH] app/testpmd: supported offload
> capabilities query
>
>
>
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Qiming Yang
> > Sent: Friday, December 2, 2016 11:31 AM
> > To: dev@dpdk.org
> > Cc: Yang, Qiming <qiming.yang@intel.com>
> > Subject: [dpdk-dev] [PATCH] app/testpmd: supported offload
> > capabilities query
> >
> > Add two new commands "show port capa <port>" and "show port capa
> > all"to diaplay what offload capabilities supported in ports. It will
> > not only display all the capabilities of the port, but also the
> > enabling condition for each capability in the running time.
>
> Hi,
>
> Thanks for that.
>
> New TestPMD functions should have a corresponding entry in the docs.
>
Also, see Ferruh's patch to the TestPMD help to make sure your patch uses a similar output style.
http://dpdk.org/dev/patchwork/patch/17361/
John
^ permalink raw reply
* Re: [PATCH] app/testpmd: supported offload capabilities query
From: Mcnamara, John @ 2016-12-02 11:40 UTC (permalink / raw)
To: Yang, Qiming, dev@dpdk.org; +Cc: Yang, Qiming
In-Reply-To: <1480678283-3415-1-git-send-email-qiming.yang@intel.com>
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Qiming Yang
> Sent: Friday, December 2, 2016 11:31 AM
> To: dev@dpdk.org
> Cc: Yang, Qiming <qiming.yang@intel.com>
> Subject: [dpdk-dev] [PATCH] app/testpmd: supported offload capabilities
> query
>
> Add two new commands "show port capa <port>" and "show port capa all"to
> diaplay what offload capabilities supported in ports. It will not only
> display all the capabilities of the port, but also the enabling condition
> for each capability in the running time.
Hi,
Thanks for that.
New TestPMD functions should have a corresponding entry in the docs.
John
^ permalink raw reply
* [PATCH] app/testpmd: supported offload capabilities query
From: Qiming Yang @ 2016-12-02 11:31 UTC (permalink / raw)
To: dev; +Cc: Qiming Yang
Add two new commands "show port capa <port>" and "show
port capa all"to diaplay what offload capabilities supported
in ports. It will not only display all the capabilities of
the port, but also the enabling condition for each capability
in the running time.
Signed-off-by: Qiming Yang <qiming.yang@intel.com>
---
app/test-pmd/cmdline.c | 15 +++--
app/test-pmd/config.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++++
app/test-pmd/testpmd.h | 1 +
3 files changed, 184 insertions(+), 4 deletions(-)
diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c
index 63b55dc..4a9bcd3 100644
--- a/app/test-pmd/cmdline.c
+++ b/app/test-pmd/cmdline.c
@@ -5766,6 +5766,9 @@ static void cmd_showportall_parsed(void *parsed_result,
else if (!strcmp(res->what, "dcb_tc"))
FOREACH_PORT(i, ports)
port_dcb_info_display(i);
+ else if (!strcmp(res->what, "capa"))
+ FOREACH_PORT(i, ports)
+ port_offload_capa_display(i);
}
cmdline_parse_token_string_t cmd_showportall_show =
@@ -5775,13 +5778,14 @@ cmdline_parse_token_string_t cmd_showportall_port =
TOKEN_STRING_INITIALIZER(struct cmd_showportall_result, port, "port");
cmdline_parse_token_string_t cmd_showportall_what =
TOKEN_STRING_INITIALIZER(struct cmd_showportall_result, what,
- "info#stats#xstats#fdir#stat_qmap#dcb_tc");
+ "info#stats#xstats#fdir#stat_qmap#dcb_tc#capa");
cmdline_parse_token_string_t cmd_showportall_all =
TOKEN_STRING_INITIALIZER(struct cmd_showportall_result, all, "all");
cmdline_parse_inst_t cmd_showportall = {
.f = cmd_showportall_parsed,
.data = NULL,
- .help_str = "show|clear port info|stats|xstats|fdir|stat_qmap|dcb_tc all",
+ .help_str = "show|clear port"
+ "info|stats|xstats|fdir|stat_qmap|dcb_tc|capa all",
.tokens = {
(void *)&cmd_showportall_show,
(void *)&cmd_showportall_port,
@@ -5821,6 +5825,8 @@ static void cmd_showport_parsed(void *parsed_result,
nic_stats_mapping_display(res->portnum);
else if (!strcmp(res->what, "dcb_tc"))
port_dcb_info_display(res->portnum);
+ else if (!strcmp(res->what, "capa"))
+ port_offload_capa_display(res->portnum);
}
cmdline_parse_token_string_t cmd_showport_show =
@@ -5830,14 +5836,15 @@ cmdline_parse_token_string_t cmd_showport_port =
TOKEN_STRING_INITIALIZER(struct cmd_showport_result, port, "port");
cmdline_parse_token_string_t cmd_showport_what =
TOKEN_STRING_INITIALIZER(struct cmd_showport_result, what,
- "info#stats#xstats#fdir#stat_qmap#dcb_tc");
+ "info#stats#xstats#fdir#stat_qmap#dcb_tc#capa");
cmdline_parse_token_num_t cmd_showport_portnum =
TOKEN_NUM_INITIALIZER(struct cmd_showport_result, portnum, UINT8);
cmdline_parse_inst_t cmd_showport = {
.f = cmd_showport_parsed,
.data = NULL,
- .help_str = "show|clear port info|stats|xstats|fdir|stat_qmap|dcb_tc X (X = port number)",
+ .help_str = "show|clear port"
+ "info|stats|xstats|fdir|stat_qmap|dcb_tc|capa X (X = port number)",
.tokens = {
(void *)&cmd_showport_show,
(void *)&cmd_showport_port,
diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c
index 36c47ab..9571426 100644
--- a/app/test-pmd/config.c
+++ b/app/test-pmd/config.c
@@ -536,6 +536,178 @@ port_infos_display(portid_t port_id)
dev_info.tx_desc_lim.nb_min);
printf("TXDs number alignment: %hu\n", dev_info.tx_desc_lim.nb_align);
}
+void
+port_offload_capa_display(portid_t port_id)
+{
+ struct rte_eth_dev *dev;
+ struct rte_eth_dev_info dev_info;
+ static const char *info_border = "************";
+
+ if (port_id_is_invalid(port_id, ENABLED_WARN))
+ return;
+
+ dev = &rte_eth_devices[port_id];
+ rte_eth_dev_info_get(port_id, &dev_info);
+
+ printf("\n%s Port %d supported offload features: %s\n",
+ info_border, port_id, info_border);
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_VLAN_STRIP) {
+ printf("VLAN stripped: ");
+ if (dev->data->dev_conf.rxmode.hw_vlan_strip)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_IPV4_CKSUM) {
+ printf("RX IPv4 checksum: ");
+ if (dev->data->dev_conf.rxmode.hw_ip_checksum)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_UDP_CKSUM) {
+ printf("RX UDP checksum: ");
+ if (dev->data->dev_conf.rxmode.hw_ip_checksum)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_CKSUM) {
+ printf("TCP checksum: ");
+ if (dev->data->dev_conf.rxmode.hw_ip_checksum)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO) {
+ printf("Large receive offload: ");
+ if (dev->data->dev_conf.rxmode.enable_lro)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_QINQ_STRIP) {
+ printf("Double VLANs stripped: ");
+ if (dev->data->dev_conf.rxmode.hw_vlan_extend)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)
+ printf("Outer IPv4 checksum: ");
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_VLAN_INSERT) {
+ printf("VLAN insert: ");
+ if (ports[port_id].tx_ol_flags & TESTPMD_TX_OFFLOAD_INSERT_VLAN)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_IPV4_CKSUM) {
+ printf("TX IPv4 checksum: ");
+ if (ports[port_id].tx_ol_flags & TESTPMD_TX_OFFLOAD_IP_CKSUM)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_UDP_CKSUM) {
+ printf("TX UDP checksum: ");
+ if (ports[port_id].tx_ol_flags & TESTPMD_TX_OFFLOAD_UDP_CKSUM)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_TCP_CKSUM) {
+ printf("TX TCP checksum: ");
+ if (ports[port_id].tx_ol_flags & TESTPMD_TX_OFFLOAD_TCP_CKSUM)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_SCTP_CKSUM) {
+ printf("TX SCTP checksum: ");
+ if (ports[port_id].tx_ol_flags & TESTPMD_TX_OFFLOAD_SCTP_CKSUM)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_TCP_TSO) {
+ printf("TX TCP segmentation: ");
+ if (ports[port_id].tso_segsz != 0)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_UDP_TSO) {
+ printf("UDP segmentation: ");
+ if (ports[port_id].tso_segsz != 0)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) {
+ printf("Outer IPv4 checksum: ");
+ if (ports[port_id].tx_ol_flags & TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_QINQ_INSERT) {
+ printf("Double VLANs insert: ");
+ if (ports[port_id].tx_ol_flags & TESTPMD_TX_OFFLOAD_INSERT_QINQ)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_VXLAN_TNL_TSO) {
+ printf("VXLAN TSO for tunnel packet: ");
+ if (ports[port_id].tunnel_tso_segsz)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_GRE_TNL_TSO) {
+ printf("Generic TSO for tunnel packet: ");
+ if (ports[port_id].tunnel_tso_segsz)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_IPIP_TNL_TSO) {
+ printf("IPIP TSO for tunnel packet: ");
+ if (ports[port_id].tunnel_tso_segsz)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+ if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_GENEVE_TNL_TSO) {
+ printf("GENEVE TSO for tunnel packet: ");
+ if (ports[port_id].tunnel_tso_segsz)
+ printf("on\n");
+ else
+ printf("off\n");
+ }
+
+}
int
port_id_is_invalid(portid_t port_id, enum print_warning warning)
diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h
index 9c1e703..c59bb03 100644
--- a/app/test-pmd/testpmd.h
+++ b/app/test-pmd/testpmd.h
@@ -484,6 +484,7 @@ void nic_xstats_display(portid_t port_id);
void nic_xstats_clear(portid_t port_id);
void nic_stats_mapping_display(portid_t port_id);
void port_infos_display(portid_t port_id);
+void port_offload_capa_display(portid_t port_id);
void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
void fwd_lcores_config_display(void);
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 00/31] Support VFD and DPDK PF + kernel VF on i40e
From: Iremonger, Bernard @ 2016-12-02 11:28 UTC (permalink / raw)
To: Iremonger, Bernard, Andrew Rybchenko, Lu, Wenzhuo, dev@dpdk.org
In-Reply-To: <8CEF83825BEC744B83065625E567D7C21A0B3B41@IRSMSX108.ger.corp.intel.com>
Hi Andrew,
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Iremonger, Bernard
> Sent: Friday, December 2, 2016 10:59 AM
> To: Andrew Rybchenko <arybchenko@solarflare.com>; Lu, Wenzhuo
> <wenzhuo.lu@intel.com>; dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 00/31] Support VFD and DPDK PF + kernel VF
> on i40e
>
> Hi Andrew,
>
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Andrew
> Rybchenko
> > Sent: Friday, December 2, 2016 9:00 AM
> > To: Lu, Wenzhuo <wenzhuo.lu@intel.com>; dev@dpdk.org
> > Subject: Re: [dpdk-dev] [PATCH 00/31] Support VFD and DPDK PF + kernel
> > VF on i40e
> >
> > On 12/02/2016 03:11 AM, Wenzhuo Lu wrote:
> > > 1, VF Daemon (VFD)
> > > VFD is an idea to control all the VFs from PF.
> > > As we need to support the scenario kernel PF + DPDK VF, DPDK follows
> > > the interface between kernel PF + kernel VF. We don't want to
> > > introduce too many new messages between PF and VF. So this patch set
> > > adds some new APIs to control VFs directly from PF.
> > > The new APIs include,
> > > 1) set VF MAC anti-spoofing
> > > 2) set VF VLAN anti-spoofing
> > > 3) set TX loopback
> > > 4) set VF unicast promiscuous mode
> > > 5) set VF multicast promiscuous mode
> > > 6) set VF MTU
> > > 7) get/reset VF stats
> > > 8) set VF MAC address
> > > 9) set VF VLAN stripping
> > > 10) VF VLAN insertion
> > > 12) set VF broadcast mode
> > > 12) set VF VLAN tag
> > > 13) set VF VLAN filter
> > > VFD also includes VF to PF mailbox message management by APP. When
> > > PF receives mailbox messages from VF, PF should call the callback
> > > provided by APP to know if they're permitted to be processed.
> >
> > The patch series adds i40e-specific API functions for VF control
> > (advertise link status change, MAC anti-spoofing, VLAN anti-spoofing,
> > promiscuous mode, MAC change, VLAN controls), but RTE API is added to
> > get VF stats. I'm wondering why.
> > Corresponding patches do not explain why i40e-specific API is added
> > instead of generic RTE API. IMHO, it is hardly convenient for applications.
> > (I guess it was a discussion and decision, but I've failed to find in the
> archive).
> >
> > Andrew.
>
> There was a discussion previously in DPDK 16.11 about this approach being
> used for the ixgbe PMD.
> I have attached the email thread.
>
> Regards,
>
> Bernard.
The attached email did not get through for some reason. Here is a link to the email archive.
http://dpdk.org/ml/archives/dev/2016-September/047786.html
Regards,
Bernard.
^ permalink raw reply
* Re: [PATCH 30/31] net/i40e: support Linux VF to configure IRQ link list
From: Ferruh Yigit @ 2016-12-02 11:25 UTC (permalink / raw)
To: Wenzhuo Lu, dev; +Cc: Chen Jing D(Mark)
In-Reply-To: <1480637533-37425-31-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:12 AM, Wenzhuo Lu wrote:
> i40e PF host only support to work with DPDK VF driver, Linux
> VF driver is not supported. This change will enhance in
> configuring IRQ link list.
>
> This Change will identify VF client by number of vector
> requested. DPDK VF will ask only single one while Linux VF
> will request at least 2. It will have different configuration
> for different clients. DPDK VF will be configured to link all
> queue together, while Linux VF will be configured per request.
>
> Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
> ---
> drivers/net/i40e/i40e_pf.c | 151 +++++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 138 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_pf.c b/drivers/net/i40e/i40e_pf.c
> index 1ad5ed1..4b0da75 100644
> --- a/drivers/net/i40e/i40e_pf.c
> +++ b/drivers/net/i40e/i40e_pf.c
> @@ -585,14 +585,116 @@
> return ret;
> }
>
> +static void
> +i40e_pf_config_irq_link_list(struct i40e_pf_vf *vf,
> + struct i40e_virtchnl_vector_map *vvm)
> +{
> + uint64_t linklistmap = 0, tempmap;
> + struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
> + uint16_t qid;
> + bool b_first_q = true;
> + enum i40e_queue_type qtype;
> + uint16_t vector_id;
> + uint32_t reg, reg_idx;
> + uint16_t itr_idx = 0, i;
> +
> + vector_id = vvm->vector_id;
> + /* setup the head */
> + if (!vector_id)
> + reg_idx = I40E_VPINT_LNKLST0(vf->vf_idx);
> + else
> + reg_idx = I40E_VPINT_LNKLSTN(
> + ((hw->func_caps.num_msix_vectors_vf - 1) * vf->vf_idx)
> + + (vector_id - 1));
> +
> + if (vvm->rxq_map == 0 && vvm->txq_map == 0) {
> + I40E_WRITE_REG(hw, reg_idx,
> + I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);
> + goto cfg_irq_done;
> + }
> +
> + /* sort all rx and tx queues */
> + tempmap = vvm->rxq_map;
> + for (i = 0; i < sizeof(vvm->rxq_map) * 8; i++) {
> + if (tempmap & 0x1)
> + linklistmap |= (1 << (2 * i));
> + tempmap >>= 1;
> + }
> +
> + tempmap = vvm->txq_map;
> + for (i = 0; i < sizeof(vvm->txq_map) * 8; i++) {
> + if (tempmap & 0x1)
> + linklistmap |= (1 << (2 * i + 1));
> + tempmap >>= 1;
> + }
> +
> + /* Link all rx and tx queues into a chained list */
> + tempmap = linklistmap;
> + i = 0;
> + b_first_q = true;
> + do {
> + if (tempmap & 0x1) {
> + qtype = i % 2;
This cause ICC compilation error:
.../app/test-pmd/cmdline.c:(.text+0x79d4): undefined reference to
`rte_pmd_i40e_set_vf_vlan_stripq'
^ permalink raw reply
* Re: [PATCH 15/31] net/i40e: add VF vlan strip func
From: Ferruh Yigit @ 2016-12-02 11:25 UTC (permalink / raw)
To: Wenzhuo Lu, dev; +Cc: Chen Jing D(Mark)
In-Reply-To: <1480637533-37425-16-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:11 AM, Wenzhuo Lu wrote:
> Add a function to configure vlan strip enable/disable for specific
> SRIOV VF device.
For shared library compilation, this function also needs to be added to
rte_pmd_i40e_version.map file, otherwise throwing build error:
.../app/test-pmd/cmdline.c:(.text+0x79d4): undefined reference to
`rte_pmd_i40e_set_vf_vlan_stripq'
>
> Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
> ---
<...>
^ permalink raw reply
* Re: [PATCH 14/31] net/i40e: fix VF MAC address assignment
From: Ferruh Yigit @ 2016-12-02 11:24 UTC (permalink / raw)
To: Wenzhuo Lu, dev
In-Reply-To: <1480637533-37425-15-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:11 AM, Wenzhuo Lu wrote:
Missing both Fixes and CC to stable.
> Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
> ---
<...>
^ permalink raw reply
* Re: [PATCH 06/31] net/i40e: set VF unicast promisc mode from PF
From: Ferruh Yigit @ 2016-12-02 11:24 UTC (permalink / raw)
To: Wenzhuo Lu, dev
In-Reply-To: <1480637533-37425-7-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:11 AM, Wenzhuo Lu wrote:
> Support enabling/disabling VF unicast promicscuous mode from
s/promicscuous/promiscuous
> PF.
> User can call the API on PF to enable/disable a specific
> VF's unicast promiscuous mode.
>
> Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
<...>
^ permalink raw reply
* Re: [PATCH 07/31] net/i40e: set VF multicast promisc mode from PF
From: Ferruh Yigit @ 2016-12-02 11:24 UTC (permalink / raw)
To: Wenzhuo Lu, dev
In-Reply-To: <1480637533-37425-8-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:11 AM, Wenzhuo Lu wrote:
> Support enabling/disabling VF multicast promicscuous mode from
s/promicscuous/promiscuous
> PF.
> User can call the API on PF to enable/disable a specific
> VF's multicast promiscuous mode.
>
> Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
> ---
<...>
^ permalink raw reply
* Re: [PATCH 11/31] net/i40e: fix VF reset flow
From: Ferruh Yigit @ 2016-12-02 11:24 UTC (permalink / raw)
To: Wenzhuo Lu, dev; +Cc: Qi Zhang
In-Reply-To: <1480637533-37425-12-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:11 AM, Wenzhuo Lu wrote:
> Add missing step during VF reset: PF should
> set I40E_VFGEN_RSTAT to ACTIVE at end of the
> VF reset operation or VF driver may not able
> to detect that reset is already completed.
> This patch also remove the uneccessary enum
s/uneccessary/unnecessary
> for vfr state.
>
> Fixes: 4861cde46116 ("i40e: new poll mode driver")
>
missing cc, yes this is very new J
CC: stable@dpdk.org
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
<...>
^ permalink raw reply
* Re: [PATCH 12/31] net/i40e: set VF MAC from PF support
From: Ferruh Yigit @ 2016-12-02 11:23 UTC (permalink / raw)
To: Wenzhuo Lu, dev
In-Reply-To: <1480637533-37425-13-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:11 AM, Wenzhuo Lu wrote:
> Support setting VF MAC address from PF.
> User can call the API on PF to set a speific VF's
s/speific/specific
> MAC address.
>
> Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
<..>
^ permalink raw reply
* Re: [PATCH 31/31] i40e: enhance in sanity check of mac
From: Ferruh Yigit @ 2016-12-02 11:23 UTC (permalink / raw)
To: Wenzhuo Lu, dev; +Cc: Chen Jing D(Mark)
In-Reply-To: <1480637533-37425-32-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:12 AM, Wenzhuo Lu wrote:
> When VF sends request to add a new mac address, PF host
> will check if it's a non-zero or uncast address, or it
> will return with error. In fact, VF still can set multicast
> address. This change remove to check if it's a unicast
> address.
>
> Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
> ---
commit subject tag should be: "net/i40e:", and MAC is uppercase.
> drivers/net/i40e/i40e_pf.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/i40e/i40e_pf.c b/drivers/net/i40e/i40e_pf.c
> index 4b0da75..c9cca1e 100644
> --- a/drivers/net/i40e/i40e_pf.c
> +++ b/drivers/net/i40e/i40e_pf.c
> @@ -890,7 +890,7 @@
> mac = (struct ether_addr *)(addr_list->list[i].addr);
> (void)rte_memcpy(&filter.mac_addr, mac, ETHER_ADDR_LEN);
> filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
> - if(!is_valid_assigned_ether_addr(mac) ||
> + if(is_zero_ether_addr(mac) ||
checkpatch warning:
ERROR:SPACING: space required before the open parenthesis '('
> i40e_vsi_add_mac(vf->vsi, &filter)) {
> ret = I40E_ERR_INVALID_MAC_ADDR;
> goto send_msg;
>
^ permalink raw reply
* Re: [PATCH 05/31] net/i40e: set TX loopback from PF
From: Ferruh Yigit @ 2016-12-02 11:22 UTC (permalink / raw)
To: Wenzhuo Lu, dev
In-Reply-To: <1480637533-37425-6-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:11 AM, Wenzhuo Lu wrote:
> Support enabling/disabling TX loopback from PF.
> User can call the API on PF to enable/disable TX loopback
> for all the PF and VFs.
>
> Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
> ---
> drivers/net/i40e/i40e_ethdev.c | 219 ++++++++++++++++++++++++++++++
> drivers/net/i40e/rte_pmd_i40e.h | 16 +++
> drivers/net/i40e/rte_pmd_i40e_version.map | 1 +
> 3 files changed, 236 insertions(+)
>
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
> index ec863b9..9fe9672 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -9938,3 +9938,222 @@ static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
<...>
> +static int
> +i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
> +{
> + struct i40e_vsi_context ctxt;
> + struct i40e_hw *hw;
> + int ret;
> +
> + hw = I40E_VSI_TO_HW(vsi);
> +
> + /* Use the FW API if FW >= v5.0 */
> + if (hw->aq.fw_maj_ver < 5) {
> + PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
> + return -ENOSYS;
Checkpatch complains about ENOSYS usage:
WARNING:ENOSYS: ENOSYS means 'invalid syscall nr' and nothing else
What is intended error code here?
^ permalink raw reply
* Re: [PATCH 20/31] app/testpmd: use VFD APIs on i40e
From: Ferruh Yigit @ 2016-12-02 11:22 UTC (permalink / raw)
To: Wenzhuo Lu, dev; +Cc: Chen Jing D(Mark), Bernard Iremonger
In-Reply-To: <1480637533-37425-21-git-send-email-wenzhuo.lu@intel.com>
On 12/2/2016 12:12 AM, Wenzhuo Lu wrote:
> The new VF Daemon (VFD) APIs is implemented on i40e. Change
> testpmd code to use them, inlcuding VF MAC anti-spoofing,
s/inlcuding/including
> VF VLAN anti-spoofing, TX loopback, VF VLAN strip, VF VLAN
> insert.
>
> Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
> Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>
> Signed-off-by: Bernard Iremonger <bernard.iremonger@intel.com>
> ---
For shared library compilation, i40e library should be linked against,
this requires testpmd Makefile modification [1], otherwise throwing
compiler error [2].
[1]
diff --git a/app/test-pmd/Makefile b/app/test-pmd/Makefile
index 891b85a..87cbaf9 100644
--- a/app/test-pmd/Makefile
+++ b/app/test-pmd/Makefile
@@ -59,6 +59,7 @@ SRCS-y += icmpecho.c
SRCS-$(CONFIG_RTE_LIBRTE_IEEE1588) += ieee1588fwd.c
_LDLIBS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += -lrte_pmd_ixgbe
+_LDLIBS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += -lrte_pmd_i40e
[2]
cmdline.o: In function `cmd_set_vf_vlan_anti_spoof_parsed':
.../app/test-pmd/cmdline.c:(.text+0x76dc): undefined reference to
`rte_pmd_i40e_set_vf_vlan_anti_spoof'
cmdline.o: In function `cmd_set_vf_mac_anti_spoof_parsed':
.../app/test-pmd/cmdline.c:(.text+0x7854): undefined reference to
`rte_pmd_i40e_set_vf_mac_anti_spoof'
cmdline.o: In function `cmd_set_vf_vlan_stripq_parsed':
.../app/test-pmd/cmdline.c:(.text+0x79d4): undefined reference to
`rte_pmd_i40e_set_vf_vlan_stripq'
cmdline.o: In function `cmd_set_vf_vlan_insert_parsed':
.../app/test-pmd/cmdline.c:(.text+0x7b1e): undefined reference to
`rte_pmd_i40e_set_vf_vlan_insert'
cmdline.o: In function `cmd_set_tx_loopback_parsed':
.../app/test-pmd/cmdline.c:(.text+0x7c94): undefined reference to
`rte_pmd_i40e_set_tx_loopback'
cmdline.o: In function `cmd_set_vf_unicast_promisc_parsed':
.../app/test-pmd/cmdline.c:(.text+0x7f44): undefined reference to
`rte_pmd_i40e_set_vf_unicast_promisc'
cmdline.o: In function `cmd_set_vf_multicast_promisc_parsed':
.../app/test-pmd/cmdline.c:(.text+0x7fe4): undefined reference to
`rte_pmd_i40e_set_vf_multicast_promisc'
cmdline.o: In function `cmd_set_vf_broadcast_parsed':
.../app/test-pmd/cmdline.c:(.text+0x8086): undefined reference to
`rte_pmd_i40e_set_vf_broadcast'
cmdline.o: In function `cmd_set_vf_vlan_tag_parsed':
.../app/test-pmd/cmdline.c:(.text+0x8146): undefined reference to
`rte_pmd_i40e_set_vf_vlan_tag'
config.o: In function `set_vf_rx_vlan':
.../app/test-pmd/config.c:(.text+0x518d): undefined reference to
`rte_pmd_i40e_set_vf_vlan_filter'
clang-3.8: error: linker command failed with exit code 1 (use -v to see
invocation)
> app/test-pmd/cmdline.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 85 insertions(+), 7 deletions(-)
>
> diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c
> index 63b55dc..1284d6c 100644
> --- a/app/test-pmd/cmdline.c
> +++ b/app/test-pmd/cmdline.c
> @@ -90,6 +90,9 @@
> #ifdef RTE_LIBRTE_IXGBE_PMD
> #include <rte_pmd_ixgbe.h>
> #endif
> +#ifdef RTE_LIBRTE_I40E_PMD
> +#include <rte_pmd_i40e.h>
> +#endif
> #include "testpmd.h"
>
> static struct cmdline *testpmd_cl;
> @@ -10806,9 +10809,22 @@ struct cmd_vf_vlan_anti_spoof_result {
> struct cmd_vf_vlan_anti_spoof_result *res = parsed_result;
> int ret = 0;
> int is_on = (strcmp(res->on_off, "on") == 0) ? 1 : 0;
> + struct rte_eth_dev_info dev_info;
> +
> + memset(&dev_info, 0, sizeof(dev_info));
> + rte_eth_dev_info_get(res->port_id, &dev_info);
> +
> + if (strstr(dev_info.driver_name, "ixgbe") != NULL)
> + ret = rte_pmd_ixgbe_set_vf_vlan_anti_spoof(res->port_id,
> + res->vf_id,
> + is_on);
> + else if (strstr(dev_info.driver_name, "i40e") != NULL)
> + ret = rte_pmd_i40e_set_vf_vlan_anti_spoof(res->port_id,
> + res->vf_id,
> + is_on);
> + else
> + ret = -ENOSYS;
Same checkpatch warning, for all ENOSYS usage,
WARNING:ENOSYS: ENOSYS means 'invalid syscall nr' and nothing else
If the intention is not matching error type, we may change it.
^ permalink raw reply related
* Re: [PATCH 1/3] doc: update AESNI MB PMD guide
From: Mcnamara, John @ 2016-12-02 10:59 UTC (permalink / raw)
To: De Lara Guarch, Pablo, Doherty, Declan
Cc: dev@dpdk.org, De Lara Guarch, Pablo
In-Reply-To: <1480585017-63239-2-git-send-email-pablo.de.lara.guarch@intel.com>
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Pablo de Lara
> Sent: Thursday, December 1, 2016 9:37 AM
> To: Doherty, Declan <declan.doherty@intel.com>
> Cc: dev@dpdk.org; De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>
> Subject: [dpdk-dev] [PATCH 1/3] doc: update AESNI MB PMD guide
>
> The Intel(R) Multi Buffer Crypto library used in the AESNI MB PMD has been
> moved to a new repository, in github.
> This patch updates the link where it can be downloaded.
>
> Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
^ permalink raw reply
* Re: [PATCH 00/31] Support VFD and DPDK PF + kernel VF on i40e
From: Iremonger, Bernard @ 2016-12-02 10:58 UTC (permalink / raw)
To: Andrew Rybchenko, Lu, Wenzhuo, dev@dpdk.org
In-Reply-To: <27bd35a3-397c-6a4b-bc78-78eb3370d178@solarflare.com>
Hi Andrew,
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Andrew Rybchenko
> Sent: Friday, December 2, 2016 9:00 AM
> To: Lu, Wenzhuo <wenzhuo.lu@intel.com>; dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 00/31] Support VFD and DPDK PF + kernel VF
> on i40e
>
> On 12/02/2016 03:11 AM, Wenzhuo Lu wrote:
> > 1, VF Daemon (VFD)
> > VFD is an idea to control all the VFs from PF.
> > As we need to support the scenario kernel PF + DPDK VF, DPDK follows
> > the interface between kernel PF + kernel VF. We don't want to
> > introduce too many new messages between PF and VF. So this patch set
> > adds some new APIs to control VFs directly from PF.
> > The new APIs include,
> > 1) set VF MAC anti-spoofing
> > 2) set VF VLAN anti-spoofing
> > 3) set TX loopback
> > 4) set VF unicast promiscuous mode
> > 5) set VF multicast promiscuous mode
> > 6) set VF MTU
> > 7) get/reset VF stats
> > 8) set VF MAC address
> > 9) set VF VLAN stripping
> > 10) VF VLAN insertion
> > 12) set VF broadcast mode
> > 12) set VF VLAN tag
> > 13) set VF VLAN filter
> > VFD also includes VF to PF mailbox message management by APP. When PF
> > receives mailbox messages from VF, PF should call the callback
> > provided by APP to know if they're permitted to be processed.
>
> The patch series adds i40e-specific API functions for VF control (advertise link
> status change, MAC anti-spoofing, VLAN anti-spoofing, promiscuous mode,
> MAC change, VLAN controls), but RTE API is added to get VF stats. I'm
> wondering why.
> Corresponding patches do not explain why i40e-specific API is added instead
> of generic RTE API. IMHO, it is hardly convenient for applications.
> (I guess it was a discussion and decision, but I've failed to find in the archive).
>
> Andrew.
There was a discussion previously in DPDK 16.11 about this approach being used for the ixgbe PMD.
I have attached the email thread.
Regards,
Bernard.
^ permalink raw reply
* Re: [PATCH 3/3] doc: add missing supported algos for AESNI MB PMD
From: Mcnamara, John @ 2016-12-02 10:56 UTC (permalink / raw)
To: De Lara Guarch, Pablo, Doherty, Declan
Cc: dev@dpdk.org, De Lara Guarch, Pablo
In-Reply-To: <1480585017-63239-4-git-send-email-pablo.de.lara.guarch@intel.com>
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Pablo de Lara
> Sent: Thursday, December 1, 2016 9:37 AM
> To: Doherty, Declan <declan.doherty@intel.com>
> Cc: dev@dpdk.org; De Lara Guarch, Pablo <pablo.de.lara.guarch@intel.com>
> Subject: [dpdk-dev] [PATCH 3/3] doc: add missing supported algos for AESNI
> MB PMD
>
> AESNI MB PMD supports SHA224-HMAC and SHA384-HMAC, but the documentation
> was not updated with this.
>
> Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
^ permalink raw reply
* Re: [PATCH] nfp: add doc about supported features
From: Mcnamara, John @ 2016-12-02 10:56 UTC (permalink / raw)
To: Alejandro Lucero, dev@dpdk.org
In-Reply-To: <1480666653-35544-1-git-send-email-alejandro.lucero@netronome.com>
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Alejandro Lucero
> Sent: Friday, December 2, 2016 8:18 AM
> To: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH] nfp: add doc about supported features
>
> Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox