* [PATCH 1/6] net/gve: add thread safety to admin queue
From: Mark Blasko @ 2026-05-12 0:53 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko, Joshua Washington, Jasper Tran O'Leary
In-Reply-To: <20260512005404.946979-1-blasko@google.com>
Introduce a pthread_mutex to protect the admin queue operations.
Locking was added around gve_adminq_execute_cmd and the batch
queue creation/destruction functions.
Signed-off-by: Mark Blasko <blasko@google.com>
Reviewed-by: Joshua Washington <joshwash@google.com>
Reviewed-by: Jasper Tran O'Leary <jtranoleary@google.com>
---
.mailmap | 1 +
drivers/net/gve/base/gve_adminq.c | 68 +++++++++++++++++++++++++------
drivers/net/gve/gve_ethdev.h | 1 +
3 files changed, 57 insertions(+), 13 deletions(-)
diff --git a/.mailmap b/.mailmap
index 3ab7364668..7f7590866b 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1009,6 +1009,7 @@ Mario Carrillo <mario.alfredo.c.arevalo@intel.com>
Mário Kuka <kuka@cesnet.cz>
Mariusz Drost <mariuszx.drost@intel.com>
Mark Asselstine <mark.asselstine@windriver.com>
+Mark Blasko <blasko@google.com>
Mark Bloch <mbloch@nvidia.com> <markb@mellanox.com>
Mark Gillott <mgillott@vyatta.att-mail.com>
Mark Kavanagh <mark.b.kavanagh@intel.com>
diff --git a/drivers/net/gve/base/gve_adminq.c b/drivers/net/gve/base/gve_adminq.c
index 9c5316fb00..28661fb6cd 100644
--- a/drivers/net/gve/base/gve_adminq.c
+++ b/drivers/net/gve/base/gve_adminq.c
@@ -216,6 +216,7 @@ gve_process_device_options(struct gve_priv *priv,
int gve_adminq_alloc(struct gve_priv *priv)
{
+ pthread_mutexattr_t mutexattr;
uint8_t pci_rev_id;
priv->adminq = gve_alloc_dma_mem(&priv->adminq_dma_mem, PAGE_SIZE);
@@ -241,6 +242,12 @@ int gve_adminq_alloc(struct gve_priv *priv)
priv->adminq_get_ptype_map_cnt = 0;
priv->adminq_cfg_flow_rule_cnt = 0;
+ pthread_mutexattr_init(&mutexattr);
+ pthread_mutexattr_setpshared(&mutexattr, PTHREAD_PROCESS_SHARED);
+ pthread_mutexattr_setrobust(&mutexattr, PTHREAD_MUTEX_ROBUST);
+ pthread_mutex_init(&priv->adminq_lock, &mutexattr);
+ pthread_mutexattr_destroy(&mutexattr);
+
/* Setup Admin queue with the device */
rte_pci_read_config(priv->pci_dev, &pci_rev_id, sizeof(pci_rev_id),
RTE_PCI_REVISION_ID);
@@ -304,6 +311,7 @@ void gve_adminq_free(struct gve_priv *priv)
return;
gve_adminq_release(priv);
gve_free_dma_mem(&priv->adminq_dma_mem);
+ pthread_mutex_destroy(&priv->adminq_lock);
gve_clear_admin_queue_ok(priv);
}
@@ -418,7 +426,10 @@ static int gve_adminq_issue_cmd(struct gve_priv *priv,
(tail & priv->adminq_mask)) {
int err;
- /* Flush existing commands to make room. */
+ /* Flush existing commands to make room.
+ * Note: This kicks the doorbell for all staged commands.
+ * Any failure here means we failed after attempting to kick.
+ */
err = gve_adminq_kick_and_wait(priv);
if (err)
return err;
@@ -509,17 +520,24 @@ static int gve_adminq_execute_cmd(struct gve_priv *priv,
u32 tail, head;
int err;
+ pthread_mutex_lock(&priv->adminq_lock);
tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
head = priv->adminq_prod_cnt;
- if (tail != head)
+ if (tail != head) {
/* This is not a valid path */
- return -EINVAL;
+ err = -EINVAL;
+ goto unlock_and_return;
+ }
err = gve_adminq_issue_cmd(priv, cmd_orig);
if (err)
- return err;
+ goto unlock_and_return;
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_adminq_execute_extended_cmd(struct gve_priv *priv, u32 opcode,
@@ -693,13 +711,19 @@ int gve_adminq_create_tx_queues(struct gve_priv *priv, u32 num_queues)
int err;
u32 i;
+ pthread_mutex_lock(&priv->adminq_lock);
+
for (i = 0; i < num_queues; i++) {
err = gve_adminq_create_tx_queue(priv, i);
if (err)
- return err;
+ goto unlock_and_return;
}
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index)
@@ -747,13 +771,19 @@ int gve_adminq_create_rx_queues(struct gve_priv *priv, u32 num_queues)
int err;
u32 i;
+ pthread_mutex_lock(&priv->adminq_lock);
+
for (i = 0; i < num_queues; i++) {
err = gve_adminq_create_rx_queue(priv, i);
if (err)
- return err;
+ goto unlock_and_return;
}
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_adminq_destroy_tx_queue(struct gve_priv *priv, u32 queue_index)
@@ -779,13 +809,19 @@ int gve_adminq_destroy_tx_queues(struct gve_priv *priv, u32 num_queues)
int err;
u32 i;
+ pthread_mutex_lock(&priv->adminq_lock);
+
for (i = 0; i < num_queues; i++) {
err = gve_adminq_destroy_tx_queue(priv, i);
if (err)
- return err;
+ goto unlock_and_return;
}
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_adminq_destroy_rx_queue(struct gve_priv *priv, u32 queue_index)
@@ -811,13 +847,19 @@ int gve_adminq_destroy_rx_queues(struct gve_priv *priv, u32 num_queues)
int err;
u32 i;
+ pthread_mutex_lock(&priv->adminq_lock);
+
for (i = 0; i < num_queues; i++) {
err = gve_adminq_destroy_rx_queue(priv, i);
if (err)
- return err;
+ goto unlock_and_return;
}
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_set_desc_cnt(struct gve_priv *priv,
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
index 0577f03974..524e48e723 100644
--- a/drivers/net/gve/gve_ethdev.h
+++ b/drivers/net/gve/gve_ethdev.h
@@ -339,6 +339,7 @@ struct gve_priv {
struct gve_tx_queue **txqs;
struct gve_rx_queue **rxqs;
+ pthread_mutex_t adminq_lock; /* Protects AdminQ command execution */
uint32_t stats_report_len;
const struct rte_memzone *stats_report_mem;
uint16_t stats_start_idx; /* start index of array of stats written by NIC */
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 0/6] net/gve: add hardware timestamping support
From: Mark Blasko @ 2026-05-12 0:53 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko
This patch series introduces support for GVE hardware timestamping on DQO
queues. To support concurrent access, a mutex lock is introduced to protect
admin queue operations. A mechanism is then added to periodically synchronize
the NIC clock via AdminQ, and support is introduced for the read_clock ethdev
operation. Finally, the RX datapath is updated to reconstruct full 64-bit
timestamps from the 32-bit values in DQO descriptors.
Mark Blasko (6):
net/gve: add thread safety to admin queue
net/gve: add device option support for HW timestamps
net/gve: add AdminQ command for NIC timestamps
net/gve: add periodic NIC clock synchronization
net/gve: support read clock ethdev op
net/gve: reconstruct HW timestamps from DQO
.mailmap | 1 +
doc/guides/nics/features/gve.ini | 1 +
doc/guides/nics/gve.rst | 18 +++
doc/guides/rel_notes/release_26_07.rst | 3 +
drivers/net/gve/base/gve_adminq.c | 127 +++++++++++++++++----
drivers/net/gve/base/gve_adminq.h | 29 +++++
drivers/net/gve/base/gve_desc_dqo.h | 8 +-
drivers/net/gve/gve_ethdev.c | 148 ++++++++++++++++++++++++-
drivers/net/gve/gve_ethdev.h | 39 +++++++
drivers/net/gve/gve_rx_dqo.c | 26 +++++
10 files changed, 378 insertions(+), 22 deletions(-)
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply
* [PATCH 6/6] net/gve: reconstruct HW timestamps from DQO
From: mark-blasko @ 2026-05-12 0:50 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko, Joshua Washington, Jasper Tran O'Leary
In-Reply-To: <20260512005057.944672-1-blasko@google.com>
From: Mark Blasko <blasko@google.com>
A full 64-bit NIC timestamp is periodically synced via an AdminQ
command and cached in the driver. In the RX datapath, this cached
value is used as a base to expand the 32-bit hardware timestamp into
a full 64-bit value, which is then stored in the mbuf's dynamic
timestamp field.
Signed-off-by: Mark Blasko <blasko@google.com>
Reviewed-by: Joshua Washington <joshwash@google.com>
Reviewed-by: Jasper Tran O'Leary <jtranoleary@google.com>
---
doc/guides/nics/features/gve.ini | 1 +
doc/guides/nics/gve.rst | 18 ++++++++++++++++++
doc/guides/rel_notes/release_26_07.rst | 3 +++
drivers/net/gve/base/gve_desc_dqo.h | 8 ++++++--
drivers/net/gve/gve_ethdev.c | 14 +++++++++++++-
drivers/net/gve/gve_ethdev.h | 25 +++++++++++++++++++++++++
drivers/net/gve/gve_rx_dqo.c | 26 ++++++++++++++++++++++++++
7 files changed, 92 insertions(+), 3 deletions(-)
diff --git a/doc/guides/nics/features/gve.ini b/doc/guides/nics/features/gve.ini
index 89c97fd27a..117ad4fc65 100644
--- a/doc/guides/nics/features/gve.ini
+++ b/doc/guides/nics/features/gve.ini
@@ -13,6 +13,7 @@ RSS hash = Y
RSS key update = Y
RSS reta update = Y
L4 checksum offload = Y
+Timestamp offload = Y
Basic stats = Y
FreeBSD = Y
Linux = Y
diff --git a/doc/guides/nics/gve.rst b/doc/guides/nics/gve.rst
index 62648c47ed..44aedc9311 100644
--- a/doc/guides/nics/gve.rst
+++ b/doc/guides/nics/gve.rst
@@ -72,6 +72,7 @@ Supported features of the GVE PMD are:
- Tx UDP/TCP/SCTP Checksum
- RSS hash configuration
- RSS redirection table query and update
+- Timestamp offload
Currently, only GQI_QPL and GQI_RDA queue format are supported in PMD.
Jumbo Frame is not supported in PMD for now.
@@ -132,6 +133,23 @@ Security Protocols
- Flow priorities are not supported (must be 0).
- Masking is limited to full matches i.e. ``0x00...0`` or ``0xFF...F``.
+Timestamp Offload
+^^^^^^^^^^^^^^^^^
+
+The driver supports hardware-based packet timestamping on supported
+devices via the standard ``RTE_ETH_RX_OFFLOAD_TIMESTAMP`` offload capability.
+
+**Limitations**
+
+- If the driver fails to fetch the NIC hardware clock for 7 consecutive periods,
+ the cached timestamp is marked as stale,
+ and the reconstructed timestamps are no longer propagated to the mbuf.
+- The timestamp reconstruction is only accurate
+ if the time between a packet's reception
+ and the last hardware clock sync is less than approximately 2 seconds.
+ The driver's internal clock sync period is set to respect this limitation.
+
+
Device Reset
^^^^^^^^^^^^
diff --git a/doc/guides/rel_notes/release_26_07.rst b/doc/guides/rel_notes/release_26_07.rst
index 1b012c4776..db886f19cf 100644
--- a/doc/guides/rel_notes/release_26_07.rst
+++ b/doc/guides/rel_notes/release_26_07.rst
@@ -62,6 +62,9 @@ New Features
* ``-A`` or ``--no-auto-probing`` disable the initial bus probing: no device is probed during
``rte_eal_init`` and the application is responsible for probing each device,
* ``--auto-probing`` enables the initial bus probing, which is the current default behavior.
+* **Updated Google GVE net driver.**
+
+ * Added hardware timestamping support on DQO queues.
* **Updated PCAP ethernet driver.**
diff --git a/drivers/net/gve/base/gve_desc_dqo.h b/drivers/net/gve/base/gve_desc_dqo.h
index 71d9d60bb9..c1534959c2 100644
--- a/drivers/net/gve/base/gve_desc_dqo.h
+++ b/drivers/net/gve/base/gve_desc_dqo.h
@@ -226,7 +226,8 @@ struct gve_rx_compl_desc_dqo {
u8 status_error1;
- __le16 reserved5;
+ u8 reserved5;
+ u8 ts_sub_nsecs_low;
__le16 buf_id; /* Buffer ID which was sent on the buffer queue. */
union {
@@ -237,9 +238,12 @@ struct gve_rx_compl_desc_dqo {
};
__le32 hash;
__le32 reserved6;
- __le64 reserved7;
+ __le32 reserved7;
+ __le32 ts; /* timestamp in nanosecs */
} __packed;
+#define GVE_DQO_RX_HWTSTAMP_VALID 0x1
+
GVE_CHECK_STRUCT_LEN(32, gve_rx_compl_desc_dqo);
/* Ringing the doorbell too often can hurt performance.
diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c
index e1f2585ede..fa26c2bdb4 100644
--- a/drivers/net/gve/gve_ethdev.c
+++ b/drivers/net/gve/gve_ethdev.c
@@ -214,6 +214,7 @@ static int
gve_dev_configure(struct rte_eth_dev *dev)
{
struct gve_priv *priv = dev->data->dev_private;
+ int err;
if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
@@ -223,13 +224,22 @@ gve_dev_configure(struct rte_eth_dev *dev)
if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)
priv->enable_rsc = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ err = rte_mbuf_dyn_rx_timestamp_register(&priv->mbuf_timestamp_offset,
+ &priv->mbuf_timestamp_mask);
+ if (err < 0) {
+ PMD_DRV_LOG(ERR, "Failed to register dynamic timestamp field");
+ return err;
+ }
+ }
+
/* Reset RSS RETA in case number of queues changed. */
if (priv->rss_config.indir) {
struct gve_rss_config update_reta_config;
gve_init_rss_config_from_priv(priv, &update_reta_config);
gve_generate_rss_reta(dev, &update_reta_config);
- int err = gve_adminq_configure_rss(priv, &update_reta_config);
+ err = gve_adminq_configure_rss(priv, &update_reta_config);
if (err)
PMD_DRV_LOG(ERR,
"Could not reconfigure RSS redirection table.");
@@ -817,6 +827,8 @@ gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->min_mtu = RTE_ETHER_MIN_MTU;
dev_info->rx_offload_capa = RTE_ETH_RX_OFFLOAD_RSS_HASH;
+ if (priv->nic_timestamp_supported)
+ dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
dev_info->tx_offload_capa =
RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
index 7e6f24e910..35d532284e 100644
--- a/drivers/net/gve/gve_ethdev.h
+++ b/drivers/net/gve/gve_ethdev.h
@@ -260,6 +260,7 @@ struct gve_rx_queue {
struct rte_mbuf **refill_bufs;
uint8_t is_gqi_qpl;
+ bool timestamp_enabled;
};
struct gve_flow {
@@ -368,8 +369,32 @@ struct gve_priv {
RTE_ATOMIC(uint64_t) last_read_nic_timestamp;
RTE_ATOMIC(uint32_t) nic_ts_read_fails;
RTE_ATOMIC(uint8_t) nic_ts_stale;
+
+ int mbuf_timestamp_offset;
+ uint64_t mbuf_timestamp_mask;
};
+/* Expand the hardware timestamp to the full 64 bits of width.
+ *
+ * This algorithm works by using the passed hardware timestamp to generate a
+ * diff relative to the last read of the nic clock. This diff can be positive or
+ * negative, as it is possible that we have read the clock more recently than
+ * the hardware has received this packet. To detect this, we use the high bit of
+ * the diff, and assume that the read is more recent if the high bit is set. In
+ * this case we invert the process.
+ *
+ * Note that this means if the time delta between packet reception and the last
+ * clock read is greater than ~2 seconds, this will provide invalid results.
+ */
+static inline uint64_t
+gve_reconstruct_ts(uint64_t last_sync, uint32_t ts)
+{
+ uint32_t low = (uint32_t)last_sync;
+ int32_t diff = (int32_t)(ts - low);
+
+ return last_sync + diff;
+}
+
static inline bool
gve_is_gqi(struct gve_priv *priv)
{
diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c
index 8035aee572..cc343f3fd8 100644
--- a/drivers/net/gve/gve_rx_dqo.c
+++ b/drivers/net/gve/gve_rx_dqo.c
@@ -160,6 +160,8 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
{
volatile struct gve_rx_compl_desc_dqo *rx_desc;
struct gve_rx_queue *rxq;
+ uint64_t last_sync = 0;
+ struct gve_priv *priv;
struct rte_mbuf *rxm;
uint16_t rx_buf_id;
uint16_t pkt_len;
@@ -171,6 +173,15 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
nb_rx = 0;
rxq = rx_queue;
rx_id = rxq->rx_tail;
+ priv = rxq->hw;
+
+ if (rxq->timestamp_enabled &&
+ !rte_atomic_load_explicit(&priv->nic_ts_stale,
+ rte_memory_order_acquire)) {
+ last_sync =
+ rte_atomic_load_explicit(&priv->last_read_nic_timestamp,
+ rte_memory_order_relaxed);
+ }
while (nb_rx < nb_pkts) {
rx_desc = &rxq->compl_ring[rx_id];
@@ -208,6 +219,16 @@ gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
gve_parse_csum_ol_flags(rxm, rx_desc);
rxm->hash.rss = rte_le_to_cpu_32(rx_desc->hash);
+ if (last_sync != 0 &&
+ (rx_desc->ts_sub_nsecs_low & GVE_DQO_RX_HWTSTAMP_VALID) &&
+ priv->mbuf_timestamp_offset >= 0) {
+ uint32_t ts = rte_le_to_cpu_32(rx_desc->ts);
+ uint64_t full_ts = gve_reconstruct_ts(last_sync, ts);
+
+ *RTE_MBUF_DYNFIELD(rxm, priv->mbuf_timestamp_offset, uint64_t *) = full_ts;
+ rxm->ol_flags |= priv->mbuf_timestamp_mask;
+ }
+
rx_pkts[nb_rx++] = rxm;
bytes += pkt_len;
}
@@ -320,6 +341,11 @@ gve_rx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,
return -ENOMEM;
}
+ /* Setup hardware timestamping if enabled */
+ if ((conf->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) ||
+ (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))
+ rxq->timestamp_enabled = true;
+
/* check free_thresh here */
free_thresh = conf->rx_free_thresh ?
conf->rx_free_thresh : GVE_DEFAULT_RX_FREE_THRESH;
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 5/6] net/gve: support read clock ethdev op
From: mark-blasko @ 2026-05-12 0:50 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko, Joshua Washington, Jasper Tran O'Leary
In-Reply-To: <20260512005057.944672-1-blasko@google.com>
From: Mark Blasko <blasko@google.com>
Implement the read_clock operation in eth_dev_ops. The function calls
the AdminQ command to fetch the current NIC timestamp synchronously,
updates the cached timestamp used for reconstruction, and returns the
full 64-bit value.
Signed-off-by: Mark Blasko <blasko@google.com>
Reviewed-by: Joshua Washington <joshwash@google.com>
Reviewed-by: Jasper Tran O'Leary <jtranoleary@google.com>
---
drivers/net/gve/gve_ethdev.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c
index b36bc7266e..e1f2585ede 100644
--- a/drivers/net/gve/gve_ethdev.c
+++ b/drivers/net/gve/gve_ethdev.c
@@ -1271,6 +1271,34 @@ gve_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops)
return 0;
}
+static int
+gve_read_clock(struct rte_eth_dev *dev, uint64_t *clock)
+{
+ struct gve_priv *priv = dev->data->dev_private;
+ uint64_t ts;
+ int err;
+
+ if (!priv->nic_timestamp_supported)
+ return -EOPNOTSUPP;
+
+ if (!priv->nic_ts_report_mz)
+ return -EIO;
+
+ err = gve_adminq_report_nic_timestamp(priv, priv->nic_ts_report_mz->iova);
+ if (err != 0)
+ return err;
+
+ ts = be64_to_cpu(priv->nic_ts_report->nic_timestamp);
+ *clock = ts;
+
+ /* Update the cached value */
+ rte_atomic_store_explicit(&priv->last_read_nic_timestamp, ts, rte_memory_order_relaxed);
+ rte_atomic_store_explicit(&priv->nic_ts_read_fails, 0, rte_memory_order_relaxed);
+ rte_atomic_store_explicit(&priv->nic_ts_stale, 0, rte_memory_order_release);
+
+ return 0;
+}
+
static const struct eth_dev_ops gve_eth_dev_ops = {
.dev_configure = gve_dev_configure,
.dev_start = gve_dev_start,
@@ -1297,6 +1325,7 @@ static const struct eth_dev_ops gve_eth_dev_ops = {
.rss_hash_conf_get = gve_rss_hash_conf_get,
.reta_update = gve_rss_reta_update,
.reta_query = gve_rss_reta_query,
+ .read_clock = gve_read_clock,
};
static const struct eth_dev_ops gve_eth_dev_ops_dqo = {
@@ -1325,6 +1354,7 @@ static const struct eth_dev_ops gve_eth_dev_ops_dqo = {
.rss_hash_conf_get = gve_rss_hash_conf_get,
.reta_update = gve_rss_reta_update,
.reta_query = gve_rss_reta_query,
+ .read_clock = gve_read_clock,
};
static int
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 4/6] net/gve: add periodic NIC clock synchronization
From: mark-blasko @ 2026-05-12 0:50 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko, Joshua Washington, Jasper Tran O'Leary
In-Reply-To: <20260512005057.944672-1-blasko@google.com>
From: Mark Blasko <blasko@google.com>
Introduce a mechanism to periodically fetch the NIC hardware timestamp
using the GVE_ADMINQ_REPORT_NIC_TIMESTAMP AdminQ command. The
synchronization runs every 250ms using rte_alarm. If the read fails,
the alarm is still rescheduled. After 7 consecutive failures, the
timestamp is marked as stale, indicating to the RX path that
reconstructed timestamps may be unreliable.
Atomics exist because of the potential for async callers (introduced
here) and async callers (introduced later in the RX datapath) accessing
the cached state.
Signed-off-by: Mark Blasko <blasko@google.com>
Reviewed-by: Joshua Washington <joshwash@google.com>
Reviewed-by: Jasper Tran O'Leary <jtranoleary@google.com>
---
drivers/net/gve/gve_ethdev.c | 104 +++++++++++++++++++++++++++++++++++
drivers/net/gve/gve_ethdev.h | 9 +++
2 files changed, 113 insertions(+)
diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c
index a9e2063dda..b36bc7266e 100644
--- a/drivers/net/gve/gve_ethdev.c
+++ b/drivers/net/gve/gve_ethdev.c
@@ -452,6 +452,86 @@ gve_dev_start(struct rte_eth_dev *dev)
return 0;
}
+static void
+gve_read_nic_clock(void *arg)
+{
+ struct gve_priv *priv = (struct gve_priv *)arg;
+ uint32_t fails;
+ uint64_t ts;
+ int err;
+
+ if (!priv || !priv->nic_ts_report_mz)
+ return;
+
+ memset(priv->nic_ts_report, 0, sizeof(struct gve_nic_ts_report));
+
+ err = gve_adminq_report_nic_timestamp(priv, priv->nic_ts_report_mz->iova);
+ if (err == 0) {
+ ts = be64_to_cpu(priv->nic_ts_report->nic_timestamp);
+ rte_atomic_store_explicit(&priv->last_read_nic_timestamp, ts,
+ rte_memory_order_relaxed);
+ PMD_DRV_LOG(DEBUG, "Fetched NIC Timestamp: %" PRIu64, ts);
+ rte_atomic_store_explicit(&priv->nic_ts_read_fails, 0,
+ rte_memory_order_relaxed);
+ rte_atomic_store_explicit(&priv->nic_ts_stale, 0,
+ rte_memory_order_release);
+ } else {
+ PMD_DRV_LOG(ERR, "Failed to read NIC clock, AQ err: %d", err);
+ fails = rte_atomic_fetch_add_explicit(&priv->nic_ts_read_fails, 1,
+ rte_memory_order_relaxed) + 1;
+ if (fails >= GVE_NIC_CLOCK_READ_MAX_FAILS) {
+ if (!rte_atomic_load_explicit(&priv->nic_ts_stale,
+ rte_memory_order_relaxed))
+ PMD_DRV_LOG(ERR,
+ "NIC timestamping marked as stale after %u consecutive failures",
+ GVE_NIC_CLOCK_READ_MAX_FAILS);
+ rte_atomic_store_explicit(&priv->nic_ts_stale, 1,
+ rte_memory_order_release);
+ }
+ }
+
+ /* Reschedule the alarm for the next interval */
+ if (priv->nic_ts_report_mz) {
+ err = rte_eal_alarm_set(GVE_NIC_CLOCK_READ_PERIOD_MS * 1000,
+ gve_read_nic_clock, priv);
+ if (err < 0)
+ PMD_DRV_LOG(ERR, "Failed to reschedule NIC clock read alarm, ret=%d", err);
+ }
+}
+
+static int
+gve_alloc_nic_ts_report(struct gve_priv *priv)
+{
+ char z_name[RTE_MEMZONE_NAMESIZE];
+
+ if (!priv->nic_timestamp_supported)
+ return -EOPNOTSUPP;
+
+ snprintf(z_name, sizeof(z_name), "gve_%s_nic_ts_report",
+ priv->pci_dev->device.name);
+ priv->nic_ts_report_mz = rte_memzone_reserve_aligned(z_name,
+ sizeof(struct gve_nic_ts_report), rte_socket_id(),
+ RTE_MEMZONE_IOVA_CONTIG, PAGE_SIZE);
+
+ if (!priv->nic_ts_report_mz) {
+ PMD_DRV_LOG(ERR, "Failed to allocate memzone for NIC TS report");
+ return -ENOMEM;
+ }
+ priv->nic_ts_report = (struct gve_nic_ts_report *)priv->nic_ts_report_mz->addr;
+ rte_atomic_store_explicit(&priv->nic_ts_read_fails, 0, rte_memory_order_relaxed);
+ return 0;
+}
+
+static void
+gve_free_nic_ts_report(struct gve_priv *priv)
+{
+ if (priv->nic_ts_report_mz) {
+ rte_memzone_free(priv->nic_ts_report_mz);
+ priv->nic_ts_report_mz = NULL;
+ priv->nic_ts_report = NULL;
+ }
+}
+
static int
gve_dev_stop(struct rte_eth_dev *dev)
{
@@ -576,6 +656,7 @@ static void
gve_teardown_device_resources(struct gve_priv *priv)
{
int err;
+ int ret;
/* Tell device its resources are being freed */
if (gve_get_device_resources_ok(priv)) {
@@ -586,6 +667,13 @@ gve_teardown_device_resources(struct gve_priv *priv)
err);
}
+ if (priv->nic_ts_report_mz) {
+ ret = rte_eal_alarm_cancel(gve_read_nic_clock, priv);
+ if (ret < 0)
+ PMD_DRV_LOG(ERR, "Failed to cancel NIC clock sync alarm, ret=%d", ret);
+ gve_free_nic_ts_report(priv);
+ }
+
gve_free_ptype_lut_dqo(priv);
gve_free_counter_array(priv);
gve_free_irq_db(priv);
@@ -1252,6 +1340,21 @@ pci_dev_msix_vec_count(struct rte_pci_device *pdev)
return 0;
}
+static void
+gve_setup_nic_timestamp(struct gve_priv *priv)
+{
+ int err;
+
+ if (!priv->nic_timestamp_supported)
+ return;
+
+ rte_atomic_store_explicit(&priv->nic_ts_read_fails, 0, rte_memory_order_relaxed);
+ rte_atomic_store_explicit(&priv->nic_ts_stale, 1, rte_memory_order_relaxed);
+ err = gve_alloc_nic_ts_report(priv);
+ if (err == 0)
+ gve_read_nic_clock(priv);
+}
+
static int
gve_setup_device_resources(struct gve_priv *priv)
{
@@ -1307,6 +1410,7 @@ gve_setup_device_resources(struct gve_priv *priv)
goto free_ptype_lut;
}
}
+ gve_setup_nic_timestamp(priv);
gve_set_device_resources_ok(priv);
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
index b67f82c263..7e6f24e910 100644
--- a/drivers/net/gve/gve_ethdev.h
+++ b/drivers/net/gve/gve_ethdev.h
@@ -12,6 +12,7 @@
#include <rte_pci.h>
#include <pthread.h>
#include <rte_bitmap.h>
+#include <rte_memzone.h>
#include "base/gve.h"
@@ -39,6 +40,9 @@
#define GVE_RSS_HASH_KEY_SIZE 40
#define GVE_RSS_INDIR_SIZE 128
+#define GVE_NIC_CLOCK_READ_PERIOD_MS 250
+#define GVE_NIC_CLOCK_READ_MAX_FAILS 7
+
#define GVE_TX_CKSUM_OFFLOAD_MASK ( \
RTE_MBUF_F_TX_L4_MASK | \
RTE_MBUF_F_TX_TCP_SEG)
@@ -359,6 +363,11 @@ struct gve_priv {
/* HW Timestamping Fields */
bool nic_timestamp_supported;
+ const struct rte_memzone *nic_ts_report_mz;
+ struct gve_nic_ts_report *nic_ts_report;
+ RTE_ATOMIC(uint64_t) last_read_nic_timestamp;
+ RTE_ATOMIC(uint32_t) nic_ts_read_fails;
+ RTE_ATOMIC(uint8_t) nic_ts_stale;
};
static inline bool
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 3/6] net/gve: add AdminQ command for NIC timestamps
From: mark-blasko @ 2026-05-12 0:50 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko, Joshua Washington, Jasper Tran O'Leary
In-Reply-To: <20260512005057.944672-1-blasko@google.com>
From: Mark Blasko <blasko@google.com>
Introduce the necessary definitions and functions for the
GVE_ADMINQ_REPORT_NIC_TIMESTAMP AdminQ command.
Signed-off-by: Mark Blasko <blasko@google.com>
Reviewed-by: Joshua Washington <joshwash@google.com>
Reviewed-by: Jasper Tran O'Leary <jtranoleary@google.com>
---
drivers/net/gve/base/gve_adminq.c | 18 ++++++++++++++++++
drivers/net/gve/base/gve_adminq.h | 20 ++++++++++++++++++++
drivers/net/gve/gve_ethdev.h | 1 +
3 files changed, 39 insertions(+)
diff --git a/drivers/net/gve/base/gve_adminq.c b/drivers/net/gve/base/gve_adminq.c
index c9095fd165..e700262d7f 100644
--- a/drivers/net/gve/base/gve_adminq.c
+++ b/drivers/net/gve/base/gve_adminq.c
@@ -523,6 +523,10 @@ static int gve_adminq_issue_cmd(struct gve_priv *priv,
case GVE_ADMINQ_CONFIGURE_FLOW_RULE:
priv->adminq_cfg_flow_rule_cnt++;
break;
+ case GVE_ADMINQ_REPORT_NIC_TIMESTAMP:
+ priv->adminq_report_nic_timestamp_cnt++;
+ break;
+
default:
PMD_DRV_LOG(ERR, "unknown AQ command opcode %d", opcode);
}
@@ -637,6 +641,20 @@ int gve_adminq_reset_flow_rules(struct gve_priv *priv)
return gve_adminq_configure_flow_rule(priv, &flow_rule_cmd);
}
+int gve_adminq_report_nic_timestamp(struct gve_priv *priv, dma_addr_t nic_ts_report_addr)
+{
+ union gve_adminq_command cmd;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.opcode = cpu_to_be32(GVE_ADMINQ_REPORT_NIC_TIMESTAMP);
+ cmd.report_nic_timestamp = (struct gve_adminq_report_nic_timestamp) {
+ .nic_ts_report_len = cpu_to_be64(sizeof(struct gve_nic_ts_report)),
+ .nic_timestamp_addr = cpu_to_be64(nic_ts_report_addr),
+ };
+
+ return gve_adminq_execute_cmd(priv, &cmd);
+}
+
/* The device specifies that the management vector can either be the first irq
* or the last irq. ntfy_blk_msix_base_idx indicates the first irq assigned to
* the ntfy blks. It if is 0 then the management vector is last, if it is 1 then
diff --git a/drivers/net/gve/base/gve_adminq.h b/drivers/net/gve/base/gve_adminq.h
index eaee5649f2..954be39fbf 100644
--- a/drivers/net/gve/base/gve_adminq.h
+++ b/drivers/net/gve/base/gve_adminq.h
@@ -26,6 +26,7 @@ enum gve_adminq_opcodes {
GVE_ADMINQ_REPORT_LINK_SPEED = 0xD,
GVE_ADMINQ_GET_PTYPE_MAP = 0xE,
GVE_ADMINQ_VERIFY_DRIVER_COMPATIBILITY = 0xF,
+ GVE_ADMINQ_REPORT_NIC_TIMESTAMP = 0x11,
/* For commands that are larger than 56 bytes */
GVE_ADMINQ_EXTENDED_COMMAND = 0xFF,
};
@@ -373,6 +374,23 @@ struct gve_stats_report {
GVE_CHECK_STRUCT_LEN(8, gve_stats_report);
+struct gve_adminq_report_nic_timestamp {
+ __be64 nic_ts_report_len;
+ __be64 nic_timestamp_addr;
+};
+
+GVE_CHECK_STRUCT_LEN(16, gve_adminq_report_nic_timestamp);
+
+struct gve_nic_ts_report {
+ __be64 nic_timestamp; /* NIC clock in nanoseconds */
+ __be64 pre_cycles; /* System cycle counter before NIC clock read */
+ __be64 post_cycles; /* System cycle counter after NIC clock read */
+ __be64 reserved3;
+ __be64 reserved4;
+};
+
+GVE_CHECK_STRUCT_LEN(40, gve_nic_ts_report);
+
/* Numbers of gve tx/rx stats in stats report. */
#define GVE_TX_STATS_REPORT_NUM 6
#define GVE_RX_STATS_REPORT_NUM 2
@@ -490,6 +508,7 @@ union gve_adminq_command {
struct gve_adminq_verify_driver_compatibility
verify_driver_compatibility;
struct gve_adminq_extended_command extended_command;
+ struct gve_adminq_report_nic_timestamp report_nic_timestamp;
};
};
u8 reserved[64];
@@ -537,5 +556,6 @@ int gve_adminq_add_flow_rule(struct gve_priv *priv,
struct gve_flow_rule_params *rule, u32 loc);
int gve_adminq_del_flow_rule(struct gve_priv *priv, u32 loc);
int gve_adminq_reset_flow_rules(struct gve_priv *priv);
+int gve_adminq_report_nic_timestamp(struct gve_priv *priv, dma_addr_t nic_ts_report_addr);
#endif /* _GVE_ADMINQ_H */
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
index b9b4688367..b67f82c263 100644
--- a/drivers/net/gve/gve_ethdev.h
+++ b/drivers/net/gve/gve_ethdev.h
@@ -328,6 +328,7 @@ struct gve_priv {
uint32_t adminq_get_ptype_map_cnt;
uint32_t adminq_verify_driver_compatibility_cnt;
uint32_t adminq_cfg_flow_rule_cnt;
+ uint32_t adminq_report_nic_timestamp_cnt;
volatile uint32_t state_flags;
/* Gvnic device link speed from hypervisor. */
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 2/6] net/gve: add device option support for HW timestamps
From: mark-blasko @ 2026-05-12 0:50 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko, Joshua Washington, Jasper Tran O'Leary
In-Reply-To: <20260512005057.944672-1-blasko@google.com>
From: Mark Blasko <blasko@google.com>
Introduce the necessary definitions and functions for the device
option flag (GVE_DEV_OPT_ID_NIC_TIMESTAMP) to detect hardware
timestamping support in the gvnic device.
Signed-off-by: Mark Blasko <blasko@google.com>
Reviewed-by: Joshua Washington <joshwash@google.com>
Reviewed-by: Jasper Tran O'Leary <jtranoleary@google.com>
---
drivers/net/gve/base/gve_adminq.c | 41 ++++++++++++++++++++++++++-----
drivers/net/gve/base/gve_adminq.h | 9 +++++++
drivers/net/gve/gve_ethdev.h | 3 +++
3 files changed, 47 insertions(+), 6 deletions(-)
diff --git a/drivers/net/gve/base/gve_adminq.c b/drivers/net/gve/base/gve_adminq.c
index 28661fb6cd..c9095fd165 100644
--- a/drivers/net/gve/base/gve_adminq.c
+++ b/drivers/net/gve/base/gve_adminq.c
@@ -38,7 +38,8 @@ void gve_parse_device_option(struct gve_priv *priv,
struct gve_device_option_dqo_rda **dev_op_dqo_rda,
struct gve_device_option_flow_steering **dev_op_flow_steering,
struct gve_device_option_modify_ring **dev_op_modify_ring,
- struct gve_device_option_jumbo_frames **dev_op_jumbo_frames)
+ struct gve_device_option_jumbo_frames **dev_op_jumbo_frames,
+ struct gve_device_option_nic_timestamp **dev_op_nic_timestamp)
{
u32 req_feat_mask = be32_to_cpu(option->required_features_mask);
u16 option_length = be16_to_cpu(option->option_length);
@@ -168,6 +169,24 @@ void gve_parse_device_option(struct gve_priv *priv,
}
*dev_op_jumbo_frames = RTE_PTR_ADD(option, sizeof(*option));
break;
+ case GVE_DEV_OPT_ID_NIC_TIMESTAMP:
+ if (option_length < sizeof(**dev_op_nic_timestamp) ||
+ req_feat_mask != GVE_DEV_OPT_REQ_FEAT_MASK_NIC_TIMESTAMP) {
+ PMD_DRV_LOG(WARNING, GVE_DEVICE_OPTION_ERROR_FMT,
+ "Nic Timestamp",
+ (int)sizeof(**dev_op_nic_timestamp),
+ GVE_DEV_OPT_REQ_FEAT_MASK_NIC_TIMESTAMP,
+ option_length, req_feat_mask);
+ break;
+ }
+
+ if (option_length > sizeof(**dev_op_nic_timestamp)) {
+ PMD_DRV_LOG(WARNING,
+ GVE_DEVICE_OPTION_TOO_BIG_FMT,
+ "Nic Timestamp");
+ }
+ *dev_op_nic_timestamp = RTE_PTR_ADD(option, sizeof(*option));
+ break;
default:
/* If we don't recognize the option just continue
* without doing anything.
@@ -186,7 +205,8 @@ gve_process_device_options(struct gve_priv *priv,
struct gve_device_option_dqo_rda **dev_op_dqo_rda,
struct gve_device_option_flow_steering **dev_op_flow_steering,
struct gve_device_option_modify_ring **dev_op_modify_ring,
- struct gve_device_option_jumbo_frames **dev_op_jumbo_frames)
+ struct gve_device_option_jumbo_frames **dev_op_jumbo_frames,
+ struct gve_device_option_nic_timestamp **dev_op_nic_timestamp)
{
const int num_options = be16_to_cpu(descriptor->num_device_options);
struct gve_device_option *dev_opt;
@@ -207,7 +227,8 @@ gve_process_device_options(struct gve_priv *priv,
gve_parse_device_option(priv, dev_opt,
dev_op_gqi_rda, dev_op_gqi_qpl,
dev_op_dqo_rda, dev_op_flow_steering,
- dev_op_modify_ring, dev_op_jumbo_frames);
+ dev_op_modify_ring, dev_op_jumbo_frames,
+ dev_op_nic_timestamp);
dev_opt = next_opt;
}
@@ -921,7 +942,8 @@ static void gve_enable_supported_features(struct gve_priv *priv,
u32 supported_features_mask,
const struct gve_device_option_flow_steering *dev_op_flow_steering,
const struct gve_device_option_modify_ring *dev_op_modify_ring,
- const struct gve_device_option_jumbo_frames *dev_op_jumbo_frames)
+ const struct gve_device_option_jumbo_frames *dev_op_jumbo_frames,
+ const struct gve_device_option_nic_timestamp *dev_op_nic_timestamp)
{
if (dev_op_flow_steering &&
(supported_features_mask & GVE_SUP_FLOW_STEERING_MASK) &&
@@ -948,6 +970,11 @@ static void gve_enable_supported_features(struct gve_priv *priv,
PMD_DRV_LOG(INFO, "JUMBO FRAMES device option enabled.");
priv->max_mtu = be16_to_cpu(dev_op_jumbo_frames->max_mtu);
}
+ if (dev_op_nic_timestamp &&
+ (supported_features_mask & GVE_SUP_NIC_TIMESTAMP_MASK)) {
+ PMD_DRV_LOG(INFO, "NIC TIMESTAMP device option enabled.");
+ priv->nic_timestamp_supported = true;
+ }
}
int gve_adminq_describe_device(struct gve_priv *priv)
@@ -955,6 +982,7 @@ int gve_adminq_describe_device(struct gve_priv *priv)
struct gve_device_option_jumbo_frames *dev_op_jumbo_frames = NULL;
struct gve_device_option_modify_ring *dev_op_modify_ring = NULL;
struct gve_device_option_flow_steering *dev_op_flow_steering = NULL;
+ struct gve_device_option_nic_timestamp *dev_op_nic_timestamp = NULL;
struct gve_device_option_gqi_rda *dev_op_gqi_rda = NULL;
struct gve_device_option_gqi_qpl *dev_op_gqi_qpl = NULL;
struct gve_device_option_dqo_rda *dev_op_dqo_rda = NULL;
@@ -984,7 +1012,8 @@ int gve_adminq_describe_device(struct gve_priv *priv)
&dev_op_gqi_qpl, &dev_op_dqo_rda,
&dev_op_flow_steering,
&dev_op_modify_ring,
- &dev_op_jumbo_frames);
+ &dev_op_jumbo_frames,
+ &dev_op_nic_timestamp);
if (err)
goto free_device_descriptor;
@@ -1039,7 +1068,7 @@ int gve_adminq_describe_device(struct gve_priv *priv)
gve_enable_supported_features(priv, supported_features_mask,
dev_op_flow_steering, dev_op_modify_ring,
- dev_op_jumbo_frames);
+ dev_op_jumbo_frames, dev_op_nic_timestamp);
free_device_descriptor:
gve_free_dma_mem(&descriptor_dma_mem);
diff --git a/drivers/net/gve/base/gve_adminq.h b/drivers/net/gve/base/gve_adminq.h
index d8e5e6a352..eaee5649f2 100644
--- a/drivers/net/gve/base/gve_adminq.h
+++ b/drivers/net/gve/base/gve_adminq.h
@@ -153,6 +153,12 @@ struct gve_device_option_jumbo_frames {
GVE_CHECK_STRUCT_LEN(8, gve_device_option_jumbo_frames);
+struct gve_device_option_nic_timestamp {
+ __be32 supported_features_mask;
+};
+
+GVE_CHECK_STRUCT_LEN(4, gve_device_option_nic_timestamp);
+
/* Terminology:
*
* RDA - Raw DMA Addressing - Buffers associated with SKBs are directly DMA
@@ -169,6 +175,7 @@ enum gve_dev_opt_id {
GVE_DEV_OPT_ID_MODIFY_RING = 0x6,
GVE_DEV_OPT_ID_JUMBO_FRAMES = 0x8,
GVE_DEV_OPT_ID_FLOW_STEERING = 0xb,
+ GVE_DEV_OPT_ID_NIC_TIMESTAMP = 0xd,
};
enum gve_dev_opt_req_feat_mask {
@@ -179,12 +186,14 @@ enum gve_dev_opt_req_feat_mask {
GVE_DEV_OPT_REQ_FEAT_MASK_FLOW_STEERING = 0x0,
GVE_DEV_OPT_REQ_FEAT_MASK_MODIFY_RING = 0x0,
GVE_DEV_OPT_REQ_FEAT_MASK_JUMBO_FRAMES = 0x0,
+ GVE_DEV_OPT_REQ_FEAT_MASK_NIC_TIMESTAMP = 0x0,
};
enum gve_sup_feature_mask {
GVE_SUP_MODIFY_RING_MASK = 1 << 0,
GVE_SUP_JUMBO_FRAMES_MASK = 1 << 2,
GVE_SUP_FLOW_STEERING_MASK = 1 << 5,
+ GVE_SUP_NIC_TIMESTAMP_MASK = 1 << 8,
};
#define GVE_DEV_OPT_LEN_GQI_RAW_ADDRESSING 0x0
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
index 524e48e723..b9b4688367 100644
--- a/drivers/net/gve/gve_ethdev.h
+++ b/drivers/net/gve/gve_ethdev.h
@@ -355,6 +355,9 @@ struct gve_priv {
void *avail_flow_rule_bmp_mem; /* Backing memory for the bitmap */
pthread_mutex_t flow_rule_lock; /* Lock for bitmap and tailq access */
TAILQ_HEAD(, gve_flow) active_flows;
+
+ /* HW Timestamping Fields */
+ bool nic_timestamp_supported;
};
static inline bool
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* [PATCH 0/6] net/gve: add hardware timestamping support
From: mark-blasko @ 2026-05-12 0:50 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko
From: Mark Blasko <blasko@google.com>
This patch series introduces support for GVE hardware timestamping on DQO
queues. To support concurrent access, a mutex lock is introduced to protect
admin queue operations. A mechanism is then added to periodically synchronize
the NIC clock via AdminQ, and support is introduced for the read_clock ethdev
operation. Finally, the RX datapath is updated to reconstruct full 64-bit
timestamps from the 32-bit values in DQO descriptors.
Mark Blasko (6):
net/gve: add thread safety to admin queue
net/gve: add device option support for HW timestamps
net/gve: add AdminQ command for NIC timestamps
net/gve: add periodic NIC clock synchronization
net/gve: support read clock ethdev op
net/gve: reconstruct HW timestamps from DQO
.mailmap | 1 +
doc/guides/nics/features/gve.ini | 1 +
doc/guides/nics/gve.rst | 18 +++
doc/guides/rel_notes/release_26_07.rst | 3 +
drivers/net/gve/base/gve_adminq.c | 127 +++++++++++++++++----
drivers/net/gve/base/gve_adminq.h | 29 +++++
drivers/net/gve/base/gve_desc_dqo.h | 8 +-
drivers/net/gve/gve_ethdev.c | 148 ++++++++++++++++++++++++-
drivers/net/gve/gve_ethdev.h | 39 +++++++
drivers/net/gve/gve_rx_dqo.c | 26 +++++
10 files changed, 378 insertions(+), 22 deletions(-)
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply
* [PATCH 1/6] net/gve: add thread safety to admin queue
From: mark-blasko @ 2026-05-12 0:50 UTC (permalink / raw)
To: stephen; +Cc: dev, Mark Blasko, Joshua Washington, Jasper Tran O'Leary
In-Reply-To: <20260512005057.944672-1-blasko@google.com>
From: Mark Blasko <blasko@google.com>
Introduce a pthread_mutex to protect the admin queue operations.
Locking was added around gve_adminq_execute_cmd and the batch
queue creation/destruction functions.
Signed-off-by: Mark Blasko <blasko@google.com>
Reviewed-by: Joshua Washington <joshwash@google.com>
Reviewed-by: Jasper Tran O'Leary <jtranoleary@google.com>
---
.mailmap | 1 +
drivers/net/gve/base/gve_adminq.c | 68 +++++++++++++++++++++++++------
drivers/net/gve/gve_ethdev.h | 1 +
3 files changed, 57 insertions(+), 13 deletions(-)
diff --git a/.mailmap b/.mailmap
index 3ab7364668..7f7590866b 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1009,6 +1009,7 @@ Mario Carrillo <mario.alfredo.c.arevalo@intel.com>
Mário Kuka <kuka@cesnet.cz>
Mariusz Drost <mariuszx.drost@intel.com>
Mark Asselstine <mark.asselstine@windriver.com>
+Mark Blasko <blasko@google.com>
Mark Bloch <mbloch@nvidia.com> <markb@mellanox.com>
Mark Gillott <mgillott@vyatta.att-mail.com>
Mark Kavanagh <mark.b.kavanagh@intel.com>
diff --git a/drivers/net/gve/base/gve_adminq.c b/drivers/net/gve/base/gve_adminq.c
index 9c5316fb00..28661fb6cd 100644
--- a/drivers/net/gve/base/gve_adminq.c
+++ b/drivers/net/gve/base/gve_adminq.c
@@ -216,6 +216,7 @@ gve_process_device_options(struct gve_priv *priv,
int gve_adminq_alloc(struct gve_priv *priv)
{
+ pthread_mutexattr_t mutexattr;
uint8_t pci_rev_id;
priv->adminq = gve_alloc_dma_mem(&priv->adminq_dma_mem, PAGE_SIZE);
@@ -241,6 +242,12 @@ int gve_adminq_alloc(struct gve_priv *priv)
priv->adminq_get_ptype_map_cnt = 0;
priv->adminq_cfg_flow_rule_cnt = 0;
+ pthread_mutexattr_init(&mutexattr);
+ pthread_mutexattr_setpshared(&mutexattr, PTHREAD_PROCESS_SHARED);
+ pthread_mutexattr_setrobust(&mutexattr, PTHREAD_MUTEX_ROBUST);
+ pthread_mutex_init(&priv->adminq_lock, &mutexattr);
+ pthread_mutexattr_destroy(&mutexattr);
+
/* Setup Admin queue with the device */
rte_pci_read_config(priv->pci_dev, &pci_rev_id, sizeof(pci_rev_id),
RTE_PCI_REVISION_ID);
@@ -304,6 +311,7 @@ void gve_adminq_free(struct gve_priv *priv)
return;
gve_adminq_release(priv);
gve_free_dma_mem(&priv->adminq_dma_mem);
+ pthread_mutex_destroy(&priv->adminq_lock);
gve_clear_admin_queue_ok(priv);
}
@@ -418,7 +426,10 @@ static int gve_adminq_issue_cmd(struct gve_priv *priv,
(tail & priv->adminq_mask)) {
int err;
- /* Flush existing commands to make room. */
+ /* Flush existing commands to make room.
+ * Note: This kicks the doorbell for all staged commands.
+ * Any failure here means we failed after attempting to kick.
+ */
err = gve_adminq_kick_and_wait(priv);
if (err)
return err;
@@ -509,17 +520,24 @@ static int gve_adminq_execute_cmd(struct gve_priv *priv,
u32 tail, head;
int err;
+ pthread_mutex_lock(&priv->adminq_lock);
tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
head = priv->adminq_prod_cnt;
- if (tail != head)
+ if (tail != head) {
/* This is not a valid path */
- return -EINVAL;
+ err = -EINVAL;
+ goto unlock_and_return;
+ }
err = gve_adminq_issue_cmd(priv, cmd_orig);
if (err)
- return err;
+ goto unlock_and_return;
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_adminq_execute_extended_cmd(struct gve_priv *priv, u32 opcode,
@@ -693,13 +711,19 @@ int gve_adminq_create_tx_queues(struct gve_priv *priv, u32 num_queues)
int err;
u32 i;
+ pthread_mutex_lock(&priv->adminq_lock);
+
for (i = 0; i < num_queues; i++) {
err = gve_adminq_create_tx_queue(priv, i);
if (err)
- return err;
+ goto unlock_and_return;
}
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index)
@@ -747,13 +771,19 @@ int gve_adminq_create_rx_queues(struct gve_priv *priv, u32 num_queues)
int err;
u32 i;
+ pthread_mutex_lock(&priv->adminq_lock);
+
for (i = 0; i < num_queues; i++) {
err = gve_adminq_create_rx_queue(priv, i);
if (err)
- return err;
+ goto unlock_and_return;
}
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_adminq_destroy_tx_queue(struct gve_priv *priv, u32 queue_index)
@@ -779,13 +809,19 @@ int gve_adminq_destroy_tx_queues(struct gve_priv *priv, u32 num_queues)
int err;
u32 i;
+ pthread_mutex_lock(&priv->adminq_lock);
+
for (i = 0; i < num_queues; i++) {
err = gve_adminq_destroy_tx_queue(priv, i);
if (err)
- return err;
+ goto unlock_and_return;
}
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_adminq_destroy_rx_queue(struct gve_priv *priv, u32 queue_index)
@@ -811,13 +847,19 @@ int gve_adminq_destroy_rx_queues(struct gve_priv *priv, u32 num_queues)
int err;
u32 i;
+ pthread_mutex_lock(&priv->adminq_lock);
+
for (i = 0; i < num_queues; i++) {
err = gve_adminq_destroy_rx_queue(priv, i);
if (err)
- return err;
+ goto unlock_and_return;
}
- return gve_adminq_kick_and_wait(priv);
+ err = gve_adminq_kick_and_wait(priv);
+
+unlock_and_return:
+ pthread_mutex_unlock(&priv->adminq_lock);
+ return err;
}
static int gve_set_desc_cnt(struct gve_priv *priv,
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
index 0577f03974..524e48e723 100644
--- a/drivers/net/gve/gve_ethdev.h
+++ b/drivers/net/gve/gve_ethdev.h
@@ -339,6 +339,7 @@ struct gve_priv {
struct gve_tx_queue **txqs;
struct gve_rx_queue **rxqs;
+ pthread_mutex_t adminq_lock; /* Protects AdminQ command execution */
uint32_t stats_report_len;
const struct rte_memzone *stats_report_mem;
uint16_t stats_start_idx; /* start index of array of stats written by NIC */
--
2.54.0.563.g4f69b47b94-goog
^ permalink raw reply related
* Re: [PATCH v2] ring: add cache guard after ring elements table
From: Wathsala Vithanage @ 2026-05-11 23:29 UTC (permalink / raw)
To: Morten Brørup, dev, Konstantin Ananyev; +Cc: Konstantin Ananyev
In-Reply-To: <20260505161329.258182-1-mb@smartsharesystems.com>
Acked-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
On 5/5/26 11:13, Morten Brørup wrote:
> Added cache guard after the table holding the ring elements, to avoid
> false sharing conflicts caused by next-line hardware prefetchers when
> accessing elements at the end of the ring table.
>
> Signed-off-by: Morten Brørup <mb@smartsharesystems.com>
> Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
> ---
> v2:
> * Added comment describing reason for padding. (Konstantin)
> ---
> lib/ring/rte_ring.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/lib/ring/rte_ring.c b/lib/ring/rte_ring.c
> index f10050a1c4..10b52dc679 100644
> --- a/lib/ring/rte_ring.c
> +++ b/lib/ring/rte_ring.c
> @@ -73,8 +73,15 @@ rte_ring_get_memsize_elem(unsigned int esize, unsigned int count)
> return -EINVAL;
> }
>
> + static_assert(sizeof(struct rte_ring) == RTE_CACHE_LINE_ROUNDUP(sizeof(struct rte_ring)),
> + "Size of struct rte_ring not cache line aligned");
> sz = sizeof(struct rte_ring) + (ssize_t)count * esize;
> + /* Add padding, to guard against false sharing-like effects
> + * on systems with a next-N-lines hardware prefetcher, when
> + * accessing elements at the end of the ring table.
> + */
> sz = RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE);
> + sz += RTE_CACHE_GUARD_LINES * RTE_CACHE_LINE_SIZE;
> return sz;
> }
>
^ permalink raw reply
* [PATCH] ci: update versions of actions in GHA
From: David Marchand @ 2026-05-11 16:11 UTC (permalink / raw)
To: dev; +Cc: stable, Aaron Conole
GitHub started deprecating GHA actions based on Node 20.
For now, only warnings are raised, but we can switch to more recent
versions of the common actions, now:
- cache v5
- checkout v6
- upload-artifact v7
- setup-python v6
Link: https://github.blog/changelog/2025-09-19-deprecation-of-node-20-on-github-actions-runners/
Cc: stable@dpdk.org
Signed-off-by: David Marchand <david.marchand@redhat.com>
---
.github/workflows/build.yml | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index b3e2957411..f0ef39d34f 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -21,7 +21,7 @@ jobs:
runs-on: ubuntu-24.04
steps:
- name: Checkout sources
- uses: actions/checkout@v4
+ uses: actions/checkout@v6
with:
fetch-depth: 0
- name: Check patches
@@ -121,7 +121,7 @@ jobs:
steps:
- name: Checkout sources
- uses: actions/checkout@v4
+ uses: actions/checkout@v6
- name: Generate cache keys
id: get_ref_keys
run: |
@@ -129,7 +129,7 @@ jobs:
echo 'libabigail=libabigail-${{ env.LIBABIGAIL_VERSION }}-${{ matrix.config.os }}' >> $GITHUB_OUTPUT
echo 'abi=abi-${{ matrix.config.os }}-${{ matrix.config.compiler }}-${{ matrix.config.cross }}-${{ env.REF_GIT_TAG }}' >> $GITHUB_OUTPUT
- name: Retrieve ccache cache
- uses: actions/cache@v4
+ uses: actions/cache@v5
with:
path: ~/.ccache
key: ${{ steps.get_ref_keys.outputs.ccache }}-${{ github.ref }}
@@ -137,13 +137,13 @@ jobs:
${{ steps.get_ref_keys.outputs.ccache }}-refs/heads/main
- name: Retrieve libabigail cache
id: libabigail-cache
- uses: actions/cache@v4
+ uses: actions/cache@v5
if: env.ABI_CHECKS == 'true'
with:
path: libabigail
key: ${{ steps.get_ref_keys.outputs.libabigail }}
- name: Retrieve ABI reference cache
- uses: actions/cache@v4
+ uses: actions/cache@v5
if: env.ABI_CHECKS == 'true'
with:
path: reference
@@ -195,7 +195,7 @@ jobs:
key: ${{ steps.get_ref_keys.outputs.ccache }}-${{ github.ref }}
- name: Upload logs on failure
if: failure()
- uses: actions/upload-artifact@v4
+ uses: actions/upload-artifact@v7
with:
name: meson-logs-${{ join(matrix.config.*, '-') }}
path: |
@@ -216,9 +216,9 @@ jobs:
steps:
- name: Checkout sources
- uses: actions/checkout@v4
+ uses: actions/checkout@v6
- name: Set up Python
- uses: actions/setup-python@v5
+ uses: actions/setup-python@v6
with:
python-version: '3.x'
- name: Install dependencies
@@ -235,7 +235,7 @@ jobs:
meson compile -C build
- name: Upload logs on failure
if: failure()
- uses: actions/upload-artifact@v4
+ uses: actions/upload-artifact@v7
with:
name: meson-logs-${{ join(matrix.config.*, '-') }}
path: |
@@ -287,7 +287,7 @@ jobs:
echo 'image=image-${{ matrix.config.image }}-'$(date -u +%Y-%m-%d) >> $GITHUB_OUTPUT
- name: Retrieve image cache
id: image_cache
- uses: actions/cache@v4
+ uses: actions/cache@v5
with:
path: ~/.image
key: ${{ steps.get_keys.outputs.image }}
@@ -331,7 +331,7 @@ jobs:
steps:
- name: Checkout sources
- uses: actions/checkout@v4
+ uses: actions/checkout@v6
- name: Generate various keys
id: get_keys
run: |
@@ -339,7 +339,7 @@ jobs:
echo 'logs=meson-logs-${{ join(matrix.config.*, '-') }}' | tr -d ':' >> $GITHUB_OUTPUT
- name: Retrieve image cache
id: image_cache
- uses: actions/cache@v4
+ uses: actions/cache@v5
with:
path: ~/.image
key: ${{ needs.prepare-container-images.outputs.image }}
@@ -349,7 +349,7 @@ jobs:
echo 'Image ${{ matrix.config.image }} is not cached.'
false
- name: Retrieve ccache cache
- uses: actions/cache@v4
+ uses: actions/cache@v5
with:
path: ~/.ccache
key: ${{ steps.get_keys.outputs.ccache }}-${{ github.ref }}
@@ -388,7 +388,7 @@ jobs:
run: docker kill dpdk
- name: Upload logs on failure
if: failure()
- uses: actions/upload-artifact@v4
+ uses: actions/upload-artifact@v7
with:
name: ${{ steps.get_keys.outputs.logs }}
path: |
--
2.53.0
^ permalink raw reply related
* [PATCH v4] dts: update test suite names to be clear and consistent
From: Andrew Bailey @ 2026-05-11 16:00 UTC (permalink / raw)
To: luca.vizzarro, patrickrobb1997
Cc: dev, lylavoie, knimoji, ahassick, Andrew Bailey
In-Reply-To: <20260508141319.52648-1-abailey@iol.unh.edu>
Some test suites were prefixed with PMD which is not meaningful.
Other test suites used inconsistent naming schemes which this patch
makes uniform. For example, some suites had abbreviated words that
others had not. These words are no longer abbreviated among any test
suite.
Bugzilla ID: 1826
Signed-off-by: Andrew Bailey <abailey@iol.unh.edu>
---
doc/api/dts/tests.TestSuite_buffer_scatter.rst | 8 ++++++++
doc/api/dts/tests.TestSuite_flow_offload.rst | 8 ++++++++
doc/api/dts/tests.TestSuite_pmd_buffer_scatter.rst | 8 --------
| 8 --------
doc/api/dts/tests.TestSuite_queue_start_stop.rst | 8 --------
doc/api/dts/tests.TestSuite_queue_toggle.rst | 8 ++++++++
| 6 +++---
doc/api/dts/tests.TestSuite_rte_flow.rst | 8 --------
doc/api/dts/tests.TestSuite_unified_packet.rst | 8 ++++++++
doc/api/dts/tests.TestSuite_virtio_forward.rst | 8 ++++++++
doc/api/dts/tests.TestSuite_virtio_fwd.rst | 8 --------
..._pmd_buffer_scatter.py => TestSuite_buffer_scatter.py} | 2 +-
.../{TestSuite_rte_flow.py => TestSuite_flow_offload.py} | 4 ++--
...uite_queue_start_stop.py => TestSuite_queue_toggle.py} | 2 +-
| 4 ++--
.../{TestSuite_uni_pkt.py => TestSuite_unified_packet.py} | 2 +-
...estSuite_virtio_fwd.py => TestSuite_virtio_forward.py} | 2 +-
17 files changed, 51 insertions(+), 51 deletions(-)
create mode 100644 doc/api/dts/tests.TestSuite_buffer_scatter.rst
create mode 100644 doc/api/dts/tests.TestSuite_flow_offload.rst
delete mode 100644 doc/api/dts/tests.TestSuite_pmd_buffer_scatter.rst
delete mode 100644 doc/api/dts/tests.TestSuite_pmd_rss.rst
delete mode 100644 doc/api/dts/tests.TestSuite_queue_start_stop.rst
create mode 100644 doc/api/dts/tests.TestSuite_queue_toggle.rst
rename doc/api/dts/{tests.TestSuite_uni_pkt.rst => tests.TestSuite_rss.rst} (50%)
delete mode 100644 doc/api/dts/tests.TestSuite_rte_flow.rst
create mode 100644 doc/api/dts/tests.TestSuite_unified_packet.rst
create mode 100644 doc/api/dts/tests.TestSuite_virtio_forward.rst
delete mode 100644 doc/api/dts/tests.TestSuite_virtio_fwd.rst
rename dts/tests/{TestSuite_pmd_buffer_scatter.py => TestSuite_buffer_scatter.py} (99%)
rename dts/tests/{TestSuite_rte_flow.py => TestSuite_flow_offload.py} (99%)
rename dts/tests/{TestSuite_queue_start_stop.py => TestSuite_queue_toggle.py} (99%)
rename dts/tests/{TestSuite_pmd_rss.py => TestSuite_rss.py} (99%)
rename dts/tests/{TestSuite_uni_pkt.py => TestSuite_unified_packet.py} (99%)
rename dts/tests/{TestSuite_virtio_fwd.py => TestSuite_virtio_forward.py} (99%)
diff --git a/doc/api/dts/tests.TestSuite_buffer_scatter.rst b/doc/api/dts/tests.TestSuite_buffer_scatter.rst
new file mode 100644
index 0000000000..ce764ff0d6
--- /dev/null
+++ b/doc/api/dts/tests.TestSuite_buffer_scatter.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+
+buffer_scatter Test Suite
+=========================
+
+.. automodule:: tests.TestSuite_buffer_scatter
+ :members:
+ :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_flow_offload.rst b/doc/api/dts/tests.TestSuite_flow_offload.rst
new file mode 100644
index 0000000000..5fcd3f57c3
--- /dev/null
+++ b/doc/api/dts/tests.TestSuite_flow_offload.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+
+flow_offload Test Suite
+=======================
+
+.. automodule:: tests.TestSuite_flow_offload
+ :members:
+ :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_pmd_buffer_scatter.rst b/doc/api/dts/tests.TestSuite_pmd_buffer_scatter.rst
deleted file mode 100644
index cdf30fd879..0000000000
--- a/doc/api/dts/tests.TestSuite_pmd_buffer_scatter.rst
+++ /dev/null
@@ -1,8 +0,0 @@
-.. SPDX-License-Identifier: BSD-3-Clause
-
-pmd_buffer_scatter Test Suite
-=============================
-
-.. automodule:: tests.TestSuite_pmd_buffer_scatter
- :members:
- :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_pmd_rss.rst b/doc/api/dts/tests.TestSuite_pmd_rss.rst
deleted file mode 100644
index 942fa5ebdc..0000000000
--- a/doc/api/dts/tests.TestSuite_pmd_rss.rst
+++ /dev/null
@@ -1,8 +0,0 @@
-.. SPDX-License-Identifier: BSD-3-Clause
-
-pmd_rss Test Suite
-==================
-
-.. automodule:: tests.TestSuite_pmd_rss
- :members:
- :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_queue_start_stop.rst b/doc/api/dts/tests.TestSuite_queue_start_stop.rst
deleted file mode 100644
index 87121676fb..0000000000
--- a/doc/api/dts/tests.TestSuite_queue_start_stop.rst
+++ /dev/null
@@ -1,8 +0,0 @@
-.. SPDX-License-Identifier: BSD-3-Clause
-
-queue_start_stop Test Suite
-===========================
-
-.. automodule:: tests.TestSuite_queue_start_stop
- :members:
- :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_queue_toggle.rst b/doc/api/dts/tests.TestSuite_queue_toggle.rst
new file mode 100644
index 0000000000..1d6345511f
--- /dev/null
+++ b/doc/api/dts/tests.TestSuite_queue_toggle.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+
+queue_toggle Test Suite
+=======================
+
+.. automodule:: tests.TestSuite_queue_toggle
+ :members:
+ :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_uni_pkt.rst b/doc/api/dts/tests.TestSuite_rss.rst
similarity index 50%
rename from doc/api/dts/tests.TestSuite_uni_pkt.rst
rename to doc/api/dts/tests.TestSuite_rss.rst
index 95c5a5a28b..ecd8676b09 100644
--- a/doc/api/dts/tests.TestSuite_uni_pkt.rst
+++ b/doc/api/dts/tests.TestSuite_rss.rst
@@ -1,8 +1,8 @@
.. SPDX-License-Identifier: BSD-3-Clause
-uni_pkt Test Suite
-==================
+rss Test Suite
+==============
-.. automodule:: tests.TestSuite_uni_pkt
+.. automodule:: tests.TestSuite_rss
:members:
:show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_rte_flow.rst b/doc/api/dts/tests.TestSuite_rte_flow.rst
deleted file mode 100644
index eacbfd3a2a..0000000000
--- a/doc/api/dts/tests.TestSuite_rte_flow.rst
+++ /dev/null
@@ -1,8 +0,0 @@
-.. SPDX-License-Identifier: BSD-3-Clause
-
-rte_flow Test Suite
-===================
-
-.. automodule:: tests.TestSuite_rte_flow
- :members:
- :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_unified_packet.rst b/doc/api/dts/tests.TestSuite_unified_packet.rst
new file mode 100644
index 0000000000..dddf12b18a
--- /dev/null
+++ b/doc/api/dts/tests.TestSuite_unified_packet.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+
+unified_packet Test Suite
+=========================
+
+.. automodule:: tests.TestSuite_unified_packet
+ :members:
+ :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_virtio_forward.rst b/doc/api/dts/tests.TestSuite_virtio_forward.rst
new file mode 100644
index 0000000000..9178c73be5
--- /dev/null
+++ b/doc/api/dts/tests.TestSuite_virtio_forward.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+
+virtio_forward Test Suite
+=========================
+
+.. automodule:: tests.TestSuite_virtio_forward
+ :members:
+ :show-inheritance:
diff --git a/doc/api/dts/tests.TestSuite_virtio_fwd.rst b/doc/api/dts/tests.TestSuite_virtio_fwd.rst
deleted file mode 100644
index e40cc4ca2b..0000000000
--- a/doc/api/dts/tests.TestSuite_virtio_fwd.rst
+++ /dev/null
@@ -1,8 +0,0 @@
-.. SPDX-License-Identifier: BSD-3-Clause
-
-virtio_fwd Test Suite
-=====================
-
-.. automodule:: tests.TestSuite_virtio_fwd
- :members:
- :show-inheritance:
diff --git a/dts/tests/TestSuite_pmd_buffer_scatter.py b/dts/tests/TestSuite_buffer_scatter.py
similarity index 99%
rename from dts/tests/TestSuite_pmd_buffer_scatter.py
rename to dts/tests/TestSuite_buffer_scatter.py
index 96da67ee7d..539082f2e4 100644
--- a/dts/tests/TestSuite_pmd_buffer_scatter.py
+++ b/dts/tests/TestSuite_buffer_scatter.py
@@ -35,7 +35,7 @@
@requires_nic_capability(NicCapability.PHYSICAL_FUNCTION)
@requires_nic_capability(NicCapability.PORT_RX_OFFLOAD_SCATTER)
-class TestPmdBufferScatter(TestSuite):
+class TestBufferScatter(TestSuite):
"""DPDK PMD packet scattering test suite.
Configure the Rx queues to have mbuf data buffers
diff --git a/dts/tests/TestSuite_rte_flow.py b/dts/tests/TestSuite_flow_offload.py
similarity index 99%
rename from dts/tests/TestSuite_rte_flow.py
rename to dts/tests/TestSuite_flow_offload.py
index 6255e4c36d..be11d09875 100644
--- a/dts/tests/TestSuite_rte_flow.py
+++ b/dts/tests/TestSuite_flow_offload.py
@@ -402,8 +402,8 @@ def generate(
@requires_nic_capability(NicCapability.FLOW_CTRL)
-class TestRteFlow(TestSuite):
- """RTE Flow test suite.
+class TestFlowOffload(TestSuite):
+ """Flow offload test suite.
This suite consists of 4 test cases:
1. Queue Action: Verifies queue actions with multi-protocol patterns
diff --git a/dts/tests/TestSuite_queue_start_stop.py b/dts/tests/TestSuite_queue_toggle.py
similarity index 99%
rename from dts/tests/TestSuite_queue_start_stop.py
rename to dts/tests/TestSuite_queue_toggle.py
index e9048d4245..e4edc89123 100644
--- a/dts/tests/TestSuite_queue_start_stop.py
+++ b/dts/tests/TestSuite_queue_toggle.py
@@ -32,7 +32,7 @@
@requires_link_topology(LinkTopology.TWO_LINKS)
@requires_nic_capability(NicCapability.RUNTIME_RX_QUEUE_SETUP)
@requires_nic_capability(NicCapability.RUNTIME_TX_QUEUE_SETUP)
-class TestQueueStartStop(TestSuite):
+class TestQueueToggle(TestSuite):
"""DPDK Queue start/stop test suite.
Ensures Rx/Tx queue on a port can be disabled and enabled.
--git a/dts/tests/TestSuite_pmd_rss.py b/dts/tests/TestSuite_rss.py
similarity index 99%
rename from dts/tests/TestSuite_pmd_rss.py
rename to dts/tests/TestSuite_rss.py
index f6adf262c3..2747c8a36c 100644
--- a/dts/tests/TestSuite_pmd_rss.py
+++ b/dts/tests/TestSuite_rss.py
@@ -55,8 +55,8 @@ class HashAlgorithm(StrEnum):
@requires_link_topology(LinkTopology.ONE_LINK)
@requires_nic_capability(NicCapability.PORT_RX_OFFLOAD_RSS_HASH)
-class TestPmdRss(TestSuite):
- """PMD RSS test suite."""
+class TestRss(TestSuite):
+ """RSS test suite."""
config: Config
diff --git a/dts/tests/TestSuite_uni_pkt.py b/dts/tests/TestSuite_unified_packet.py
similarity index 99%
rename from dts/tests/TestSuite_uni_pkt.py
rename to dts/tests/TestSuite_unified_packet.py
index 222276ce67..fcc7f7fbbb 100644
--- a/dts/tests/TestSuite_uni_pkt.py
+++ b/dts/tests/TestSuite_unified_packet.py
@@ -31,7 +31,7 @@
from framework.test_suite import TestSuite, func_test
-class TestUniPkt(TestSuite):
+class TestUnifiedPacket(TestSuite):
"""DPDK Unified packet test suite.
This testing suite uses testpmd's verbose output hardware/software
diff --git a/dts/tests/TestSuite_virtio_fwd.py b/dts/tests/TestSuite_virtio_forward.py
similarity index 99%
rename from dts/tests/TestSuite_virtio_fwd.py
rename to dts/tests/TestSuite_virtio_forward.py
index bdecdb76fd..6efaa4e156 100644
--- a/dts/tests/TestSuite_virtio_fwd.py
+++ b/dts/tests/TestSuite_virtio_forward.py
@@ -20,7 +20,7 @@
from framework.testbed_model.virtual_device import VirtualDevice
-class TestVirtioFwd(TestSuite):
+class TestVirtioForward(TestSuite):
"""Virtio forwarding test suite."""
virtio_user_vdev = VirtualDevice(
--
2.50.1
^ permalink raw reply related
* [PATCH v2] dts: add ipgre test suite
From: Andrew Bailey @ 2026-05-11 15:46 UTC (permalink / raw)
To: luca.vizzarro, patrickrobb1997
Cc: dev, ahassick, lylavoie, knimoji, Andrew Bailey
In-Reply-To: <20260327180232.443820-1-abailey@iol.unh.edu>
Port over the IP GRE test suite from old DTS to next DTS. This test
suite covers GRE tunneling and checksum offload verification using this
protocol.
Bugzilla ID: 1480
Signed-off-by: Andrew Bailey <abailey@iol.unh.edu>
---
doc/api/dts/tests.TestSuite_ip_gre.rst | 8 +
dts/api/testpmd/__init__.py | 23 ++
dts/tests/TestSuite_ip_gre.py | 301 +++++++++++++++++++++++++
3 files changed, 332 insertions(+)
create mode 100644 doc/api/dts/tests.TestSuite_ip_gre.rst
create mode 100644 dts/tests/TestSuite_ip_gre.py
diff --git a/doc/api/dts/tests.TestSuite_ip_gre.rst b/doc/api/dts/tests.TestSuite_ip_gre.rst
new file mode 100644
index 0000000000..e8ce01dc0b
--- /dev/null
+++ b/doc/api/dts/tests.TestSuite_ip_gre.rst
@@ -0,0 +1,8 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+
+ip_gre Test Suite
+=================
+
+.. automodule:: tests.TestSuite_ip_gre
+ :members:
+ :show-inheritance:
diff --git a/dts/api/testpmd/__init__.py b/dts/api/testpmd/__init__.py
index e9187440bb..bb5cbd6725 100644
--- a/dts/api/testpmd/__init__.py
+++ b/dts/api/testpmd/__init__.py
@@ -951,6 +951,29 @@ def set_flow_control(
f"Testpmd failed to set the {flow_ctrl} in port {port}."
)
+ def set_csum_parse_tunnel(self, port: int, on: bool, verify: bool = True) -> None:
+ """Set parse tunnel on or of in testpmd for a given port.
+
+ Args:
+ port: The ID of the requested port
+ on: set parse tunnel on if `on` is :data:`True`, otherwise off
+ verify: if :data:`True`, the output of the command is scanned to verify that
+ parse tunnel was set successfully
+
+ Raises:
+ InteractiveCommandExecutionError: If `verify` is :data:`True` and the command
+ fails to execute.
+
+ """
+ output = self.send_command(f"csum parse-tunnel {'on' if on else 'off'} {port}")
+ if verify and f"Parse tunnel is {'on' if on else'off'}" not in output:
+ self._logger.debug(
+ f"Testpmd failed to set csum parse-tunnel {'on' if on else 'off'} in port {port}"
+ )
+ raise InteractiveCommandExecutionError(
+ f"Testpmd failed to set csum parse-tunnel {'on' if on else 'off'} in port {port}"
+ )
+
def show_port_flow_info(self, port: int) -> TestPmdPortFlowCtrl | None:
"""Show port info flow.
diff --git a/dts/tests/TestSuite_ip_gre.py b/dts/tests/TestSuite_ip_gre.py
new file mode 100644
index 0000000000..fc51eef181
--- /dev/null
+++ b/dts/tests/TestSuite_ip_gre.py
@@ -0,0 +1,301 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2026 University of New Hampshire
+
+"""DPDK IP GRE test suite."""
+
+from scapy.layers.inet import GRE, IP, TCP, UDP
+from scapy.layers.inet6 import IPv6
+from scapy.layers.l2 import Dot1Q, Ether
+from scapy.layers.sctp import SCTP
+from scapy.packet import Packet
+
+from api.capabilities import (
+ NicCapability,
+ requires_nic_capability,
+)
+from api.packet import send_packet_and_capture
+from api.test import verify
+from api.testpmd import TestPmd
+from api.testpmd.config import SimpleForwardingModes
+from api.testpmd.types import (
+ ChecksumOffloadOptions,
+ PacketOffloadFlag,
+ RtePTypes,
+ TestPmdVerbosePacket,
+)
+from framework.test_suite import TestSuite, func_test
+
+SRC_ID = "FF:FF:FF:FF:FF:FF"
+
+
+class TestIpGre(TestSuite):
+ """IP GRE test suite."""
+
+ def _check_for_matching_packet(
+ self, output: list[TestPmdVerbosePacket], flags: RtePTypes
+ ) -> bool:
+ """Returns :data:`True` if the packet in verbose output contains all specified flags."""
+ for packet in output:
+ if packet.src_mac == SRC_ID:
+ if flags not in packet.hw_ptype and flags not in packet.sw_ptype:
+ return False
+ return True
+
+ def _send_packet_and_verify_flags(
+ self, expected_flag: RtePTypes, packet: Packet, testpmd: TestPmd
+ ) -> None:
+ """Sends a packet to the DUT and verifies the verbose ptype flags."""
+ send_packet_and_capture(packet=packet)
+ verbose_output = testpmd.extract_verbose_output(testpmd.stop(verify=True))
+ valid = self._check_for_matching_packet(output=verbose_output, flags=expected_flag)
+ verify(valid, f"Packet type flag did not match the expected flag: {expected_flag}.")
+
+ def _setup_session(
+ self, testpmd: TestPmd, expected_flags: list[RtePTypes], packet_list=list[Packet]
+ ) -> None:
+ """Sets the forwarding and verbose mode of each test case interactive shell session."""
+ testpmd.set_forward_mode(SimpleForwardingModes.rxonly)
+ testpmd.set_verbose(level=1)
+ for i in range(0, len(packet_list)):
+ testpmd.start(verify=True)
+ self._send_packet_and_verify_flags(
+ expected_flag=expected_flags[i], packet=packet_list[i], testpmd=testpmd
+ )
+
+ def _send_packet_and_verify_checksum(
+ self, packet: Packet, good_L4: bool, good_IP: bool, testpmd: TestPmd
+ ) -> None:
+ """Send packet and verify verbose output matches expected output."""
+ testpmd.start()
+ send_packet_and_capture(packet=packet)
+ verbose_output = testpmd.extract_verbose_output(testpmd.stop())
+ is_IP = is_L4 = None
+ for testpmd_packet in verbose_output:
+ if testpmd_packet.src_mac == SRC_ID:
+ is_IP = PacketOffloadFlag.RTE_MBUF_F_RX_IP_CKSUM_GOOD in testpmd_packet.ol_flags
+ is_L4 = PacketOffloadFlag.RTE_MBUF_F_RX_L4_CKSUM_GOOD in testpmd_packet.ol_flags
+ verify(
+ is_IP is not None and is_L4 is not None,
+ "Test packet was dropped when it should have been received.",
+ )
+ verify(is_L4 == good_L4, "Layer 4 checksum flag did not match expected checksum flag.")
+ verify(is_IP == good_IP, "IP checksum flag did not match expected checksum flag.")
+
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_GRE_TNL_TSO)
+ @func_test
+ def gre_ip4_pkt_detect(self) -> None:
+ """GRE IP4 packet send and detect.
+
+ Steps:
+ * Craft packets using GRE tunneling.
+ * Send them to the testpmd application.
+
+ Verify:
+ * All packets were received.
+ """
+ packets = [
+ Ether(src=SRC_ID) / IP() / GRE() / IP() / UDP(),
+ Ether(src=SRC_ID) / IP() / GRE() / IP() / TCP(),
+ Ether(src=SRC_ID) / IP() / GRE() / IP() / SCTP(),
+ Ether(src=SRC_ID) / Dot1Q() / IP() / GRE() / IP() / UDP(),
+ Ether(src=SRC_ID) / Dot1Q() / IP() / GRE() / IP() / TCP(),
+ Ether(src=SRC_ID) / Dot1Q() / IP() / GRE() / IP() / SCTP(),
+ ]
+ flags = [
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV4
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_UDP,
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV4
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_TCP,
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV4
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_SCTP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV4
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_UDP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV4
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_TCP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV4
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_SCTP,
+ ]
+ with TestPmd() as testpmd:
+ self._setup_session(testpmd=testpmd, expected_flags=flags, packet_list=packets)
+
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_GRE_TNL_TSO)
+ @func_test
+ def gre_ip6_outer_ip4_inner_pkt_detect(self) -> None:
+ """GRE IPv6 outer and IPv4 inner send and detect.
+
+ Steps:
+ * Craft packets using GRE tunneling.
+ * Send them to the testpmd application.
+
+ Verify:
+ * All packets were received.
+ """
+ packets = [
+ Ether(src=SRC_ID) / IPv6() / GRE() / IP() / UDP(),
+ Ether(src=SRC_ID) / IPv6() / GRE() / IP() / TCP(),
+ Ether(src=SRC_ID) / IPv6() / GRE() / IP() / SCTP(),
+ Ether(src=SRC_ID) / Dot1Q() / IPv6() / GRE() / IP() / UDP(),
+ Ether(src=SRC_ID) / Dot1Q() / IPv6() / GRE() / IP() / TCP(),
+ Ether(src=SRC_ID) / Dot1Q() / IPv6() / GRE() / IP() / SCTP(),
+ ]
+ flags = [
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_UDP,
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_TCP,
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_SCTP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_UDP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_TCP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV4
+ | RtePTypes.INNER_L4_SCTP,
+ ]
+ with TestPmd() as testpmd:
+ self._setup_session(testpmd=testpmd, expected_flags=flags, packet_list=packets)
+
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_GRE_TNL_TSO)
+ @func_test
+ def gre_ip6_outer_ip6_inner_pkt_detect(self) -> None:
+ """GRE IPv6 outer and inner send and detect.
+
+ Steps:
+ * Craft packets using GRE tunneling.
+ * Send them to the testpmd application.
+
+ Verify:
+ * All packets were received.
+ """
+ packets = [
+ Ether(src=SRC_ID) / IPv6() / GRE() / IPv6() / UDP(),
+ Ether(src=SRC_ID) / IPv6() / GRE() / IPv6() / TCP(),
+ Ether(src=SRC_ID) / IPv6() / GRE() / IPv6() / SCTP(),
+ Ether(src=SRC_ID) / Dot1Q() / IPv6() / GRE() / IPv6() / UDP(),
+ Ether(src=SRC_ID) / Dot1Q() / IPv6() / GRE() / IPv6() / TCP(),
+ Ether(src=SRC_ID) / Dot1Q() / IPv6() / GRE() / IPv6() / SCTP(),
+ ]
+ flags = [
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV6
+ | RtePTypes.INNER_L4_UDP,
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV6
+ | RtePTypes.INNER_L4_TCP,
+ RtePTypes.L2_ETHER
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV6
+ | RtePTypes.INNER_L4_SCTP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV6
+ | RtePTypes.INNER_L4_UDP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV6
+ | RtePTypes.INNER_L4_TCP,
+ RtePTypes.L2_ETHER_VLAN
+ | RtePTypes.L3_IPV6
+ | RtePTypes.TUNNEL_GRE
+ | RtePTypes.INNER_L3_IPV6
+ | RtePTypes.INNER_L4_SCTP,
+ ]
+ with TestPmd() as testpmd:
+ self._setup_session(testpmd=testpmd, expected_flags=flags, packet_list=packets)
+
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_OUTER_IPV4_CKSUM)
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_IPV4_CKSUM)
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_TCP_CKSUM)
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_UDP_CKSUM)
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_SCTP_CKSUM)
+ @requires_nic_capability(NicCapability.PORT_TX_OFFLOAD_GRE_TNL_TSO)
+ @func_test
+ def gre_checksum_offload(self) -> None:
+ """GRE checksum offload test.
+
+ Steps:
+ * Craft packets using GRE tunneling.
+ * Alter checksum of each packet.
+ * Send packets to the testpmd application.
+
+ Verify:
+ * All packets were received with the expected checksum flags.
+ """
+ packets = [
+ Ether(src=SRC_ID) / IP(chksum=0x0) / GRE() / IP() / TCP(),
+ Ether(src=SRC_ID) / IP() / GRE() / IP(chksum=0x0) / TCP(),
+ Ether(src=SRC_ID) / IP() / GRE() / IP() / TCP(chksum=0x0),
+ Ether(src=SRC_ID) / IP() / GRE() / IP() / UDP(chksum=0xFFFF),
+ Ether(src=SRC_ID) / IP() / GRE() / IP() / SCTP(chksum=0x0),
+ ]
+ good_l4_ip = [
+ (True, True),
+ (True, False),
+ (False, True),
+ (False, True),
+ (False, True),
+ ]
+ with TestPmd() as testpmd:
+ testpmd.set_forward_mode(SimpleForwardingModes.csum)
+ testpmd.csum_set_hw(
+ layers=ChecksumOffloadOptions.ip
+ | ChecksumOffloadOptions.udp
+ | ChecksumOffloadOptions.outer_ip
+ | ChecksumOffloadOptions.sctp
+ | ChecksumOffloadOptions.tcp,
+ port_id=0,
+ )
+ testpmd.set_csum_parse_tunnel(port=0, on=True)
+ testpmd.set_verbose(1)
+ testpmd.start_all_ports()
+ testpmd.start()
+ for i in range(len(packets)):
+ self._send_packet_and_verify_checksum(
+ packets[i],
+ good_l4_ip[i][0],
+ good_l4_ip[i][1],
+ testpmd,
+ )
--
2.50.1
^ permalink raw reply related
* [PATCH v2] dts: clean cryptodev environment after a test run
From: Andrew Bailey @ 2026-05-11 15:31 UTC (permalink / raw)
To: luca.vizzarro, patrickrobb1997
Cc: lylavoie, knimoji, ahassick, dev, Andrew Bailey
In-Reply-To: <20260507163659.40739-1-abailey@iol.unh.edu>
Prior to this patch, the virtual functions created by DTS for crypto
devices were not properly cleanedu up. This could lead to a system to be
left in a bad state after running the cryptodev throughput test suite.
This patch properly cleans up the environment after cryptodev testing.
Bugzilla ID: 1923
Fixes: 8ee2df9da125 ("dts: add cryptodev package")
Signed-off-by: Andrew Bailey <abailey@iol.unh.edu>
---
dts/framework/testbed_model/linux_session.py | 29 +++++++++++++++++++-
dts/framework/testbed_model/os_session.py | 8 ++++++
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/dts/framework/testbed_model/linux_session.py b/dts/framework/testbed_model/linux_session.py
index ee943462c2..6e40552d21 100644
--- a/dts/framework/testbed_model/linux_session.py
+++ b/dts/framework/testbed_model/linux_session.py
@@ -181,6 +181,22 @@ def get_port_info(self, pci_address: str) -> PortInfo:
return PortInfo(mac_address, logical_name, driver, is_link_up)
+ def unbind_ports(self, ports):
+ """Overrides :meth:`~.os_session.OSSession.unbind_ports`.
+
+ The :attr:`~.devbind_script_path` property must be setup in order to call this method.
+ """
+ ports_pci_addrs = " ".join(port.pci for port in ports)
+
+ self.send_command(
+ f"{self.devbind_script_path} -u --force {ports_pci_addrs}",
+ privileged=True,
+ verify=True,
+ )
+
+ if self._lshw_net_info:
+ del self._lshw_net_info
+
def bind_ports_to_driver(self, ports: list[Port], driver_name: str) -> None:
"""Overrides :meth:`~.os_session.OSSession.bind_ports_to_driver`.
@@ -289,7 +305,18 @@ def create_vfs(self, pf_port: Port) -> None:
self.refresh_lshw()
def delete_crypto_vfs(self, pf_port: Port) -> None:
- """Overrides :meth:`~.os_session.OSSession.delete_crypto_vfs`."""
+ """Overrides :meth:`~.os_session.OSSession.delete_crypto_vfs`.
+
+ The :attr:`~.devbind_script_path` property must be setup in order to call this method.
+ """
+ if vfs := self.get_pci_addr_of_crypto_vfs(pf_port):
+ vf_pci_addrs = " ".join(vf for vf in vfs)
+ self.send_command(
+ f"{self.devbind_script_path} -u --force {vf_pci_addrs}",
+ privileged=True,
+ verify=True,
+ )
+ self.unbind_ports([pf_port])
self.send_command(
f"echo 1 | sudo tee /sys/bus/pci/devices/{pf_port.pci}/remove".replace(":", "\\:"),
privileged=True,
diff --git a/dts/framework/testbed_model/os_session.py b/dts/framework/testbed_model/os_session.py
index 2c267afed1..f2dc9b20a9 100644
--- a/dts/framework/testbed_model/os_session.py
+++ b/dts/framework/testbed_model/os_session.py
@@ -573,6 +573,14 @@ def get_port_info(self, pci_address: str) -> PortInfo:
ConfigurationError: If the port could not be found.
"""
+ @abstractmethod
+ def unbind_ports(self, ports: list[Port]) -> None:
+ """Unbind `ports` from any driver.
+
+ Args:
+ ports: The list of ports to unbind.
+ """
+
@abstractmethod
def bind_ports_to_driver(self, ports: list[Port], driver_name: str) -> None:
"""Bind `ports` to the given `driver_name`.
--
2.50.1
^ permalink raw reply related
* [PATCH v2] mbuf: fix mbuf operations history recording
From: Morten Brørup @ 2026-05-11 13:39 UTC (permalink / raw)
To: dev, Shani Peretz, Thomas Monjalon, Konstantin Ananyev
Cc: Morten Brørup, stable
In-Reply-To: <20260419221220.86455-1-mb@smartsharesystems.com>
This addresses two bugs in mbuf operations history recording.
1. With mbuf operations history recording enabled, when allocating mbufs
from a mempool failed, the array of fetched mbuf pointers was not set, but
it was dereferenced for mbuf operations history recording anyway, which
would trigger a segmentation fault or cause undefined behavior.
This was fixed by changing how the return value from the mempool
allocation is checked, so the function returns early on failure, and only
proceeds on success.
2. When allocating a bulk of mbufs using rte_pktmbuf_alloc_bulk(), two
mbuf library allocation operations were recorded on the mbuf, because the
function calls rte_mbuf_raw_alloc_bulk() for allocation, and both
functions record a mbuf library allocation operation.
This was fixed by not recording a mbuf library allocation operation in
rte_pktmbuf_alloc_bulk().
3. When freeing a bulk of segmented mbufs, the free operations were only
recorded on the first segments.
This was fixed by freeing the pending bulks of segments using
rte_mbuf_raw_free_bulk(), which records the free operation on the mbufs,
instead of calling rte_mempool_put_bulk() directly.
The bulk operation recording at the start of the function, which only
affected the first segments of segmented packets, was removed.
Fixes: d265a24a32a4 ("mbuf: record mbuf operations history")
Cc: stable@dpdk.org
Signed-off-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Konstantin Ananyev <konstantin.ananyev@huawei.com>
---
v2:
* Added fix for rte_pktmbuf_free_bulk.
---
lib/mbuf/rte_mbuf.c | 8 +++-----
lib/mbuf/rte_mbuf.h | 12 +++++-------
2 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/lib/mbuf/rte_mbuf.c b/lib/mbuf/rte_mbuf.c
index c2476e7704..005bfaa573 100644
--- a/lib/mbuf/rte_mbuf.c
+++ b/lib/mbuf/rte_mbuf.c
@@ -540,8 +540,8 @@ __rte_pktmbuf_free_seg_via_array(struct rte_mbuf *m,
if (likely(m != NULL)) {
if (*nb_pending == pending_sz ||
(*nb_pending > 0 && m->pool != pending[0]->pool)) {
- rte_mempool_put_bulk(pending[0]->pool,
- (void **)pending, *nb_pending);
+ rte_mbuf_raw_free_bulk(pending[0]->pool,
+ pending, *nb_pending);
*nb_pending = 0;
}
@@ -562,8 +562,6 @@ void rte_pktmbuf_free_bulk(struct rte_mbuf **mbufs, unsigned int count)
struct rte_mbuf *m, *m_next, *pending[RTE_PKTMBUF_FREE_PENDING_SZ];
unsigned int idx, nb_pending = 0;
- rte_mbuf_history_mark_bulk(mbufs, count, RTE_MBUF_HISTORY_OP_LIB_FREE);
-
for (idx = 0; idx < count; idx++) {
m = mbufs[idx];
if (unlikely(m == NULL))
@@ -581,7 +579,7 @@ void rte_pktmbuf_free_bulk(struct rte_mbuf **mbufs, unsigned int count)
}
if (nb_pending > 0)
- rte_mempool_put_bulk(pending[0]->pool, (void **)pending, nb_pending);
+ rte_mbuf_raw_free_bulk(pending[0]->pool, pending, nb_pending);
}
/* Creates a shallow copy of mbuf */
diff --git a/lib/mbuf/rte_mbuf.h b/lib/mbuf/rte_mbuf.h
index e7c3bbadd4..60ec8158cd 100644
--- a/lib/mbuf/rte_mbuf.h
+++ b/lib/mbuf/rte_mbuf.h
@@ -663,14 +663,14 @@ static __rte_always_inline int
rte_mbuf_raw_alloc_bulk(struct rte_mempool *mp, struct rte_mbuf **mbufs, unsigned int count)
{
int rc = rte_mempool_get_bulk(mp, (void **)mbufs, count);
- if (likely(rc == 0)) {
- for (unsigned int idx = 0; idx < count; idx++)
- __rte_mbuf_raw_sanity_check_mp(mbufs[idx], mp);
- }
+ if (unlikely(rc))
+ return rc;
+ for (unsigned int idx = 0; idx < count; idx++)
+ __rte_mbuf_raw_sanity_check_mp(mbufs[idx], mp);
rte_mbuf_history_mark_bulk(mbufs, count, RTE_MBUF_HISTORY_OP_LIB_ALLOC);
- return rc;
+ return 0;
}
/**
@@ -1068,8 +1068,6 @@ static inline int rte_pktmbuf_alloc_bulk(struct rte_mempool *pool,
if (unlikely(rc))
return rc;
- rte_mbuf_history_mark_bulk(mbufs, count, RTE_MBUF_HISTORY_OP_LIB_ALLOC);
-
rte_mbuf_raw_reset_bulk(pool, mbufs, count);
return 0;
--
2.43.0
^ permalink raw reply related
* Re: [PATCH] doc: add link to mbuf layout history
From: Thomas Monjalon @ 2026-05-11 13:00 UTC (permalink / raw)
To: Morten Brørup; +Cc: dev
In-Reply-To: <98CBD80474FA8B44BF855DF32C47DC35F657D8@smartserver.smartshare.dk>
07/04/2026 10:44, Morten Brørup:
> > From: Thomas Monjalon [mailto:thomas@monjalon.net]
> > Sent: Tuesday, 7 April 2026 10.06
> >
> > In order to illustrate how mbuf is kept small,
> > add a link to a page showing the mbuf layout for each version.
> >
> > Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
> > ---
> > doc/guides/prog_guide/mbuf_lib.rst | 11 ++++++-----
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/doc/guides/prog_guide/mbuf_lib.rst
> > b/doc/guides/prog_guide/mbuf_lib.rst
> > index 382bfbdca4..97f8e72356 100644
> > --- a/doc/guides/prog_guide/mbuf_lib.rst
> > +++ b/doc/guides/prog_guide/mbuf_lib.rst
> > @@ -8,11 +8,12 @@ The Packet (MBuf) library provides the ability to
> > allocate and free buffers (mbu
> > that may be used by the DPDK application to store message buffers.
> > The message buffers are stored in a mempool, using the
> > :doc:`mempool_lib`.
> >
> > -A rte_mbuf struct generally carries network packet buffers, but it can
> > actually
> > -be any data (control data, events, ...).
> > -The rte_mbuf header structure is kept as small as possible and
> > currently uses
> > -just two cache lines, with the most frequently used fields being on
> > the first
> > -of the two cache lines.
> > +A ``struct rte_mbuf`` generally carries network packet buffers,
> > +but it can actually be any data (control data, events, etc).
> > +The ``rte_mbuf`` header structure is
> > +`kept as small as possible
> > <https://doc.dpdk.org/struct/mbuf/history.html>`_
> > +and currently uses just two 64-byte cache lines,
> > +with the most frequently used fields being on the first of the two
> > cache lines.
> >
> > Design of Packet Buffers
> > ------------------------
> > --
> > 2.53.0
>
> Hadn't noticed that illustration before, so good idea linking to it here.
>
> Acked-by: Morten Brørup <mb@smartsharesystems.com>
Applied
^ permalink raw reply
* [PATCH v4 20/20] net/txgbe: fix to enable Tx desc check
From: Zaiyu Wang @ 2026-05-11 10:36 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
Now lib security is enabled by default, and cannot be disabled if the
driver is intended to be used. So Tdm_desc_chk is always unable to enable.
Remove this restriction, and just enable the corresponding queue check.
Fixes: 0eabdfcd4af4 ("net/txgbe: enable Tx descriptor error interrupt")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/txgbe_rxtx.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c
index ef53a868a6..8b3d5eec14 100644
--- a/drivers/net/txgbe/txgbe_rxtx.c
+++ b/drivers/net/txgbe/txgbe_rxtx.c
@@ -4768,6 +4768,12 @@ txgbe_dev_tx_init(struct rte_eth_dev *dev)
wr32(hw, TXGBE_TXRP(txq->reg_idx), 0);
wr32(hw, TXGBE_TXWP(txq->reg_idx), 0);
+#ifdef RTE_LIBRTE_SECURITY
+ if (!(txq->using_ipsec))
+#endif
+ wr32m(hw, TXGBE_TDM_DESC_CHK(txq->reg_idx / 32),
+ BIT(txq->reg_idx % 32), BIT(txq->reg_idx % 32));
+
if (txq->headwb_mem) {
uint32_t txdctl;
@@ -4785,11 +4791,6 @@ txgbe_dev_tx_init(struct rte_eth_dev *dev)
}
}
-#ifndef RTE_LIB_SECURITY
- for (i = 0; i < 4; i++)
- wr32(hw, TXGBE_TDM_DESC_CHK(i), 0xFFFFFFFF);
-#endif
-
/* Device configured with multiple TX queues. */
txgbe_dev_mq_tx_configure(dev);
}
--
2.21.0.windows.1
^ permalink raw reply related
* [PATCH v4 19/20] net/txgbe: fix to reset Tx write-back pointer
From: Zaiyu Wang @ 2026-05-11 10:36 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
The write-back pointer was not reset when the Tx queue was reset. This
leads to the wrong Tx desc free logic. Move the resetting of pointer into
txq->ops->reset(txq).
Fixes: 8ada71d0bb7f ("net/txgbe: add Tx head write-back mode for Amber-Lite")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/txgbe_rxtx.c | 45 +++++++++++++----------
drivers/net/txgbe/txgbe_rxtx.h | 1 +
drivers/net/txgbe/txgbe_rxtx_vec_common.h | 7 ++++
3 files changed, 33 insertions(+), 20 deletions(-)
diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c
index 851cd122d8..ef53a868a6 100644
--- a/drivers/net/txgbe/txgbe_rxtx.c
+++ b/drivers/net/txgbe/txgbe_rxtx.c
@@ -2320,6 +2320,12 @@ txgbe_reset_tx_queue(struct txgbe_tx_queue *txq)
txq->tx_next_dd = (uint16_t)(txq->tx_free_thresh - 1);
txq->tx_tail = 0;
+ /* Zero out headwb_mem memory */
+ if (txq->headwb_mem) {
+ for (i = 0; i < txq->headwb_size; i++)
+ txq->headwb_mem[i] = 0;
+ }
+
/*
* Always allow 1 descriptor to be un-allocated to avoid
* a H/W race condition
@@ -2419,7 +2425,7 @@ txgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
return tx_offload_capa;
}
-static int
+static void
txgbe_setup_headwb_resources(struct rte_eth_dev *dev,
void *tx_queue,
unsigned int socket_id)
@@ -2427,33 +2433,33 @@ txgbe_setup_headwb_resources(struct rte_eth_dev *dev,
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
const struct rte_memzone *headwb;
struct txgbe_tx_queue *txq = tx_queue;
- u8 i, headwb_size = 0;
+ u8 headwb_size = 0;
- if (hw->mac.type != txgbe_mac_aml && hw->mac.type != txgbe_mac_aml40) {
- txq->headwb_mem = NULL;
- return 0;
- }
+ if (hw->mac.type != txgbe_mac_aml && hw->mac.type != txgbe_mac_aml40)
+ goto out;
+
+ if (!hw->devarg.tx_headwb)
+ goto out;
- headwb_size = hw->devarg.tx_headwb_size;
+ headwb_size = txq->headwb_size;
headwb = rte_eth_dma_zone_reserve(dev, "tx_headwb_mem", txq->queue_id,
sizeof(u32) * headwb_size,
TXGBE_ALIGN, socket_id);
if (headwb == NULL) {
- DEBUGOUT("Fail to setup headwb resources: no mem");
- txgbe_tx_queue_release(txq);
- return -ENOMEM;
+ PMD_DRV_LOG(INFO,
+ "Failed to allocate headwb memory for Tx queue %u, change to SP mode",
+ txq->queue_id);
+ goto out;
}
txq->headwb = headwb;
txq->headwb_dma = TMZ_PADDR(headwb);
txq->headwb_mem = (uint32_t *)TMZ_VADDR(headwb);
+ return;
- /* Zero out headwb_mem memory */
- for (i = 0; i < headwb_size; i++)
- txq->headwb_mem[i] = 0;
-
- return 0;
+out:
+ txq->headwb_mem = NULL;
}
int __rte_cold
@@ -2549,6 +2555,7 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
txq->offloads = offloads;
txq->ops = &def_txq_ops;
txq->tx_deferred_start = tx_conf->tx_deferred_start;
+ txq->headwb_size = hw->devarg.tx_headwb_size;
#ifdef RTE_LIB_SECURITY
txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
RTE_ETH_TX_OFFLOAD_SECURITY);
@@ -2584,8 +2591,7 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
/* set up scalar TX function as appropriate */
txgbe_set_tx_function(dev, txq);
- if (hw->devarg.tx_headwb)
- err = txgbe_setup_headwb_resources(dev, txq, socket_id);
+ txgbe_setup_headwb_resources(dev, txq, socket_id);
txq->ops->reset(txq);
txq->desc_error = 0;
@@ -4762,15 +4768,14 @@ txgbe_dev_tx_init(struct rte_eth_dev *dev)
wr32(hw, TXGBE_TXRP(txq->reg_idx), 0);
wr32(hw, TXGBE_TXWP(txq->reg_idx), 0);
- if ((hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) &&
- hw->devarg.tx_headwb) {
+ if (txq->headwb_mem) {
uint32_t txdctl;
wr32(hw, TXGBE_PX_TR_HEAD_ADDRL(txq->reg_idx),
(uint32_t)(txq->headwb_dma & BIT_MASK32));
wr32(hw, TXGBE_PX_TR_HEAD_ADDRH(txq->reg_idx),
(uint32_t)(txq->headwb_dma >> 32));
- if (hw->devarg.tx_headwb_size == 16)
+ if (txq->headwb_size == 16)
txdctl = TXGBE_PX_TR_CFG_HEAD_WB |
TXGBE_PX_TR_CFG_HEAD_WB_64BYTE;
else
diff --git a/drivers/net/txgbe/txgbe_rxtx.h b/drivers/net/txgbe/txgbe_rxtx.h
index 02e2617cce..237bb64697 100644
--- a/drivers/net/txgbe/txgbe_rxtx.h
+++ b/drivers/net/txgbe/txgbe_rxtx.h
@@ -416,6 +416,7 @@ struct txgbe_tx_queue {
uint64_t desc_error;
bool resetting;
const struct rte_memzone *headwb;
+ uint16_t headwb_size;
uint64_t headwb_dma;
volatile uint32_t *headwb_mem;
};
diff --git a/drivers/net/txgbe/txgbe_rxtx_vec_common.h b/drivers/net/txgbe/txgbe_rxtx_vec_common.h
index edf3586b77..594886c5b1 100644
--- a/drivers/net/txgbe/txgbe_rxtx_vec_common.h
+++ b/drivers/net/txgbe/txgbe_rxtx_vec_common.h
@@ -255,6 +255,13 @@ _txgbe_reset_tx_queue_vec(struct txgbe_tx_queue *txq)
txq->tx_next_dd = (uint16_t)(txq->tx_free_thresh - 1);
txq->tx_tail = 0;
+
+ /* Zero out headwb_mem memory */
+ if (txq->headwb_mem) {
+ for (i = 0; i < txq->headwb_size; i++)
+ txq->headwb_mem[i] = 0;
+ }
+
/*
* Always allow 1 descriptor to be un-allocated to avoid
* a H/W race condition
--
2.21.0.windows.1
^ permalink raw reply related
* [PATCH v4 17/20] net/txgbe: fix get module info operation
From: Zaiyu Wang @ 2026-05-11 10:35 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
The original I2C access flow in the module information retrieval
process was flawed. Correct the implementation to properly fetch
module info.
Fixes: abf042d32b39 ("net/txgbe: add Amber-Lite 25G/40G NICs")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_phy.h | 6 +-
drivers/net/txgbe/txgbe_ethdev.c | 116 ++++++++++++++++++++++-------
2 files changed, 95 insertions(+), 27 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index 4da4be0d5f..581f667bdc 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -257,11 +257,15 @@
#define TXGBE_SFF_CABLE_DA_PASSIVE 0x4
#define TXGBE_SFF_CABLE_DA_ACTIVE 0x8
#define TXGBE_SFF_CABLE_SPEC_COMP 0x3C
+#define TXGBE_SFF_DDM_IMPLEMENTED 0x40
#define TXGBE_SFF_SFF_8472_SWAP 0x5C
#define TXGBE_SFF_SFF_8472_COMP 0x5E
#define TXGBE_SFF_SFF_8472_OSCB 0x6E
#define TXGBE_SFF_SFF_8472_ESCB 0x76
-#define TXGBE_SFF_QSFP_PAGE_SELECT 0x7F
+#define TXGBE_SFF_SFF_REVISION_ADDR 0x01
+#define TXGBE_SFF_QSFP_PAGE_SELECT 0x7F
+
+#define TXGBE_MODULE_QSFP_MAX_LEN 640
#define TXGBE_SFF_IDENTIFIER_QSFP 0x0C
#define TXGBE_SFF_IDENTIFIER_QSFP_PLUS 0x0D
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 56987ae028..bc651cfcfb 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -5348,41 +5348,105 @@ txgbe_get_module_info(struct rte_eth_dev *dev,
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
uint32_t status;
uint8_t sff8472_rev, addr_mode;
+ u8 identifier = 0;
+ u8 sff8636_rev = 0;
bool page_swap = false;
+ u32 value;
- /* Check whether we support SFF-8472 or not */
- status = hw->phy.read_i2c_eeprom(hw,
- TXGBE_SFF_SFF_8472_COMP,
- &sff8472_rev);
- if (status != 0)
- return -EIO;
-
- /* addressing mode is not supported */
- status = hw->phy.read_i2c_eeprom(hw,
- TXGBE_SFF_SFF_8472_SWAP,
- &addr_mode);
- if (status != 0)
- return -EIO;
+ if (hw->mac.type == txgbe_mac_aml40) {
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & TXGBE_SFP1_MOD_PRST_LS)
+ return -EIO;
+ }
- if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
- PMD_DRV_LOG(ERR,
- "Address change required to access page 0xA2, "
- "but not supported. Please report the module "
- "type to the driver maintainers.");
- page_swap = true;
+ if (hw->mac.type == txgbe_mac_aml) {
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & TXGBE_SFP1_MOD_ABS_LS)
+ return -EIO;
}
- if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
- /* We have a SFP, but it does not support SFF-8472 */
- modinfo->type = RTE_ETH_MODULE_SFF_8079;
- modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
+ status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
+ if (status)
+ return -EBUSY;
+
+ if (hw->mac.type == txgbe_mac_aml40) {
+ status = hw->phy.read_i2c_sff8636(hw, 0,
+ TXGBE_SFF_IDENTIFIER,
+ &identifier);
} else {
- /* We have a SFP which supports a revision of SFF-8472. */
- modinfo->type = RTE_ETH_MODULE_SFF_8472;
- modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
+ status = hw->phy.read_i2c_eeprom(hw,
+ TXGBE_SFF_IDENTIFIER,
+ &identifier);
}
+ if (status != 0)
+ goto ERROR_IO;
+
+ switch (identifier) {
+ case TXGBE_SFF_IDENTIFIER_SFP:
+ /* Check whether we support SFF-8472 or not */
+ status = hw->phy.read_i2c_eeprom(hw,
+ TXGBE_SFF_SFF_8472_COMP,
+ &sff8472_rev);
+ if (status != 0)
+ goto ERROR_IO;
+
+ /* addressing mode is not supported */
+ status = hw->phy.read_i2c_eeprom(hw,
+ TXGBE_SFF_SFF_8472_SWAP,
+ &addr_mode);
+ if (status != 0)
+ goto ERROR_IO;
+
+ if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
+ PMD_DRV_LOG(ERR,
+ "Address change required to access page 0xA2, "
+ "but not supported. Please report the module "
+ "type to the driver maintainers.");
+ page_swap = true;
+ }
+
+ if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap ||
+ !(addr_mode & TXGBE_SFF_DDM_IMPLEMENTED)) {
+ /* We have a SFP, but it does not support SFF-8472 */
+ modinfo->type = RTE_ETH_MODULE_SFF_8079;
+ modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
+ } else {
+ /* We have a SFP which supports a revision of SFF-8472. */
+ modinfo->type = RTE_ETH_MODULE_SFF_8472;
+ modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
+ }
+ break;
+ case TXGBE_SFF_IDENTIFIER_QSFP:
+ case TXGBE_SFF_IDENTIFIER_QSFP_PLUS:
+ status = hw->phy.read_i2c_sff8636(hw, 0,
+ TXGBE_SFF_SFF_REVISION_ADDR,
+ &sff8636_rev);
+ if (status != 0)
+ goto ERROR_IO;
+ /* Check revision compliance */
+ if (sff8636_rev > 0x02) {
+ /* Module is SFF-8636 compliant */
+ modinfo->type = RTE_ETH_MODULE_SFF_8636;
+ modinfo->eeprom_len = TXGBE_MODULE_QSFP_MAX_LEN;
+ } else {
+ modinfo->type = RTE_ETH_MODULE_SFF_8436;
+ modinfo->eeprom_len = TXGBE_MODULE_QSFP_MAX_LEN;
+ }
+ break;
+ default:
+ PMD_DRV_LOG(ERR, "SFF Module Type not recognized.");
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
+ return -EINVAL;
+ }
+
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return 0;
+
+ERROR_IO:
+ PMD_DRV_LOG(ERR, "I2C IO ERROR.");
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
+ return -EIO;
}
static int
--
2.21.0.windows.1
^ permalink raw reply related
* [PATCH v4 18/20] net/txgbe: fix get EEPROM operation
From: Zaiyu Wang @ 2026-05-11 10:36 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
The original I2C access flow in the module information retrieval
process was flawed. Correct the implementation to properly fetch
module info.
Fixes: abf042d32b39 ("net/txgbe: add Amber-Lite 25G/40G NICs")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/txgbe_ethdev.c | 67 ++++++++++++++++++++++++++++----
1 file changed, 60 insertions(+), 7 deletions(-)
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index bc651cfcfb..d6921704e8 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -5458,23 +5458,76 @@ txgbe_get_module_eeprom(struct rte_eth_dev *dev,
uint8_t databyte = 0xFF;
uint8_t *data = info->data;
uint32_t i = 0;
+ bool is_sfp = false;
+ u32 value;
+ u8 identifier = 0;
+ u16 offset;
+ u8 page = 0;
+
+ if (hw->mac.type == txgbe_mac_aml40) {
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & TXGBE_SFP1_MOD_PRST_LS)
+ return -EIO;
+ }
+
+ if (hw->mac.type == txgbe_mac_aml) {
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & TXGBE_SFP1_MOD_ABS_LS)
+ return -EIO;
+ }
if (info->length == 0)
return -EINVAL;
- for (i = info->offset; i < info->offset + info->length; i++) {
- if (i < RTE_ETH_MODULE_SFF_8079_LEN)
- status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
- else
- status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
+ status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
+ if (status)
+ return -EBUSY;
- if (status != 0)
- return -EIO;
+ status = hw->phy.read_i2c_eeprom(hw,
+ TXGBE_SFF_IDENTIFIER,
+ &identifier);
+ if (status != 0)
+ goto ERROR_IO;
+ if (identifier == TXGBE_SFF_IDENTIFIER_SFP)
+ is_sfp = true;
+
+ memset(data, 0, info->length);
+
+ for (i = info->offset; i < info->offset + info->length; i++) {
+ if (is_sfp) {
+ if (i < RTE_ETH_MODULE_SFF_8079_LEN)
+ status = hw->phy.read_i2c_eeprom(hw, i,
+ &databyte);
+ else
+ status = hw->phy.read_i2c_sff8472(hw, i,
+ &databyte);
+
+ if (status != 0)
+ goto ERROR_IO;
+ } else {
+ offset = i;
+ while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
+ offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
+ page++;
+ }
+ if (page == 0 || !(data[0x2] & 0x4)) {
+ status = hw->phy.read_i2c_sff8636(hw, page, offset,
+ &databyte);
+ if (status != 0)
+ goto ERROR_IO;
+ }
+ }
data[i - info->offset] = databyte;
}
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return 0;
+
+ERROR_IO:
+ PMD_DRV_LOG(ERR, "I2C IO ERROR.");
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
+ return -EIO;
}
bool
--
2.21.0.windows.1
^ permalink raw reply related
* [PATCH v4 16/20] net/txgbe: fix SFP module identification
From: Zaiyu Wang @ 2026-05-11 10:35 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
Some optical modules were not correctly recognized due to ambiguous
classification in the original detection flow. Rework the module
identification logic to cover all module types. Also narrow the
I2C lock scope to avoid potential race conditions during module
access.
Fixes: ab191e6d9189 ("net/txgbe: support new SFP/QSFP modules")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_hw.c | 2 -
drivers/net/txgbe/base/txgbe_phy.c | 339 ++++++++++------------------
drivers/net/txgbe/base/txgbe_phy.h | 18 +-
drivers/net/txgbe/base/txgbe_type.h | 2 +
4 files changed, 132 insertions(+), 229 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 6d76b4854c..16fd9ba20d 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2909,8 +2909,6 @@ s32 txgbe_init_ops_generic(struct txgbe_hw *hw)
phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
phy->identify_sfp = txgbe_identify_module;
- phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked;
- phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
phy->check_overtemp = txgbe_check_overtemp;
phy->reset = txgbe_reset_phy;
phy->set_link_hostif = txgbe_hic_ephy_set_link;
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index f3e3491b30..ac06f9530a 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -830,6 +830,10 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
return TXGBE_ERR_SFP_NOT_PRESENT;
}
+ err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
+ if (err)
+ return -EBUSY;
+
err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
&identifier);
if (err != 0) {
@@ -839,11 +843,13 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
hw->phy.id = 0;
hw->phy.type = txgbe_phy_unknown;
}
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return TXGBE_ERR_SFP_NOT_PRESENT;
}
if (identifier != TXGBE_SFF_IDENTIFIER_SFP) {
hw->phy.type = txgbe_phy_sfp_unsupported;
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return TXGBE_ERR_SFP_NOT_SUPPORTED;
}
@@ -888,7 +894,42 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
* 11 SFP_1g_sx_CORE0 - chip-specific
* 12 SFP_1g_sx_CORE1 - chip-specific
*/
- if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
+ if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
+ else
+ hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
+
+ if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
+ hw->dac_sfp = true;
+ }
+
+ if (comp_copper_len == TXGBE_SFF_COPPER_1M)
+ hw->bypass_ctle = true;
+ else
+ hw->bypass_ctle = false;
+
+ if (comp_codes_25g == TXGBE_SFF_25GBASECR_91FEC ||
+ comp_codes_25g == TXGBE_SFF_25GBASECR_74FEC ||
+ comp_codes_25g == TXGBE_SFF_25GBASECR_NOFEC) {
+ hw->phy.fiber_suppport_speed =
+ TXGBE_LINK_SPEED_25GB_FULL |
+ TXGBE_LINK_SPEED_10GB_FULL;
+ } else {
+ hw->phy.fiber_suppport_speed |=
+ TXGBE_LINK_SPEED_10GB_FULL;
+ }
+ } else if (comp_codes_25g == TXGBE_SFF_25GAUI_C2M_AOC_BER_5 ||
+ comp_codes_25g == TXGBE_SFF_25GAUI_C2M_ACC_BER_5 ||
+ comp_codes_25g == TXGBE_SFF_25GAUI_C2M_AOC_BER_12 ||
+ comp_codes_25g == TXGBE_SFF_25GAUI_C2M_ACC_BER_12) {
+ hw->dac_sfp = false;
+ hw->phy.sfp_type = (hw->bus.lan_id == 0
+ ? txgbe_sfp_type_25g_aoc_core0
+ : txgbe_sfp_type_25g_aoc_core1);
+ } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
+ hw->dac_sfp = false;
err = hw->phy.read_i2c_eeprom(hw,
TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
if (err != 0)
@@ -1005,6 +1046,7 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
/* Allow any DA cable vendor */
if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE |
TXGBE_SFF_CABLE_DA_ACTIVE)) {
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return 0;
}
@@ -1017,6 +1059,7 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
hw->phy.type = txgbe_phy_sfp_unsupported;
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return TXGBE_ERR_SFP_NOT_SUPPORTED;
}
@@ -1031,9 +1074,11 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
DEBUGOUT("SFP+ module not supported");
hw->phy.type = txgbe_phy_sfp_unsupported;
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return TXGBE_ERR_SFP_NOT_SUPPORTED;
}
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return err;
}
@@ -1046,28 +1091,13 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
{
s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
- u32 vendor_oui = 0;
- enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
- u8 identifier = 0;
- u8 comp_codes_1g = 0;
- u8 comp_codes_10g = 0;
- u8 oui_bytes[3] = {0, 0, 0};
- u16 enforce_sfp = 0;
- u8 connector = 0;
- u8 cable_length = 0;
- u8 device_tech = 0;
- bool active_cable = false;
+ u8 identifier = 0, transceiver_type = 0;
u32 value;
- if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
- hw->phy.sfp_type = txgbe_sfp_type_not_present;
- err = TXGBE_ERR_SFP_NOT_PRESENT;
- goto out;
- }
+ /* config GPIO before read i2c */
+ wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_1);
if (hw->mac.type == txgbe_mac_aml40) {
- /* config GPIO before read i2c */
- wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_1);
value = rd32(hw, TXGBE_GPIOEXT);
if (value & TXGBE_SFP1_MOD_PRST_LS) {
hw->phy.sfp_type = txgbe_sfp_type_not_present;
@@ -1075,175 +1105,68 @@ s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
}
}
- err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
- &identifier);
-ERR_I2C:
- if (err != 0) {
+ if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
hw->phy.sfp_type = txgbe_sfp_type_not_present;
- hw->phy.id = 0;
- hw->phy.type = txgbe_phy_unknown;
return TXGBE_ERR_SFP_NOT_PRESENT;
}
- if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
- hw->phy.type = txgbe_phy_sfp_unsupported;
- err = TXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
- }
- hw->phy.id = identifier;
+ err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
+ if (err)
+ return -EBUSY;
- err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP,
- &comp_codes_10g);
+ err = hw->phy.read_i2c_sff8636(hw, 0, TXGBE_SFF_IDENTIFIER,
+ &identifier);
if (err != 0)
- goto ERR_I2C;
+ goto err_read_i2c_eeprom;
- err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP,
- &comp_codes_1g);
-
- if (err != 0)
- goto ERR_I2C;
+ if (identifier != TXGBE_SFF_IDENTIFIER_QSFP &&
+ identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
+ PMD_INIT_LOG(ERR, "port[%d] QSFP module not supported, identifier = 0x%x",
+ hw->bus.lan_id, identifier);
+ hw->phy.type = txgbe_phy_sfp_unsupported;
+ err = TXGBE_ERR_SFP_NOT_SUPPORTED;
+ } else {
+ err = hw->phy.read_i2c_sff8636(hw, 0,
+ TXGBE_ETHERNET_COMP_OFFSET,
+ &transceiver_type);
+ if (err != 0)
+ goto err_read_i2c_eeprom;
- if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
- hw->phy.type = txgbe_phy_qsfp_unknown_passive;
- if (hw->mac.type == txgbe_mac_aml40) {
+ if (transceiver_type & TXGBE_SFF_ETHERNET_40G_CR4) {
if (hw->bus.lan_id == 0)
hw->phy.sfp_type = txgbe_qsfp_type_40g_cu_core0;
else
hw->phy.sfp_type = txgbe_qsfp_type_40g_cu_core1;
- } else {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
- else
- hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
- }
- } else if (comp_codes_10g & TXGBE_SFF_40GBASE_SR4) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type = txgbe_qsfp_type_40g_sr_core0;
- else
- hw->phy.sfp_type = txgbe_qsfp_type_40g_sr_core1;
- } else if (comp_codes_10g & TXGBE_SFF_40GBASE_LR4) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type = txgbe_qsfp_type_40g_lr_core0;
- else
- hw->phy.sfp_type = txgbe_qsfp_type_40g_lr_core1;
- } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
- TXGBE_SFF_10GBASELR_CAPABLE)) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type = txgbe_sfp_type_srlr_core0;
- else
- hw->phy.sfp_type = txgbe_sfp_type_srlr_core1;
- } else {
- if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
- active_cable = true;
-
- if (!active_cable) {
- hw->phy.read_i2c_eeprom(hw,
- TXGBE_SFF_QSFP_CONNECTOR,
- &connector);
-
- hw->phy.read_i2c_eeprom(hw,
- TXGBE_SFF_QSFP_CABLE_LENGTH,
- &cable_length);
-
- hw->phy.read_i2c_eeprom(hw,
- TXGBE_SFF_QSFP_DEVICE_TECH,
- &device_tech);
-
- if (connector ==
- TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE &&
- cable_length > 0 &&
- ((device_tech >> 4) ==
- TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL))
- active_cable = true;
+ hw->phy.fiber_suppport_speed =
+ TXGBE_LINK_SPEED_40GB_FULL |
+ TXGBE_LINK_SPEED_10GB_FULL;
}
- if (active_cable) {
- hw->phy.type = txgbe_phy_qsfp_unknown_active;
+ if (transceiver_type & TXGBE_SFF_ETHERNET_40G_SR4) {
if (hw->bus.lan_id == 0)
- hw->phy.sfp_type =
- txgbe_sfp_type_da_act_lmt_core0;
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_sr_core0;
else
- hw->phy.sfp_type =
- txgbe_sfp_type_da_act_lmt_core1;
- } else {
- /* unsupported module type */
- hw->phy.type = txgbe_phy_sfp_unsupported;
- err = TXGBE_ERR_SFP_NOT_SUPPORTED;
- goto out;
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_sr_core1;
}
- }
-
- if (hw->phy.sfp_type != stored_sfp_type)
- hw->phy.sfp_setup_needed = true;
-
- /* Determine if the QSFP+ PHY is dual speed or not. */
- hw->phy.multispeed_fiber = false;
- if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
- (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
- ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
- (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
- hw->phy.multispeed_fiber = true;
-
- /* Determine PHY vendor for optical modules */
- if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
- TXGBE_SFF_10GBASELR_CAPABLE)) {
- err = hw->phy.read_i2c_eeprom(hw,
- TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
- &oui_bytes[0]);
-
- if (err != 0)
- goto ERR_I2C;
-
- err = hw->phy.read_i2c_eeprom(hw,
- TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
- &oui_bytes[1]);
-
- if (err != 0)
- goto ERR_I2C;
-
- err = hw->phy.read_i2c_eeprom(hw,
- TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
- &oui_bytes[2]);
- if (err != 0)
- goto ERR_I2C;
-
- vendor_oui =
- ((oui_bytes[0] << 24) |
- (oui_bytes[1] << 16) |
- (oui_bytes[2] << 8));
-
- if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL)
- hw->phy.type = txgbe_phy_qsfp_intel;
- else
- hw->phy.type = txgbe_phy_qsfp_unknown;
-
- hw->mac.get_device_caps(hw, &enforce_sfp);
- if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
- /* Make sure we're a supported PHY type */
- if (hw->phy.type == txgbe_phy_qsfp_intel) {
- err = 0;
- } else {
- if (hw->allow_unsupported_sfp) {
- DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. "
- "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
- "Wangxun Corporation is not responsible for any harm caused by using untested modules.");
- err = 0;
- } else {
- DEBUGOUT("QSFP module not supported");
- hw->phy.type =
- txgbe_phy_sfp_unsupported;
- err = TXGBE_ERR_SFP_NOT_SUPPORTED;
- }
- }
- } else {
- err = 0;
+ if (transceiver_type & TXGBE_SFF_ETHERNET_40G_LR4) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_lr_core0;
+ else
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_lr_core1;
}
}
-out:
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
return err;
+
+err_read_i2c_eeprom:
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
+ hw->phy.sfp_type = txgbe_sfp_type_not_present;
+ hw->phy.id = 0;
+ hw->phy.type = txgbe_phy_unknown;
+ return TXGBE_ERR_SFP_NOT_PRESENT;
}
/**
@@ -1278,6 +1201,26 @@ s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset,
sff8472_data);
}
+/**
+ * txgbe_read_i2c_sff8636 - Reads 8 bit word over I2C interface
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset at address 0xA2
+ * @eeprom_data: value read
+ *
+ * Performs byte read operation to SFP module's SFF-8472 data over I2C
+ **/
+s32 txgbe_read_i2c_sff8636(struct txgbe_hw *hw, u8 page, u8 byte_offset,
+ u8 *sff8636_data)
+{
+ hw->phy.write_i2c_byte(hw, TXGBE_SFF_QSFP_PAGE_SELECT,
+ TXGBE_I2C_EEPROM_DEV_ADDR,
+ page);
+
+ return hw->phy.read_i2c_byte(hw, byte_offset,
+ TXGBE_I2C_EEPROM_DEV_ADDR,
+ sff8636_data);
+}
+
/**
* txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure
@@ -1295,7 +1238,7 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
}
/**
- * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C
+ * txgbe_read_i2c_byte - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @dev_addr: address to read from
@@ -1304,7 +1247,7 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified device address.
**/
-s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
+s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
{
txgbe_i2c_start(hw, dev_addr);
@@ -1334,30 +1277,7 @@ s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
}
/**
- * txgbe_read_i2c_byte - Reads 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @dev_addr: address to read from
- * @data: value read
- *
- * Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
- **/
-s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 *data)
-{
- u32 swfw_mask = hw->phy.phy_semaphore_mask;
- int err = 0;
-
- if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
- return TXGBE_ERR_SWFW_SYNC;
- err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
- hw->mac.release_swfw_sync(hw, swfw_mask);
- return err;
-}
-
-/**
- * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
+ * txgbe_write_i2c_byte - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
* @dev_addr: address to write to
@@ -1366,54 +1286,29 @@ s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.
**/
-s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data)
+s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
+ u8 dev_addr, u8 data)
{
txgbe_i2c_start(hw, dev_addr);
/* wait tx empty */
if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
- TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
+ TXGBE_I2CICR_TXEMPTY, NULL, 100, 100))
return -TERR_TIMEOUT;
- }
- wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP);
+ wr32(hw, TXGBE_I2CDATA, byte_offset);
wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE);
/* wait for write complete */
if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
- TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
+ TXGBE_I2CICR_RXFULL, NULL, 100, 100))
return -TERR_TIMEOUT;
- }
+
txgbe_i2c_stop(hw);
return 0;
}
-/**
- * txgbe_write_i2c_byte - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @dev_addr: address to write to
- * @data: value to write
- *
- * Performs byte write operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
- **/
-s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data)
-{
- u32 swfw_mask = hw->phy.phy_semaphore_mask;
- int err = 0;
-
- if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
- return TXGBE_ERR_SWFW_SYNC;
- err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
- hw->mac.release_swfw_sync(hw, swfw_mask);
-
- return err;
-}
-
/**
* txgbe_i2c_start - Sets I2C start condition
* @hw: pointer to hardware structure
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index 3fe7a34409..4da4be0d5f 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -261,7 +261,9 @@
#define TXGBE_SFF_SFF_8472_COMP 0x5E
#define TXGBE_SFF_SFF_8472_OSCB 0x6E
#define TXGBE_SFF_SFF_8472_ESCB 0x76
+#define TXGBE_SFF_QSFP_PAGE_SELECT 0x7F
+#define TXGBE_SFF_IDENTIFIER_QSFP 0x0C
#define TXGBE_SFF_IDENTIFIER_QSFP_PLUS 0x0D
#define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
#define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
@@ -289,6 +291,9 @@
#define TXGBE_SFF_4x10GBASESR_CAP 0x11
#define TXGBE_SFF_40GBASEPSM4_PARALLEL 0x12
#define TXGBE_SFF_40GBASE_SWMD4_CAP 0x1f
+#define TXGBE_SFF_COPPER_5M 0x5
+#define TXGBE_SFF_COPPER_3M 0x3
+#define TXGBE_SFF_COPPER_1M 0x1
#define TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
#define TXGBE_SFF_25GAUI_C2M_AOC_BER_5 0x1
@@ -296,6 +301,11 @@
#define TXGBE_SFF_25GAUI_C2M_AOC_BER_12 0x18
#define TXGBE_SFF_25GAUI_C2M_ACC_BER_12 0x19
+#define TXGBE_ETHERNET_COMP_OFFSET 0x83
+#define TXGBE_SFF_ETHERNET_40G_CR4 MS(3, 0x1)
+#define TXGBE_SFF_ETHERNET_40G_SR4 MS(2, 0x1)
+#define TXGBE_SFF_ETHERNET_40G_LR4 MS(1, 0x1)
+
#define TXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
#define TXGBE_SFF_SOFT_RS_SELECT_10G 0x8
#define TXGBE_SFF_SOFT_RS_SELECT_1G 0x0
@@ -493,14 +503,12 @@ s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw);
s32 txgbe_check_overtemp(struct txgbe_hw *hw);
s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data);
-s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 *data);
s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data);
-s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
- u8 dev_addr, u8 data);
s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset,
- u8 *sff8472_data);
+ u8 *sff8472_data);
+s32 txgbe_read_i2c_sff8636(struct txgbe_hw *hw, u8 page, u8 byte_offset,
+ u8 *sff8636_data);
s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
u8 *eeprom_data);
s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 47629aa9e0..2e2d79e0e1 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -702,6 +702,8 @@ struct txgbe_phy_info {
u8 dev_addr, u8 data);
s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset,
u8 *sff8472_data);
+ s32 (*read_i2c_sff8636)(struct txgbe_hw *hw, u8 page, u8 byte_offset,
+ u8 *sff8636_data);
s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
u8 *eeprom_data);
s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
--
2.21.0.windows.1
^ permalink raw reply related
* [PATCH v4 15/20] net/txgbe: fix FEC mode configuration on 25G NIC
From: Zaiyu Wang @ 2026-05-11 10:35 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
The 25G NIC offers off, RS, Base-R, and auto FEC modes. When
reconfiguring the PHY, the FEC mode must match on both sides;
otherwise, the link cannot come up. The current driver fails to
maintain this requirement, causing link instability.
Add proper FEC mode handling during PHY reconfiguration to
guarantee link establishment.
Fixes: fb6eb170dfa2 ("net/txgbe: add basic link configuration for Amber-Lite")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_aml.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c
index a5b9d951ea..fbb09d144b 100644
--- a/drivers/net/txgbe/base/txgbe_aml.c
+++ b/drivers/net/txgbe/base/txgbe_aml.c
@@ -282,6 +282,14 @@ s32 txgbe_setup_phy_link_aml(struct txgbe_hw *hw,
!(hw->fec_mode & hw->cur_fec_link)))
goto out;
+ if (speed == TXGBE_LINK_SPEED_25GB_FULL &&
+ link_speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ txgbe_e56_fec_polling(hw, &link_up);
+
+ if (link_up)
+ goto out;
+ }
+
rte_spinlock_lock(&hw->phy_lock);
ret_status = txgbe_set_link_to_amlite(hw, speed);
rte_spinlock_unlock(&hw->phy_lock);
@@ -360,7 +368,10 @@ static s32 txgbe_setup_mac_link_multispeed_fiber_aml(struct txgbe_hw *hw,
/* If we already have link at this speed, just jump out */
txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
- if (link_speed == TXGBE_LINK_SPEED_25GB_FULL && link_up)
+ hw->cur_fec_link = txgbe_phy_fec_get(hw);
+
+ if (link_speed == TXGBE_LINK_SPEED_25GB_FULL && link_up &&
+ hw->fec_mode & hw->cur_fec_link)
goto out;
/* Allow module to change analog characteristics (10G -> 25G) */
--
2.21.0.windows.1
^ permalink raw reply related
* [PATCH v4 14/20] net/txgbe: fix link stability for Amber-Lite backplane mode
From: Zaiyu Wang @ 2026-05-11 10:35 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
The link was previously configured via firmware, but this approach
resulted in unstable link behavior. To resolve the issue, re-add the
PHY configuration flow directly into the driver.
Fixes: ead3616f630d ("net/txgbe: support PHY configuration via SW-FW mailbox")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/meson.build | 1 +
drivers/net/txgbe/base/txgbe.h | 2 +
drivers/net/txgbe/base/txgbe_aml.c | 65 +-
drivers/net/txgbe/base/txgbe_aml40.c | 43 +-
drivers/net/txgbe/base/txgbe_e56.c | 22 +-
drivers/net/txgbe/base/txgbe_e56.h | 2 +
drivers/net/txgbe/base/txgbe_e56_bp.c | 2597 +++++++++++++++++++++++++
drivers/net/txgbe/base/txgbe_e56_bp.h | 3 +
drivers/net/txgbe/base/txgbe_hw.c | 6 +
drivers/net/txgbe/base/txgbe_hw.h | 4 +-
drivers/net/txgbe/base/txgbe_osdep.h | 4 +
drivers/net/txgbe/base/txgbe_phy.c | 21 +
drivers/net/txgbe/base/txgbe_phy.h | 22 +
drivers/net/txgbe/base/txgbe_type.h | 25 +-
drivers/net/txgbe/txgbe_ethdev.c | 109 +-
drivers/net/txgbe/txgbe_ethdev.h | 2 +-
16 files changed, 2898 insertions(+), 30 deletions(-)
create mode 100644 drivers/net/txgbe/base/txgbe_e56_bp.c
diff --git a/drivers/net/txgbe/base/meson.build b/drivers/net/txgbe/base/meson.build
index 305c0291e3..a9a02577ce 100644
--- a/drivers/net/txgbe/base/meson.build
+++ b/drivers/net/txgbe/base/meson.build
@@ -13,4 +13,5 @@ base_sources = files(
'txgbe_phy.c',
'txgbe_vf.c',
'txgbe_e56.c',
+ 'txgbe_e56_bp.c',
)
diff --git a/drivers/net/txgbe/base/txgbe.h b/drivers/net/txgbe/base/txgbe.h
index 673a299860..27c3e3be38 100644
--- a/drivers/net/txgbe/base/txgbe.h
+++ b/drivers/net/txgbe/base/txgbe.h
@@ -13,5 +13,7 @@
#include "txgbe_hw.h"
#include "txgbe_vf.h"
#include "txgbe_dcb.h"
+#include "txgbe_e56.h"
+#include "txgbe_e56_bp.h"
#endif /* _TXGBE_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c
index 008b0245e5..a5b9d951ea 100644
--- a/drivers/net/txgbe/base/txgbe_aml.c
+++ b/drivers/net/txgbe/base/txgbe_aml.c
@@ -13,6 +13,7 @@
#include "txgbe_hw.h"
#include "txgbe_aml.h"
#include "txgbe_e56.h"
+#include "txgbe_e56_bp.h"
void txgbe_init_ops_aml(struct txgbe_hw *hw)
{
@@ -84,6 +85,13 @@ s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw, u32 *speed,
*speed = TXGBE_LINK_SPEED_UNKNOWN;
}
+ if (txgbe_xpcs_an_enabled(hw)) {
+ if (!hw->an_done) {
+ *link_up = false;
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+ }
+ }
+
return 0;
}
@@ -95,23 +103,41 @@ s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw,
*speed = TXGBE_LINK_SPEED_10GB_FULL |
TXGBE_LINK_SPEED_25GB_FULL;
*autoneg = true;
+ } else if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
+ if (hw->phy.fiber_suppport_speed ==
+ TXGBE_LINK_SPEED_10GB_FULL) {
+ hw->devarg.auto_neg = false;
+ *autoneg = false;
+ } else {
+ *autoneg = true;
+ }
+ *speed = hw->phy.fiber_suppport_speed;
} else if (hw->phy.sfp_type == txgbe_sfp_type_25g_sr_core0 ||
hw->phy.sfp_type == txgbe_sfp_type_25g_sr_core1 ||
hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core0 ||
- hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core1) {
+ hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core1 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_aoc_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_aoc_core1) {
*speed = TXGBE_LINK_SPEED_25GB_FULL;
*autoneg = false;
- } else if (hw->phy.sfp_type == txgbe_sfp_type_25g_aoc_core0 ||
- hw->phy.sfp_type == txgbe_sfp_type_25g_aoc_core1) {
- *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ } else if (hw->phy.media_type == txgbe_media_type_backplane) {
+ /* Backplane */
+ *speed = TXGBE_LINK_SPEED_10GB_FULL |
+ TXGBE_LINK_SPEED_25GB_FULL;
+ /* Backplane supports autonegotiation */
+ *autoneg = hw->devarg.auto_neg;
+ } else if (hw->phy.media_type == txgbe_media_type_fiber) {
+ /* Fiber */
+ *speed = TXGBE_LINK_SPEED_10GB_FULL |
+ TXGBE_LINK_SPEED_25GB_FULL;
*autoneg = false;
} else {
- /* SFP */
- if (hw->phy.sfp_type == txgbe_sfp_type_not_present)
- *speed = TXGBE_LINK_SPEED_25GB_FULL;
- else
- *speed = TXGBE_LINK_SPEED_10GB_FULL;
- *autoneg = true;
+ /* Unknown */
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+ *autoneg = false;
+ PMD_DRV_LOG(DEBUG, "GET link capabilities failed");
+ return TXGBE_ERR_LINK_SETUP;
}
return 0;
@@ -193,7 +219,7 @@ s32 txgbe_setup_phy_link_aml(struct txgbe_hw *hw,
*need_reset = false;
- if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
+ if (hw->phy.sfp_type == txgbe_sfp_type_not_present && !txgbe_is_backplane(hw)) {
DEBUGOUT("SFP not detected, skip setup mac link");
return 0;
}
@@ -216,6 +242,23 @@ s32 txgbe_setup_phy_link_aml(struct txgbe_hw *hw,
if (speed == TXGBE_LINK_SPEED_UNKNOWN)
return TXGBE_ERR_LINK_SETUP;
+ if (txgbe_xpcs_an_enabled(hw)) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up && hw->an_done && !autoneg_wait_to_complete)
+ return status;
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_set_phy_link_mode(hw, speed, autoneg_wait_to_complete);
+ rte_spinlock_unlock(&hw->phy_lock);
+ return 0;
+ }
+
+ if (txgbe_is_backplane(hw) || txgbe_is_dac_cable(hw) ||
+ hw->phy.ffe_set) {
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_tx_ffe_cfg(hw, speed);
+ rte_spinlock_unlock(&hw->phy_lock);
+ }
+
if (txgbe_gpio_ext_check(hw, TXGBE_SFP1_MOD_ABS_LS |
TXGBE_SFP1_RX_LOS_LS)) {
DEBUGOUT("RX LOS");
diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c
index 84c130704a..d350f18c4b 100644
--- a/drivers/net/txgbe/base/txgbe_aml40.c
+++ b/drivers/net/txgbe/base/txgbe_aml40.c
@@ -14,6 +14,7 @@
#include "txgbe_aml.h"
#include "txgbe_aml40.h"
#include "txgbe_e56.h"
+#include "txgbe_e56_bp.h"
void txgbe_init_ops_aml40(struct txgbe_hw *hw)
{
@@ -98,7 +99,10 @@ s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw,
if (hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core0 ||
hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core1) {
*speed = TXGBE_LINK_SPEED_40GB_FULL;
- *autoneg = false;
+ *autoneg = true;
+ } else if (txgbe_is_backplane(hw)) {
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ *autoneg = true;
} else {
/*
* Temporary workaround: set speed to 40G even if sfp not present
@@ -115,8 +119,22 @@ s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw,
u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw)
{
- UNREFERENCED_PARAMETER(hw);
- return txgbe_media_type_fiber_qsfp;
+ u8 device_type = hw->subsystem_device_id & 0xF0;
+ enum txgbe_media_type media_type;
+
+ switch (device_type) {
+ case TXGBE_DEV_ID_KR_KX_KX4:
+ media_type = txgbe_media_type_backplane;
+ break;
+ case TXGBE_DEV_ID_SFP:
+ media_type = txgbe_media_type_fiber_qsfp;
+ break;
+ default:
+ media_type = txgbe_media_type_unknown;
+ break;
+ }
+
+ return media_type;
}
s32 txgbe_setup_phy_link_aml40(struct txgbe_hw *hw,
@@ -135,7 +153,7 @@ s32 txgbe_setup_phy_link_aml40(struct txgbe_hw *hw,
*need_reset = false;
- if (hw->phy.sfp_type == txgbe_sfp_type_not_present)
+ if (hw->phy.sfp_type == txgbe_sfp_type_not_present && !txgbe_is_backplane(hw))
hw->phy.identify_sfp(hw);
/* Check to see if speed passed in is supported. */
@@ -148,6 +166,23 @@ s32 txgbe_setup_phy_link_aml40(struct txgbe_hw *hw,
if (speed == TXGBE_LINK_SPEED_UNKNOWN)
return TXGBE_ERR_LINK_SETUP;
+ if (txgbe_xpcs_an_enabled(hw)) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up && hw->an_done && !autoneg_wait_to_complete)
+ return status;
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_set_phy_link_mode(hw, 40, autoneg_wait_to_complete);
+ rte_spinlock_unlock(&hw->phy_lock);
+ return status;
+ }
+
+ if (txgbe_is_backplane(hw) || txgbe_is_dac_cable(hw) ||
+ hw->phy.ffe_set) {
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_tx_ffe_cfg(hw, speed);
+ rte_spinlock_unlock(&hw->phy_lock);
+ }
+
for (i = 0; i < 4; i++) {
txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
if (link_up)
diff --git a/drivers/net/txgbe/base/txgbe_e56.c b/drivers/net/txgbe/base/txgbe_e56.c
index c6fb2627d4..79f3a81348 100644
--- a/drivers/net/txgbe/base/txgbe_e56.c
+++ b/drivers/net/txgbe/base/txgbe_e56.c
@@ -53,7 +53,7 @@ int txgbe_e56_int_cmp(const void *a, const void *b)
}
s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed,
- bool *link_up)
+ bool *link_up)
{
u32 rdata = 0;
u32 links_reg = 0;
@@ -101,7 +101,8 @@ u32 txgbe_e56_tx_ffe_cfg(struct txgbe_hw *hw, u32 speed)
post = S10G_TX_FFE_CFG_POST;
} else if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
- hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
+ hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1 ||
+ txgbe_is_backplane(hw)) {
ffe_main = S25G_TX_FFE_CFG_DAC_MAIN;
pre1 = S25G_TX_FFE_CFG_DAC_PRE1;
pre2 = S25G_TX_FFE_CFG_DAC_PRE2;
@@ -119,7 +120,8 @@ u32 txgbe_e56_tx_ffe_cfg(struct txgbe_hw *hw, u32 speed)
post = S10G_TX_FFE_CFG_POST;
if (hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core0 ||
- hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core1) {
+ hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core1 ||
+ txgbe_is_backplane(hw)) {
ffe_main = S40G_TX_FFE_CFG_MAIN;
pre1 = S40G_TX_FFE_CFG_PRE1;
pre2 = S40G_TX_FFE_CFG_PRE2;
@@ -1508,7 +1510,7 @@ txgbe_e56_rxs_osc_init_for_temp_track_range(struct txgbe_hw *hw, u32 speed)
rdata = rd32_ephy(hw, addr);
if (timer++ > PHYINIT_TIMEOUT) {
- DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!\n");
+ DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!");
break;
return -1;
}
@@ -1543,7 +1545,7 @@ txgbe_e56_rxs_osc_init_for_temp_track_range(struct txgbe_hw *hw, u32 speed)
if (((rdata >> (i * 8)) & 0x3f) == 0x21)
break;
if (timer++ > PHYINIT_TIMEOUT) {
- DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!\n");
+ DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!");
break;
return -1;
}
@@ -1620,7 +1622,7 @@ txgbe_e56_rxs_osc_init_for_temp_track_range(struct txgbe_hw *hw, u32 speed)
addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
rdata = rd32_ephy(hw, addr);
if (timer++ > PHYINIT_TIMEOUT) {
- DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!\n");
+ DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!");
break;
return -1;
}
@@ -1667,7 +1669,7 @@ txgbe_e56_rxs_osc_init_for_temp_track_range(struct txgbe_hw *hw, u32 speed)
if (((rdata >> (i * 8)) & 0x3f) == 0x21)
break;
if (timer++ > PHYINIT_TIMEOUT) {
- DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!\n");
+ DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!");
break;
return -1;
}
@@ -1936,7 +1938,7 @@ int txgbe_temp_track_seq_40g(struct txgbe_hw *hw, u32 speed)
CMVAR_UFINE_FMIN_WRAP = S25G_CMVAR_UFINE_FMIN_WRAP;
CMVAR_FINE_FMIN_WRAP = S25G_CMVAR_FINE_FMIN_WRAP;
} else {
- DEBUGOUT("Error Speed\n");
+ DEBUGOUT("Error Speed");
return 0;
}
@@ -3195,7 +3197,7 @@ static int txgbe_e56_disable_rx40G(struct txgbe_hw *hw)
rdata = rd32_ephy(hw, addr);
usec_delay(100);
if (timer++ > PHYINIT_TIMEOUT) {
- DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!\n");
+ DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!");
break;
}
}
@@ -3301,7 +3303,7 @@ static int txgbe_e56_disable_rx(struct txgbe_hw *hw)
break;
usec_delay(100);
if (timer++ > PHYINIT_TIMEOUT) {
- DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!\n");
+ DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!");
break;
}
}
diff --git a/drivers/net/txgbe/base/txgbe_e56.h b/drivers/net/txgbe/base/txgbe_e56.h
index 7509526263..974af675ed 100644
--- a/drivers/net/txgbe/base/txgbe_e56.h
+++ b/drivers/net/txgbe/base/txgbe_e56.h
@@ -1739,6 +1739,8 @@ int txgbe_temp_track_seq(struct txgbe_hw *hw, u32 speed);
int txgbe_e56_get_temp(struct txgbe_hw *hw, int *temp);
int txgbe_set_link_to_amlite(struct txgbe_hw *hw, u32 speed);
int txgbe_e56_reconfig_rx(struct txgbe_hw *hw, u32 speed);
+s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up);
s32 txgbe_e56_fec_set(struct txgbe_hw *hw);
s32 txgbe_e56_fec_polling(struct txgbe_hw *hw, bool *link_up);
u32 txgbe_e56_tx_ffe_cfg(struct txgbe_hw *hw, u32 speed);
diff --git a/drivers/net/txgbe/base/txgbe_e56_bp.c b/drivers/net/txgbe/base/txgbe_e56_bp.c
new file mode 100644
index 0000000000..0cb2bc0fd6
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_e56_bp.c
@@ -0,0 +1,2597 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024-2026 Beijing WangXun Technology Co., Ltd.
+ */
+
+#include "txgbe_e56.h"
+#include "txgbe_hw.h"
+#include "txgbe_osdep.h"
+#include "txgbe_phy.h"
+#include "txgbe_e56_bp.h"
+#include "txgbe.h"
+#include "../txgbe_logs.h"
+
+static int
+txgbe_e56_set_rxs_ufine_le_max(struct txgbe_hw *hw, u32 speed)
+{
+ u32 rdata, addr;
+ u32 ULTRAFINE_CODE[4] = {0};
+ int lane_num = 0, lane_idx = 0;
+ u32 CMVAR_UFINE_MAX = 0;
+
+ switch (speed) {
+ case 10:
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ lane_num = 1;
+ break;
+ case 40:
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ lane_num = 4;
+ break;
+ case 25:
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+ lane_num = 1;
+ break;
+ default:
+ BP_LOG("%s %d :Invalid speed\n", __func__, __LINE__);
+ break;
+ }
+
+ for (lane_idx = 0; lane_idx < lane_num; lane_idx++) {
+ /* ii get rx ana_bbcdr_ultrafine_i[14, 12] per lane */
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ ULTRAFINE_CODE[lane_idx] = FIELD_GET_M(GENMASK(14, 12), rdata);
+ BP_LOG("ULTRAFINE_CODE[%d] = %d, CMVAR_UFINE_MAX: %x\n",
+ lane_idx, ULTRAFINE_CODE[lane_idx], CMVAR_UFINE_MAX);
+ }
+
+ for (lane_idx = 0; lane_idx < lane_num; lane_idx++) {
+ /* b. Perform the below logic sequence */
+ while (ULTRAFINE_CODE[lane_idx] > CMVAR_UFINE_MAX) {
+ ULTRAFINE_CODE[lane_idx] -= 1;
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR +
+ (E56PHY_RXS_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 14, 12, ULTRAFINE_CODE[lane_idx]);
+ wr32_ephy(hw, addr, rdata);
+
+ /* ovrd_en_ana_bbcdr_ultrafine=1 override ASIC value */
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR +
+ (E56PHY_RXS_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ wr32_ephy(hw, addr, rdata | BIT(3));
+
+ /* Wait until 1milliseconds or greater */
+ usec_delay(1000);
+ }
+ }
+ return 0;
+}
+
+static int txgbe_e56_rxs_osc_init_for_temp_track_range(struct txgbe_hw *hw,
+ u32 speed)
+{
+ int OFFSET_CENTRE_RANGE_H[4] = {0}, OFFSET_CENTRE_RANGE_L[4] = {}, RANGE_FINAL[4] = {};
+ int RX_COARSE_MID_TD, CMVAR_RANGE_H = 0, CMVAR_RANGE_L = 0;
+ int status = 0, lane_num = 0;
+ int T = 40, lane_id = 0;
+ u32 addr, rdata;
+
+ /* Set CMVAR_RANGE_H/L based on the link speed mode */
+ switch (speed) {
+ case 10:
+ CMVAR_RANGE_H = S10G_CMVAR_RANGE_H;
+ CMVAR_RANGE_L = S10G_CMVAR_RANGE_L;
+ lane_num = 1;
+ break;
+ case 40:
+ CMVAR_RANGE_H = S10G_CMVAR_RANGE_H;
+ CMVAR_RANGE_L = S10G_CMVAR_RANGE_L;
+ lane_num = 4;
+ break;
+ case 25:
+ CMVAR_RANGE_H = S25G_CMVAR_RANGE_H;
+ CMVAR_RANGE_L = S25G_CMVAR_RANGE_L;
+ lane_num = 1;
+ break;
+ default:
+ BP_LOG("%s %d :Invalid speed\n", __func__, __LINE__);
+ break;
+ }
+
+ /* 1. Read the temperature T just before RXS is enabled. */
+ txgbe_e56_get_temp(hw, &T);
+
+ /* 2. Define software variable RX_COARSE_MID_TD */
+ if (T < -5)
+ RX_COARSE_MID_TD = 10;
+ else if (T < 30)
+ RX_COARSE_MID_TD = 9;
+ else if (T < 65)
+ RX_COARSE_MID_TD = 8;
+ else if (T < 100)
+ RX_COARSE_MID_TD = 7;
+ else
+ RX_COARSE_MID_TD = 6;
+
+ for (lane_id = 0; lane_id < lane_num; lane_id++) {
+ addr = 0x0b4 + (0x200 * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 0, CMVAR_RANGE_H);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x08c + (0x200 * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 29, 29, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1540 + (0x02c * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 22, 22, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1530 + (0x02c * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 27, 27, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ }
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 19, 16, GENMASK(lane_num - 1, 0));
+ wr32_ephy(hw, 0x1400, rdata);
+ status |= kr_read_poll(rd32_ephy, rdata,
+ (((rdata & 0x3f3f3f3f) & GENMASK(8 * lane_num - 1, 0))
+ == (0x09090909 & GENMASK(8 * lane_num - 1, 0))),
+ 100, 2000, hw,
+ E56PHY_CTRL_FSM_RX_STAT_0_ADDR);
+ if (status)
+ BP_LOG("Wait fsm_rx_sts 1 = %x : %d, Wait rx_sts %s.\n",
+ rdata, status, status ? "FAILED" : "SUCCESS");
+
+ for (lane_id = 0; lane_id < lane_num; lane_id++) {
+ addr = 0x0b4 + (0x0200 * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ OFFSET_CENTRE_RANGE_H[lane_id] = (rdata >> 4) & 0xf;
+ if (OFFSET_CENTRE_RANGE_H[lane_id] > RX_COARSE_MID_TD)
+ OFFSET_CENTRE_RANGE_H[lane_id] = OFFSET_CENTRE_RANGE_H[lane_id] -
+ RX_COARSE_MID_TD;
+ else
+ OFFSET_CENTRE_RANGE_H[lane_id] = RX_COARSE_MID_TD -
+ OFFSET_CENTRE_RANGE_H[lane_id];
+ }
+
+ /* 7. Do SEQ::RX_DISABLE to disable RXS. */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 19, 16, 0x0);
+ wr32_ephy(hw, 0x1400, rdata);
+ status |= kr_read_poll(rd32_ephy, rdata,
+ (((rdata & 0x3f3f3f3f) & GENMASK(8 * lane_num - 1, 0))
+ == (0x21212121 & GENMASK(8 * lane_num - 1, 0))),
+ 100, 2000, hw,
+ E56PHY_CTRL_FSM_RX_STAT_0_ADDR);
+ if (status)
+ BP_LOG("Wait fsm_rx_sts 2 = %x : %d, Wait rx_sts %s.\n",
+ rdata, status, status ? "FAILED" : "SUCCESS");
+ rdata = rd32_ephy(hw, 0x15ec);
+ wr32_ephy(hw, 0x15ec, rdata);
+
+ for (lane_id = 0; lane_id < lane_num; lane_id++) {
+ addr = 0x0b4 + (0x200 * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 0, CMVAR_RANGE_L);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x08c + (0x200 * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 29, 29, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1540 + (0x02c * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 22, 22, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1530 + (0x02c * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 27, 27, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ }
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 19, 16, 0xf);
+ wr32_ephy(hw, 0x1400, rdata);
+ status |= kr_read_poll(rd32_ephy, rdata,
+ (((rdata & 0x3f3f3f3f) & GENMASK(8 * lane_num - 1, 0))
+ == (0x09090909 & GENMASK(8 * lane_num - 1, 0))),
+ 100, 2000, hw,
+ E56PHY_CTRL_FSM_RX_STAT_0_ADDR);
+ if (status)
+ BP_LOG("Wait fsm_rx_sts 3 = %x : %d, Wait rx_sts %s.\n",
+ rdata, status, status ? "FAILED" : "SUCCESS");
+ for (lane_id = 0; lane_id < lane_num; lane_id++) {
+ addr = 0x0b4 + (0x0200 * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ OFFSET_CENTRE_RANGE_L[lane_id] = (rdata >> 4) & 0xf;
+ if (OFFSET_CENTRE_RANGE_L[lane_id] > RX_COARSE_MID_TD)
+ OFFSET_CENTRE_RANGE_L[lane_id] = OFFSET_CENTRE_RANGE_L[lane_id] -
+ RX_COARSE_MID_TD;
+ else
+ OFFSET_CENTRE_RANGE_L[lane_id] = RX_COARSE_MID_TD -
+ OFFSET_CENTRE_RANGE_L[lane_id];
+ }
+ for (lane_id = 0; lane_id < lane_num; lane_id++) {
+ RANGE_FINAL[lane_id] = OFFSET_CENTRE_RANGE_L[lane_id] <
+ OFFSET_CENTRE_RANGE_H[lane_id] ?
+ CMVAR_RANGE_L : CMVAR_RANGE_H;
+ BP_LOG("lane_id:%d-RANGE_L:%x-RANGE_H:%x-RANGE_FINAL:%x\n",
+ lane_id, OFFSET_CENTRE_RANGE_L[lane_id],
+ OFFSET_CENTRE_RANGE_H[lane_id], RANGE_FINAL[lane_id]);
+ }
+
+ /* 7. Do SEQ::RX_DISABLE to disable RXS. */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 19, 16, 0x0);
+ wr32_ephy(hw, 0x1400, rdata);
+ status |= kr_read_poll(rd32_ephy, rdata,
+ (((rdata & 0x3f3f3f3f) & GENMASK(8 * lane_num - 1, 0))
+ == (0x21212121 & GENMASK(8 * lane_num - 1, 0))),
+ 100, 2000, hw,
+ E56PHY_CTRL_FSM_RX_STAT_0_ADDR);
+ if (status)
+ BP_LOG("Wait fsm_rx_sts 4 = %x : %d, Wait rx_sts %s.\n",
+ rdata, status, status ? "FAILED" : "SUCCESS");
+ rdata = rd32_ephy(hw, 0x15ec);
+ wr32_ephy(hw, 0x15ec, rdata);
+
+ for (lane_id = 0; lane_id < lane_num; lane_id++) {
+ addr = 0x0b4 + (0x0200 * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 0, RANGE_FINAL[lane_id]);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0x1544 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 25, 25, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1538 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 0, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 28, 28, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1538 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 3, 3, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0x1544 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 16, 16, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1534 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 23, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 17, 17, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1534 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 24, 24, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 31, 31, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1538 + (lane_id * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 6, 6, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1530 + (0x02c * lane_id);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 27, 27, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ /* Do SEQ::RX_ENABLE */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, GENMASK(lane_num - 1, 0));
+ wr32_ephy(hw, 0x1400, rdata);
+
+ return status;
+}
+
+static int txgbe_e56_rxs_post_cdr_lock_temp_track_seq(struct txgbe_hw *hw,
+ u32 speed)
+{
+ int status = 0;
+ u32 rdata;
+ int SECOND_CODE;
+ int COARSE_CODE;
+ int FINE_CODE;
+ int ULTRAFINE_CODE;
+
+ int CMVAR_SEC_LOW_TH = 0;
+ int CMVAR_UFINE_MAX = 0;
+ int CMVAR_FINE_MAX = 0;
+ int CMVAR_UFINE_UMAX_WRAP = 0;
+ int CMVAR_COARSE_MAX = 0;
+ int CMVAR_UFINE_FMAX_WRAP = 0;
+ int CMVAR_FINE_FMAX_WRAP = 0;
+ int CMVAR_SEC_HIGH_TH = 0;
+ int CMVAR_UFINE_MIN = 0;
+ int CMVAR_FINE_MIN = 0;
+ int CMVAR_UFINE_UMIN_WRAP = 0;
+ int CMVAR_COARSE_MIN = 0;
+ int CMVAR_UFINE_FMIN_WRAP = 0;
+ int CMVAR_FINE_FMIN_WRAP = 0;
+
+ if (speed == 10) {
+ CMVAR_SEC_LOW_TH = S10G_CMVAR_SEC_LOW_TH;
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ CMVAR_FINE_MAX = S10G_CMVAR_FINE_MAX;
+ CMVAR_UFINE_UMAX_WRAP = S10G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S10G_CMVAR_COARSE_MAX;
+ CMVAR_UFINE_FMAX_WRAP = S10G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S10G_CMVAR_FINE_FMAX_WRAP;
+ CMVAR_SEC_HIGH_TH = S10G_CMVAR_SEC_HIGH_TH;
+ CMVAR_UFINE_MIN = S10G_CMVAR_UFINE_MIN;
+ CMVAR_FINE_MIN = S10G_CMVAR_FINE_MIN;
+ CMVAR_UFINE_UMIN_WRAP = S10G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S10G_CMVAR_COARSE_MIN;
+ CMVAR_UFINE_FMIN_WRAP = S10G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S10G_CMVAR_FINE_FMIN_WRAP;
+ } else if (speed == 25) {
+ CMVAR_SEC_LOW_TH = S25G_CMVAR_SEC_LOW_TH;
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+ CMVAR_FINE_MAX = S25G_CMVAR_FINE_MAX;
+ CMVAR_UFINE_UMAX_WRAP = S25G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S25G_CMVAR_COARSE_MAX;
+ CMVAR_UFINE_FMAX_WRAP = S25G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S25G_CMVAR_FINE_FMAX_WRAP;
+ CMVAR_SEC_HIGH_TH = S25G_CMVAR_SEC_HIGH_TH;
+ CMVAR_UFINE_MIN = S25G_CMVAR_UFINE_MIN;
+ CMVAR_FINE_MIN = S25G_CMVAR_FINE_MIN;
+ CMVAR_UFINE_UMIN_WRAP = S25G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S25G_CMVAR_COARSE_MIN;
+ CMVAR_UFINE_FMIN_WRAP = S25G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S25G_CMVAR_FINE_FMIN_WRAP;
+ }
+
+ status |= txgbe_e56_rx_rd_second_code(hw, &SECOND_CODE);
+
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ COARSE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i);
+ FINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ if (SECOND_CODE <= CMVAR_SEC_LOW_TH) {
+ if (ULTRAFINE_CODE < CMVAR_UFINE_MAX) {
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i,
+ ULTRAFINE_CODE + 1);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (FINE_CODE < CMVAR_FINE_MAX) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = FINE_CODE + 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (COARSE_CODE < CMVAR_COARSE_MAX) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_fine_i) = CMVAR_FINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i) = COARSE_CODE + 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else {
+ BP_LOG("ERROR: (SECOND_CODE <= CMVAR_SEC_LOW_TH) temperature tracking occurs Error condition\n");
+ }
+ } else if (SECOND_CODE >= CMVAR_SEC_HIGH_TH) {
+ if (ULTRAFINE_CODE > CMVAR_UFINE_MIN) {
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i,
+ ULTRAFINE_CODE - 1);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (FINE_CODE > CMVAR_FINE_MIN) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = FINE_CODE - 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (COARSE_CODE > CMVAR_COARSE_MIN) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_fine_i) = CMVAR_FINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i) = COARSE_CODE - 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else {
+ BP_LOG("ERROR: (SECOND_CODE >= CMVAR_SEC_HIGH_TH) temperature tracking occurs Error condition\n");
+ }
+ }
+
+ return status;
+}
+
+static int txgbe_e56_ctle_bypass_seq(struct txgbe_hw *hw, u8 bp_link_mode)
+{
+ u32 rdata;
+
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDVAL_1);
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDEN_1);
+
+ if (bp_link_mode == 40) {
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+
+ EPHY_RREG(E56G__PMD_RXS1_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS1_OVRDVAL_1);
+ EPHY_RREG(E56G__PMD_RXS2_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS2_OVRDVAL_1);
+ EPHY_RREG(E56G__PMD_RXS3_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS3_OVRDVAL_1);
+
+ EPHY_RREG(E56G__PMD_RXS1_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDEN_1, ovrd_en_rxs1_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDEN_1, ovrd_en_rxs1_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS1_OVRDEN_1);
+ EPHY_RREG(E56G__PMD_RXS2_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDEN_1, ovrd_en_rxs2_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDEN_1, ovrd_en_rxs2_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS2_OVRDEN_1);
+ EPHY_RREG(E56G__PMD_RXS3_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDEN_1, ovrd_en_rxs3_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDEN_1, ovrd_en_rxs3_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS3_OVRDEN_1);
+ }
+ return 0;
+}
+
+static int txgbe_e56_rxs_adc_adapt_seq(struct txgbe_hw *hw, u32 bypass_ctle)
+{
+ int lane_num = 0, lane_idx = 0;
+ u32 rdata = 0, addr = 0;
+ int status = 0;
+
+ int timer = 0, j = 0;
+
+ switch (hw->bp_link_mode) {
+ case 10:
+ lane_num = 1;
+ break;
+ case 40:
+ lane_num = 4;
+ break;
+ case 25:
+ lane_num = 1;
+ break;
+ default:
+ BP_LOG("%s %d :Invalid speed\n", __func__, __LINE__);
+ break;
+ }
+
+ for (lane_idx = 0; lane_idx < lane_num; lane_idx++) {
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ /* Wait RXS0-3_OVRDVAL[1]::rxs0-3_rx0_cdr_rdy_o = 1 */
+ status = kr_read_poll(rd32_ephy, rdata, (rdata & BIT(12)),
+ 100, 2000, hw, 0x1544);
+ if (status)
+ BP_LOG("rxs%d_rx0_cdr_rdy_o = %x, %s.\n",
+ lane_idx, rdata,
+ status ? "FAILED" : "SUCCESS");
+ }
+
+ for (lane_idx = 0; lane_idx < lane_num; lane_idx++) {
+ /* 4. Disable VGA and CTLE training so they don't interfere with ADC calibration */
+ /* a. Set ALIAS::RXS::VGA_TRAIN_EN = 0b0 */
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 7, 7, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1534 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 14, 14, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* b. Set ALIAS::RXS::CTLE_TRAIN_EN = 0b0 */
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 9, 9, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1534 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 16, 16, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* 5. Perform ADC interleaver calibration */
+ /* a. Remove the OVERRIDE on ALIAS::RXS::ADC_INTL_CAL_DONE */
+ addr = 0x1534 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 24, 24, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 16, 16, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ /* Wait rxs0_rx0_adc_intl_cal_done_o bit17 = 1 */
+ status = kr_read_poll(rd32_ephy, rdata, (rdata & BIT(17)),
+ 100, 2000, hw, addr);
+ if (status)
+ BP_LOG("rxs0_rx0_adc_intl_cal_done_o = %x, %s.\n", rdata,
+ status ? "FAILED" : "SUCCESS");
+
+ /* 6. Perform ADC offset adaptation and ADC gain adaptation,
+ * repeat them a few times and after that keep it disabled.
+ */
+ for (j = 0; j < 16; j++) {
+ /* a. ALIAS::RXS::ADC_OFST_ADAPT_EN = 0b1 */
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 25, 25, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* b. Wait for 1ms or greater */
+ /* usec_delay(1000); */
+ /* set ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o bit1=0 */
+ addr = 0x1538 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 1, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ /* Wait rxs0_rx0_adc_ofst_adapt_done_o bit26 = 0 */
+ status = kr_read_poll(rd32_ephy, rdata,
+ !(rdata & BIT(26)),
+ 100, 2000, hw, addr);
+ if (status)
+ BP_LOG("rxs0_rx0_adc_ofst_adapt_done_o %d = %x, %s.\n",
+ j, rdata, status ? "FAILED" : "SUCCESS");
+
+ /* c. ALIAS::RXS::ADC_OFST_ADAPT_EN = 0b0 */
+ rdata = 0x0000;
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 25, 25, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ /* d. ALIAS::RXS::ADC_GAIN_ADAPT_EN = 0b1 */
+ rdata = 0x0000;
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 28, 28, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* e. Wait for 1ms or greater */
+ /* usec_delay(1000); */
+ /* set ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o bit1=0 */
+ addr = 0x1538 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 1, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ /* Wait rxs0_rx0_adc_gain_adapt_done_o bit29 = 0 */
+ status = kr_read_poll(rd32_ephy, rdata, !(rdata & BIT(29)),
+ 100, 2000, hw, addr);
+ if (status)
+ BP_LOG("rxs0_rx0_adc_gain_adapt_done_o %d = %x, %s.\n",
+ j, rdata, status ? "FAILED" : "SUCCESS");
+
+ /* f. ALIAS::RXS::ADC_GAIN_ADAPT_EN = 0b0 */
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 28, 28, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ }
+ /* g. Repeat #a to #f total 16 times */
+
+ /* 7. Perform ADC interleaver adaptation for 10ms or greater,
+ * and after that disable it
+ */
+ /* a. ALIAS::RXS::ADC_INTL_ADAPT_EN = 0b1 */
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 31, 31, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ /* b. Wait for 10ms or greater */
+ msleep(20);
+
+ /* c. ALIAS::RXS::ADC_INTL_ADAPT_EN = 0b0 */
+ /* set ovrd_en_rxs0_rx0_adc_intl_adapt_en_i=0 */
+ addr = 0x1538 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 6, 6, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ /* 8. Now re-enable VGA and CTLE trainings, so that it continues
+ * to adapt tracking changes in temperature or voltage
+ * <1>Set ALIAS::RXS::VGA_TRAIN_EN = 0b1
+ */
+ /* set rxs0_rx0_vga_train_en_i=1 */
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 7, 7, 0x1);
+ if (bypass_ctle == 0)
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+
+ /* <2>wait for ALIAS::RXS::VGA_TRAIN_DONE = 1 */
+ /* set ovrd_en_rxs0_rx0_vga_train_done_o = 0 */
+ addr = 0x1534 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 15, 15, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ /* Wait rxs0_rx0_vga_train_done_o bit8 = 0 */
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ status = kr_read_poll(rd32_ephy, rdata, (rdata & BIT(8)),
+ 100, 3000, hw, addr);
+ if (status)
+ BP_LOG("rxs0_rx0_vga_train_done_o = %x, %s.\n", rdata,
+ status ? "FAILED" : "SUCCESS");
+
+ if (bypass_ctle == 0) {
+ addr = 0x1534 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1,
+ ovrd_en_rxs0_rx0_ctle_train_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ timer = 0;
+ addr = 0x1544 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1,
+ rxs0_rx0_ctle_train_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+ }
+
+ /* a. Remove the OVERRIDE on ALIAS::RXS::VGA_TRAIN_EN */
+ addr = 0x1534 + (E56PHY_PMD_RX_OFFSET * lane_idx);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 15, 15, 0);
+ /* b. Remove the OVERRIDE on ALIAS::RXS::CTLE_TRAIN_EN */
+ if (bypass_ctle == 0)
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1,
+ ovrd_en_rxs0_rx0_ctle_train_en_i) = 0;
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ return status;
+}
+
+static int txgbe_e56_phy_rxs_calib_adapt_seq(struct txgbe_hw *hw,
+ u8 bp_link_mode, u32 bypass_ctle)
+{
+ int lane_num = 0, lane_idx = 0;
+ int status = 0;
+ u32 rdata, addr;
+
+ switch (bp_link_mode) {
+ case 10:
+ lane_num = 1;
+ break;
+ case 40:
+ lane_num = 4;
+ break;
+ case 25:
+ lane_num = 1;
+ break;
+ default:
+ BP_LOG("%s %d :Invalid speed\n", __func__, __LINE__);
+ break;
+ }
+
+ for (lane_idx = 0; lane_idx < lane_num; lane_idx++) {
+ rdata = 0x0000;
+ addr = 0x1544 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 25, 25, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1538 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 0, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 28, 28, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1538 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 3, 3, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0x1544 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 16, 16, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1534 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 23, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 17, 17, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1534 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 24, 24, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1544 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 31, 31, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x1538 + (lane_idx * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 6, 6, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ }
+ if (bypass_ctle != 0)
+ status |= txgbe_e56_ctle_bypass_seq(hw, bp_link_mode);
+
+ status |= txgbe_e56_rxs_osc_init_for_temp_track_range(hw, bp_link_mode);
+
+ /* Wait an fsm_rx_sts 25G */
+ BP_LOG("Wait CTRL_FSM_RX_STAT[0]::ctrl_fsm_rx0_st to be ready ...\n");
+
+ status |= kr_read_poll(rd32_ephy, rdata,
+ (((rdata & 0x3f3f3f3f) & GENMASK(8 * lane_num - 1, 0))
+ == (0x1b1b1b1b & GENMASK(8 * lane_num - 1, 0))),
+ 1000, 300, hw,
+ E56PHY_CTRL_FSM_RX_STAT_0_ADDR);
+ BP_LOG("wait ctrl_fsm_rx0_st = %x, %s.\n",
+ rdata, status ? "FAILED" : "SUCCESS");
+
+ return status;
+}
+
+static int txgbe_e56_cms_cfg_for_temp_track_range(struct txgbe_hw *hw)
+{
+ int status = 0, T = 40;
+ u32 addr, rdata;
+
+ status = txgbe_e56_get_temp(hw, &T);
+ if (T < 40) {
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDVAL_7_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ } else if (T > 70) {
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I, 0x3);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDVAL_7_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I, 0x3);
+ wr32_ephy(hw, addr, rdata);
+ } else {
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_HF_TEST_IN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 24, 24, 0x1);
+ set_fields_e56(&rdata, 31, 29, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 0, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_LF_TEST_IN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_9_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 24, 24, 0x1);
+ set_fields_e56(&rdata, 31, 29, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_10_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 0, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ }
+ return status;
+}
+
+static int txgbe_e56_bp_cfg_25g(struct txgbe_hw *hw)
+{
+ u32 addr, rdata;
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_PIN_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_PIN_OVRDVAL_0_INT_PLL0_TX_SIGNAL_TYPE_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_PIN_OVRDEN_0_OVRD_EN_PLL0_TX_SIGNAL_TYPE_I,
+ 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_VCO_SWING_CTRL_I,
+ 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_VCO_SWING_CTRL_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 0, 0x260000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_HF_TEST_IN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_TXS_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256, 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_WKUP_CNT_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32, 0xff);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_PIN_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 27, 24, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_ANA_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_tx_ffe_cfg(hw, TXGBE_LINK_SPEED_25GB_FULL);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_RXS_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN, 0x1fff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_1_PREDIV1, 0x700);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_1_TARGET_CNT1, 0x2418);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_OSC_RANGE_SEL1, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_VCO_CODE_INIT, 0x7fb);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_OSC_CURRENT_BOOST_EN1, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_BBCDR_CURRENT_BOOST1, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK,
+ 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK, 0x7);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_INTL_CONFIG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_INTL_CONFIG_0_ADC_INTL2SLICE_DELAY1, 0x3333);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_INTL_CONFIG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_INTL_CONFIG_2_INTERLEAVER_HBW_DISABLE1, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH, 0x56);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH, 0x6a);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH, 0x1f8);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH, 0xf0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH, 0x100);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH, 0x4);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH, 0x37);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE, 0x38);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56G__RXS0_FOM_18__ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFFL_HINT__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFFL_HINT__LSB, 0x0);
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFFH_HINT__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFFH_HINT__LSB, 0x0);
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFF_HINT_LOAD__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFF_HINT_LOAD__LSB, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET, 0x34);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123, 0xa);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0, 0x9);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT, 0x1ffffea);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1, 18);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2, 0);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1, 1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2, 0);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8,
+ 0xc);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_FFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN, 0xf9ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_IDLE_DETECT_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x6cc;
+ rdata = 0x8020000;
+ wr32_ephy(hw, addr, rdata);
+ addr = 0x94;
+ rdata = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 4, 0, 0x0);
+ set_fields_e56(&rdata, 14, 13, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I,
+ 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 2, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_EYE_SCAN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER, 0x400);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_RINGO_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 21, 12, 0x366);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K, 0x80);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K, 0x18);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K, 0x3e);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL, 0x3);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN, 0x40);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN, 0x4bf);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN, 0xc4bf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_8_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN, 0x47ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_12_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN, 0x67ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_13_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN, 0x8001);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN, 0x8002);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN, 0x8008);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN, 0x8004);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN, 0x20c0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_18_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_29_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN, 0x3f6d);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_33_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_34_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_KRT_TFSM_CFG_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K, 0x49);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K, 0x37);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K, 0x2f);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2,
+ 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ return 0;
+}
+
+static int txgbe_e56_bp_cfg_10g(struct txgbe_hw *hw)
+{
+ u32 addr, rdata;
+
+ rdata = 0x0000;
+ addr = E56G__CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G__CMS_ANA_OVRDVAL_7 *)&rdata)->ana_lcpll_lf_vco_swing_ctrl_i = 0xf;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56G__CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G__CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_vco_swing_ctrl_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56G__CMS_ANA_OVRDVAL_9_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 0, 0x260000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56G__CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G__CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_test_in_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_TXS_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256, 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_WKUP_CNT_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32, 0xff);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_PIN_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 19, 16, 0x6);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_ANA_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_tx_ffe_cfg(hw, TXGBE_LINK_SPEED_10GB_FULL);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_RXS_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN, 0x1fff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->prediv0 = 0xfa0;
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->target_cnt0 = 0x203a;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_range_sel0 = 0x2;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->vco_code_init = 0x7ff;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_current_boost_en0 = 0x1;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->bbcdr_current_boost0 = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK,
+ 0xc);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK, 0x7);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_INTL_CONFIG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_0 *)&rdata)->adc_intl2slice_delay0 = 0x5555;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_INTL_CONFIG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_2 *)&rdata)->interleaver_hbw_disable0 = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH, 0x56);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH, 0x6a);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH, 0x1e8);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH, 0x78);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH, 0x100);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH, 0x4);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH, 0x37);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE, 0x38);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET, 0x34);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123, 0xa);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0, 0x9);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT, 0x1ffffea);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1, 0x18);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2, 0);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1, 1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2, 0);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8,
+ 0xc);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_FFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN, 0xf9ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_IDLE_DETECT_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x6cc;
+ rdata = 0x8020000;
+ wr32_ephy(hw, addr, rdata);
+ addr = 0x94;
+ rdata = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 4, 0, 0x6);
+ set_fields_e56(&rdata, 14, 13, 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I,
+ 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 2, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_EYE_SCAN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER, 0x400);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_RINGO_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 21, 12, 0x366);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K, 0x80);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K, 0x18);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K, 0x3e);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL, 0x3);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN, 0x40);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN, 0x4bf);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN, 0xc4bf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_8_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN, 0x47ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_12_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN, 0x67ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_13_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN, 0x8001);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN, 0x8002);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN, 0x8008);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN, 0x8004);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN, 0x20c0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_18_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_29_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN, 0x3f6d);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_33_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_34_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_KRT_TFSM_CFG_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K, 0x49);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K, 0x37);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K, 0x2f);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2,
+ 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ return 0;
+}
+
+static int txgbe_set_phy_link_mode(struct txgbe_hw *hw,
+ u8 bp_link_mode)
+{
+ int status = 0;
+ u32 rdata = 0;
+
+ u32 speed_select = 0;
+ u32 pcs_type_sel = 0;
+ u32 cns_en = 0;
+ u32 rsfec_en = 0;
+ u32 pma_type = 0;
+ u32 an0_rate_select = 0;
+
+ switch (bp_link_mode) {
+ case 10:
+ bp_link_mode = 10;
+ speed_select = 0; /* 10 Gb/s */
+ pcs_type_sel = 0; /* 10GBASE-R PCS Type */
+ cns_en = 0; /* CNS_EN disable */
+ rsfec_en = 0; /* RS-FEC disable */
+ pma_type = 0xb; /* 10GBASE-KR PMA/PMD type */
+ an0_rate_select = 2; /* 10G-KR */
+ break;
+ case 40:
+ bp_link_mode = 40;
+ speed_select = 3; /* 40 Gb/s */
+ pcs_type_sel = 4; /* 40GBASE-R PCS Type */
+ cns_en = 0; /* CNS_EN disable */
+ rsfec_en = 0; /* RS-FEC disable */
+ pma_type = 0b0100001; /* 40GBASE-CR PMA/PMD type */
+ an0_rate_select = 4; /* 40G-KR: 3 40G-CR: 4 */
+ break;
+ case 25:
+ bp_link_mode = 25;
+ speed_select = 5; /* 25 Gb/s */
+ pcs_type_sel = 7; /* 25GBASE-R PCS Type */
+ cns_en = 1; /* CNS_EN */
+ rsfec_en = 1; /* RS-FEC enable*/
+ pma_type = 0b0111001; /* 25GBASE-KR PMA/PMD type */
+ an0_rate_select = 9; /* 9/10/17 25GK/CR-S or 25GK/CR */
+ break;
+ default:
+ BP_LOG("%s %d :Invalid bp_link_mode\n", __func__, __LINE__);
+ break;
+ }
+
+ hw->curbp_link_mode = bp_link_mode;
+ /* To switch to the 40G mode Ethernet operation, complete the following steps:*/
+ /* 1. Initiate the vendor-specific software reset by programming
+ * the VR_RST field (bit [15]) of the VR_PCS_DIG_CTRL1 register to 1.
+ */
+ rdata = rd32_epcs(hw, 0x038000);
+ wr32_epcs(hw, 0x038000, rdata | BIT(15));
+
+ /* 2. Wait for the hardware to clear the value for the VR_RST
+ * field (bit [15]) of the VR_PCS_DIG_CTRL1 register.
+ */
+ BP_LOG("Wait for the bit [15] (VR_RST) to get cleared.\n");
+ status = kr_read_poll(rd32_ephy, rdata,
+ FIELD_GET_M(BIT(15), rdata) == 0, 100,
+ 2000, hw, 0x038000);
+ BP_LOG("Wait PHY VR_RST = %x, Wait VR_RST %s.\n",
+ rdata, status ? "FAILED" : "SUCCESS");
+
+ /* wait rx/tx/cm powerdn_st according pmd 50 2.0.5 */
+ status = kr_read_poll(rd32_ephy, rdata,
+ (rdata & GENMASK(3, 0)) == 0x9, 100,
+ 2000, hw, 0x14d4);
+ BP_LOG("wait ctrl_fsm_cm_st = %x, %s.\n",
+ rdata, status ? "FAILED" : "SUCCESS");
+
+ /* 3. Write 4'b0011 to bits [5:2] of the SR_PCS_CTRL1 register.
+ * 10G: 0 25G: 5 40G: 3
+ */
+ rdata = rd32_epcs(hw, 0x030000);
+ set_fields_e56(&rdata, 5, 2, speed_select);
+ wr32_epcs(hw, 0x030000, rdata);
+
+ /* 4. Write pcs mode sel to bits [3:0] of the SR_PCS_CTRL2 register.
+ * 10G: 0 25G: 4'b0111 40G: 4'b0100
+ */
+ rdata = rd32_epcs(hw, 0x030007);
+ set_fields_e56(&rdata, 3, 0, pcs_type_sel);
+ wr32_epcs(hw, 0x030007, rdata);
+
+ /* 0 1 1 1 0 0 1 : 25GBASE-KR or 25GBASE-KR-S PMA/PMD type
+ * 0 1 1 1 0 0 0 : 25GBASE-CR or 25GBASE-CR-S PMA/PMD type
+ * 0 1 0 0 0 0 1 : 40GBASE-CR4 PMA/PMD type
+ * 0 1 0 0 0 0 0 : 40GBASE-KR4 PMA/PMD type
+ * 0 0 0 1 0 1 1 : 10GBASE-KR PMA/PMD type
+ */
+ rdata = rd32_epcs(hw, 0x010007);
+ set_fields_e56(&rdata, 6, 0, pma_type);
+ wr32_epcs(hw, 0x010007, rdata);
+
+ /* 5. Write only 25g en to Bits [1:0] of VR_PCS_DIG_CTRL3 register. */
+ rdata = rd32_epcs(hw, 0x38003);
+ set_fields_e56(&rdata, 1, 0, cns_en);
+ wr32_epcs(hw, 0x38003, rdata);
+
+ /* 6. Program PCS_AM_CNT field of VR_PCS_AM_CNT register to 'd16383 to
+ * configure the alignment marker interval. To speed-up simulation,
+ * program a smaller value to this field.
+ */
+ if (bp_link_mode == 40)
+ wr32_epcs(hw, 0x38018, 16383);
+
+ /* 7. Program bit [2] of SR_PMA_RS_FEC_CTRL register to 0
+ * if previously 1 (as RS-FEC is supported in 25G Mode).
+ */
+
+ rdata = rd32_epcs(hw, 0x100c8);
+ set_fields_e56(&rdata, 2, 2, rsfec_en);
+ wr32_epcs(hw, 0x100c8, rdata);
+
+ /* 8. To enable BASE-R FEC (if desired), set bit [0].
+ * in SR_PMA_KR_FEC_CTRL register
+ */
+
+ /* 4. set phy an status to 0 */
+ rdata = rd32_ephy(hw, 0x1434);
+ set_fields_e56(&rdata, 7, 4, 0xe);
+ wr32_ephy(hw, 0x1434, rdata);
+
+ /* 9. Program Enterprise 56G PHY regs through its own APB interface:
+ * a. Program PHY registers as mentioned in Table 6-6 on page 1197 to
+ * configure the PHY to 40G
+ * Mode. For fast-simulation mode, additionally program,
+ * the registers shown in the Table 6-7 on page 1199
+ * b. Enable the PMD by setting pmd_en field in PMD_CFG[0] (0x1400)
+ * register
+ */
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, ANA_OVRDVAL0);
+ set_fields_e56(&rdata, 29, 29, 0x1);
+ set_fields_e56(&rdata, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL0, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, ANA_OVRDVAL5);
+ set_fields_e56(&rdata, 24, 24, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL5, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, ANA_OVRDEN0);
+ set_fields_e56(&rdata, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN0, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, ANA_OVRDEN1);
+ set_fields_e56(&rdata, 30, 30, 0x1);
+ set_fields_e56(&rdata, 25, 25, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN1, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, PLL0_CFG0);
+ set_fields_e56(&rdata, 25, 24, 0x1);
+ set_fields_e56(&rdata, 17, 16, 0x3);
+ wr32_ephy(hw, PLL0_CFG0, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, PLL0_CFG2);
+ set_fields_e56(&rdata, 12, 8, 0x4);
+ wr32_ephy(hw, PLL0_CFG2, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, PLL1_CFG0);
+ set_fields_e56(&rdata, 25, 24, 0x1);
+ set_fields_e56(&rdata, 17, 16, 0x3);
+ wr32_ephy(hw, PLL1_CFG0, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, PLL1_CFG2);
+ set_fields_e56(&rdata, 12, 8, 0x8);
+ wr32_ephy(hw, PLL1_CFG2, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, PLL0_DIV_CFG0);
+ set_fields_e56(&rdata, 18, 8, 0x294);
+ set_fields_e56(&rdata, 4, 0, 0x8);
+ wr32_ephy(hw, PLL0_DIV_CFG0, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, DATAPATH_CFG0);
+ set_fields_e56(&rdata, 30, 28, 0x7);
+ set_fields_e56(&rdata, 26, 24, 0x5);
+ if (bp_link_mode == 10 || bp_link_mode == 40)
+ set_fields_e56(&rdata, 18, 16, 0x5);
+ else if (bp_link_mode == 25)
+ set_fields_e56(&rdata, 18, 16, 0x3);
+ set_fields_e56(&rdata, 14, 12, 0x5);
+ set_fields_e56(&rdata, 10, 8, 0x5);
+ wr32_ephy(hw, DATAPATH_CFG0, rdata);
+
+ rdata = 0x0000;
+ rdata = rd32_ephy(hw, DATAPATH_CFG1);
+ set_fields_e56(&rdata, 26, 24, 0x5);
+ set_fields_e56(&rdata, 10, 8, 0x5);
+ if (bp_link_mode == 10 || bp_link_mode == 40) {
+ set_fields_e56(&rdata, 18, 16, 0x5);
+ set_fields_e56(&rdata, 2, 0, 0x5);
+ } else if (bp_link_mode == 25) {
+ set_fields_e56(&rdata, 18, 16, 0x3);
+ set_fields_e56(&rdata, 2, 0, 0x3);
+ }
+ wr32_ephy(hw, DATAPATH_CFG1, rdata);
+
+ rdata = rd32_ephy(hw, AN_CFG1);
+ set_fields_e56(&rdata, 4, 0, an0_rate_select);
+ wr32_ephy(hw, AN_CFG1, rdata);
+
+ status = txgbe_e56_cms_cfg_for_temp_track_range(hw);
+
+ if (bp_link_mode == 10)
+ txgbe_e56_bp_cfg_10g(hw);
+ else if (bp_link_mode == 25)
+ txgbe_e56_bp_cfg_25g(hw);
+ else if (bp_link_mode == 40)
+ txgbe_e56_cfg_40g(hw);
+
+ return status;
+}
+
+int txgbe_e56_set_phy_link_mode(struct txgbe_hw *hw,
+ u8 bp_link_mode, u32 need_restart)
+{
+ int status = 0;
+ u32 rdata;
+
+ UNREFERENCED_PARAMETER(bp_link_mode);
+
+ hw->an_done = false;
+ if (hw->curbp_link_mode == 10 && !need_restart)
+ return 0;
+ BP_LOG("Setup to backplane mode ==========\n");
+
+ u32 backplane_mode = 0;
+ u32 fec_advertise = 0;
+
+ hw->an_done = false;
+ /* pcs + phy rst */
+ rdata = rd32(hw, 0x1000c);
+ if (hw->bus.lan_id == 1)
+ rdata |= BIT(16);
+ else
+ rdata |= BIT(19);
+ wr32(hw, 0x1000c, rdata);
+ msleep(20);
+
+ /* clear interrupt */
+ wr32_epcs(hw, 0x070000, 0);
+ wr32_epcs(hw, 0x030000, 0x8000);
+ rdata = rd32_epcs(hw, 0x070000);
+ set_fields_e56(&rdata, 12, 12, 0x1);
+ wr32_epcs(hw, 0x070000, rdata);
+ wr32_epcs(hw, 0x078002, 0x0000);
+ /* pcs case fec en to work around first */
+ wr32_epcs(hw, 0x100ab, 1);
+
+ if (txgbe_is_backplane(hw)) {
+ /* backplane 10G/25G/40G */
+ /* 10GKR:7-25KR:14/15-40GKR:8-40GCR:9 */
+ /* default all speed */
+ if ((hw->device_id & 0xFF) == 0x10) {
+ backplane_mode |= BIT(7);
+ fec_advertise |= TXGBE_10G_FEC_ABL;
+ } else if ((hw->device_id & 0xFF) == 0x25) {
+ backplane_mode |= BIT(14) | BIT(15);
+ fec_advertise |= TXGBE_25G_RS_FEC_REQ |
+ TXGBE_25G_BASE_FEC_REQ;
+ } else if ((hw->device_id & 0xFF) == 0x40) {
+ if (hw->phy.bp_capa == 0)
+ /* original configure: KR4 + CR4 */
+ backplane_mode |= BIT(9) | BIT(8);
+ else if (hw->phy.bp_capa == 1)
+ /* only 40GBASE-KR4 */
+ backplane_mode |= BIT(8);
+ else if (hw->phy.bp_capa == 2)
+ /* only 40GBASE-CR4 */
+ backplane_mode |= BIT(9);
+ fec_advertise |= TXGBE_10G_FEC_ABL;
+ BP_LOG("Advertised abilities: %d\n", backplane_mode);
+ }
+ } else {
+ if ((hw->phy.fiber_suppport_speed & TXGBE_LINK_SPEED_10GB_FULL)
+ == TXGBE_LINK_SPEED_10GB_FULL) {
+ backplane_mode |= 0x80;
+ fec_advertise |= TXGBE_10G_FEC_ABL;
+ }
+
+ if ((hw->phy.fiber_suppport_speed & TXGBE_LINK_SPEED_25GB_FULL)
+ == TXGBE_LINK_SPEED_25GB_FULL) {
+ backplane_mode |= 0xc000;
+ fec_advertise |= TXGBE_25G_RS_FEC_REQ |
+ TXGBE_25G_BASE_FEC_REQ;
+ }
+
+ if ((hw->phy.fiber_suppport_speed & TXGBE_LINK_SPEED_40GB_FULL)
+ == TXGBE_LINK_SPEED_40GB_FULL) {
+ backplane_mode |= BIT(9) | BIT(8);
+ fec_advertise |= TXGBE_10G_FEC_ABL;
+ }
+ }
+
+ wr32_epcs(hw, 0x070010, 0x0001);
+
+ /* 10GKR:7-25KR:14/15-40GKR:8-40GCR:9 */
+ wr32_epcs(hw, 0x070011, backplane_mode | 0x11);
+
+ /* BASE-R FEC */
+ rdata = rd32_epcs(hw, 0x70012);
+ wr32_epcs(hw, 0x70012, fec_advertise);
+
+ wr32_epcs(hw, 0x070016, 0x0000);
+ wr32_epcs(hw, 0x070017, 0x0);
+ wr32_epcs(hw, 0x070018, 0x0);
+
+ /* config timer */
+ wr32_epcs(hw, 0x078004, 0x003c);
+ wr32_epcs(hw, 0x078005, CL74_KRTR_TRAINNING_TIMEOUT);
+ wr32_epcs(hw, 0x078006, 25);
+ wr32_epcs(hw, 0x078000, 0x0008 | BIT(2));
+
+ BP_LOG("1.2 Wait 10G KR phy/pcs mode init ....\n");
+ status = txgbe_set_phy_link_mode(hw, 10);
+ BP_LOG("Wait 10g phy/pcs mode init = %x, %s.\n", rdata,
+ /* wait rx/tx/cm powerdn_st according pmd 50 2.0.5 */
+ status ? "FAILED" : "SUCCESS");
+
+ /* 5. CM_ENABLE */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 21, 20, 0x3); /* pll en */
+ set_fields_e56(&rdata, 19, 12, 0x0); /* tx disable */
+ set_fields_e56(&rdata, 8, 8, 0x0); /* pmd mode */
+ set_fields_e56(&rdata, 1, 1, 0x1); /* pmd en */
+ wr32_ephy(hw, 0x1400, rdata);
+
+ /* 6, TX_ENABLE */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 19, 12, 0x1); /* tx en */
+ wr32_ephy(hw, 0x1400, rdata);
+
+ BP_LOG("1.3 Wait 10G PHY RXS....\n");
+ status = txgbe_e56_rxs_osc_init_for_temp_track_range(hw, 10);
+ BP_LOG("Wait 10G PHY/RXS mode init = %x, %s.\n", rdata,
+ status ? "FAILED" : "SUCCESS");
+
+ /* Wait an 10g fsm_rx_sts */
+ status = kr_read_poll(rd32_ephy, rdata,
+ ((rdata & 0x3f) == 0xb), 1000,
+ 200, hw,
+ E56PHY_CTRL_FSM_RX_STAT_0_ADDR);
+ BP_LOG("Wait 10g fsm_rx_sts = %x, Wait rx_sts %s.\n", rdata,
+ status ? "FAILED" : "SUCCESS");
+ rdata = rd32_epcs(hw, 0x070000);
+ set_fields_e56(&rdata, 12, 12, 0x1);
+ wr32_epcs(hw, 0x070000, rdata);
+ BP_LOG("Setup the backplane mode========end ==\n");
+
+ return status;
+}
+
+static void txgbe_e56_print_page_status(struct txgbe_hw *hw,
+ struct txgbe_backplane_ability *local_ability,
+ struct txgbe_backplane_ability *lp_ability)
+{
+ u32 rdata = 0;
+
+ /* Read the local AN73 Base Page Ability Registers */
+ BP_LOG("Read the local Base Page Ability Registers\n");
+ rdata = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
+ local_ability->next_page = (rdata & BIT(15)) ? 1 : 0;
+ BP_LOG("\tread 70010 data %0x\n", rdata);
+ rdata = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
+ BP_LOG("\tread 70011 data %0x\n", rdata);
+ local_ability->link_ability = (rdata >> 5) & GENMASK(10, 0);
+ /* amber-lite only support 10GKR - 25GKR/CR - 25GKR-S/CR-S */
+ BP_LOG("\t10GKR : %x\t25GKR-S/CR-S: %x\t25GKR/CR : %x\n",
+ local_ability->link_ability & BIT(ABILITY_10GBASE_KR) ? 1 : 0,
+ local_ability->link_ability & BIT(ABILITY_25GBASE_KRCR_S) ? 1 : 0,
+ local_ability->link_ability & BIT(ABILITY_25GBASE_KRCR) ? 1 : 0);
+ BP_LOG("\t40GCR4 : %x\t40GKR4 : %x\n",
+ local_ability->link_ability & BIT(ABILITY_40GBASE_CR4) ? 1 : 0,
+ local_ability->link_ability & BIT(ABILITY_40GBASE_KR4) ? 1 : 0);
+ rdata = rd32_epcs(hw, SR_AN_MMD_ADV_REG3);
+ BP_LOG("\tF1:FEC Req\tF0:FEC Sup\tF3:25GFEC\tF2:25GRS\n");
+ BP_LOG("\tF1: %d\t\tF0: %d\t\tF3: %d\t\tF2: %d\n",
+ ((rdata >> 15) & 0x01), ((rdata >> 14) & 0x01),
+ ((rdata >> 13) & 0x01), ((rdata >> 12) & 0x01));
+ local_ability->fec_ability = rdata;
+ BP_LOG("\tread 70012 data %0x\n", rdata);
+
+ /* Read the link partner AN73 Base Page Ability Registers */
+ BP_LOG("Read the link partner Base Page Ability Registers\n");
+ rdata = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
+ lp_ability->next_page = (rdata & BIT(15)) ? 1 : 0;
+ BP_LOG("\tread 70013 data %0x\n", rdata);
+ rdata = rd32_epcs(hw, SR_AN_MMD_LP_ABL2);
+ lp_ability->link_ability = (rdata >> 5) & GENMASK(10, 0);
+ BP_LOG("\tread 70014 data %0x\n", rdata);
+ BP_LOG("\tKX : %x\tKX4 : %x\n",
+ lp_ability->link_ability & BIT(ABILITY_1000BASE_KX) ? 1 : 0,
+ lp_ability->link_ability & BIT(ABILITY_10GBASE_KX4) ? 1 : 0);
+ BP_LOG("\t10GKR : %x\t25GKR-S/CR-S: %x\t25GKR/CR : %x\n",
+ lp_ability->link_ability & BIT(ABILITY_10GBASE_KR) ? 1 : 0,
+ lp_ability->link_ability & BIT(ABILITY_25GBASE_KRCR_S) ? 1 : 0,
+ lp_ability->link_ability & BIT(ABILITY_25GBASE_KRCR) ? 1 : 0);
+ BP_LOG("\t40GCR4 : %x\t40GKR4 : %x\n",
+ lp_ability->link_ability & BIT(ABILITY_40GBASE_CR4) ? 1 : 0,
+ lp_ability->link_ability & BIT(ABILITY_40GBASE_KR4) ? 1 : 0);
+ rdata = rd32_epcs(hw, SR_AN_MMD_LP_ABL3);
+ BP_LOG("\tF1:FEC Req\tF0:FEC Sup\tF3:25GFEC\tF2:25GRS\n");
+ BP_LOG("\tF1: %d\t\tF0: %d\t\tF3: %d\t\tF2: %d\n",
+ ((rdata >> 15) & 0x01), ((rdata >> 14) & 0x01),
+ ((rdata >> 13) & 0x01), ((rdata >> 12) & 0x01));
+ lp_ability->fec_ability = rdata;
+
+ hw->phy.fec_mode = 0;
+ if (rdata & TXGBE_25G_RS_FEC_REQ)
+ hw->phy.fec_mode |= TXGBE_25G_RS_FEC_REQ;
+ if (rdata & TXGBE_25G_BASE_FEC_REQ)
+ hw->phy.fec_mode |= TXGBE_25G_BASE_FEC_REQ;
+ if (rdata & TXGBE_10G_FEC_ABL)
+ hw->phy.fec_mode |= TXGBE_10G_FEC_ABL;
+ if (rdata & TXGBE_10G_FEC_REQ)
+ hw->phy.fec_mode |= TXGBE_10G_FEC_REQ;
+ BP_LOG("\tread 70015 data %0x\n", rdata);
+
+ BP_LOG("\tread 70016 data %0x\n", rd32_epcs(hw, 0x70016));
+ BP_LOG("\tread 70017 data %0x\n", rd32_epcs(hw, 0x70017));
+ BP_LOG("\tread 70018 data %0x\n", rd32_epcs(hw, 0x70018));
+ BP_LOG("\tread 70019 data %0x\n", rd32_epcs(hw, 0x70019));
+ BP_LOG("\tread 7001a data %0x\n", rd32_epcs(hw, 0x7001a));
+ BP_LOG("\tread 7001b data %0x\n", rd32_epcs(hw, 0x7001b));
+}
+
+static int chk_bkp_ability(struct txgbe_hw *hw,
+ struct txgbe_backplane_ability local_ability,
+ struct txgbe_backplane_ability lp_ability)
+{
+ unsigned int com_link_ability;
+
+ BP_LOG("CheckBkpAn73Ability():\n");
+ /* Check the common link ability and take action based on the result*/
+ com_link_ability = local_ability.link_ability &
+ lp_ability.link_ability;
+ BP_LOG("comAbility= 0x%x, Ability= 0x%x, lpAbility= 0x%x\n",
+ com_link_ability, local_ability.link_ability,
+ lp_ability.link_ability);
+
+ if (com_link_ability == 0) {
+ hw->bp_link_mode = 0;
+ BP_LOG("Do not support any compatible speed mode!\n");
+ return -EINVAL;
+ } else if (com_link_ability & BIT(ABILITY_40GBASE_KR4)) {
+ BP_LOG("Link mode is [ABILITY_40GBASE_KR4].\n");
+ hw->bp_link_mode = 40;
+ } else if (com_link_ability & BIT(ABILITY_40GBASE_CR4)) {
+ BP_LOG("Link mode is [ABILITY_40GBASE_CR4].\n");
+ hw->bp_link_mode = 40;
+ } else if (com_link_ability & BIT(ABILITY_25GBASE_KRCR_S)) {
+ BP_LOG("Link mode is [ABILITY_25GBASE_KRCR_S].\n");
+ hw->fec_mode = TXGBE_25G_RS_FEC_REQ;
+ hw->bp_link_mode = 25;
+ } else if (com_link_ability & BIT(ABILITY_25GBASE_KRCR)) {
+ BP_LOG("Link mode is [ABILITY_25GBASE_KRCR].\n");
+ hw->bp_link_mode = 25;
+ } else if (com_link_ability & BIT(ABILITY_10GBASE_KR)) {
+ BP_LOG("Link mode is [ABILITY_10GBASE_KR].\n");
+ hw->bp_link_mode = 10;
+ } else if (com_link_ability & BIT(ABILITY_10GBASE_KX4)) {
+ BP_LOG("Link mode is [ABILITY_10GBASE_KX4].\n");
+ hw->bp_link_mode = 10;
+ } else if (com_link_ability & BIT(ABILITY_1000BASE_KX)) {
+ BP_LOG("Link mode is [ABILITY_1000BASE_KX].\n");
+ hw->bp_link_mode = 1;
+ } else {
+ BP_LOG("No compatible link mode found!\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int txgbe_e56_exchange_page(struct txgbe_hw *hw)
+{
+ struct txgbe_backplane_ability local_ability = {0}, lp_ability = {0};
+ u32 an_int, base_page = 0;
+ int count = 0;
+
+ an_int = rd32_epcs(hw, 0x78002);
+ /* 500ms timeout */
+ if (!(an_int & VR_AN_INTR_PG_RCV))
+ return -EINVAL;
+
+ for (count = 0; count < 500; count++) {
+ u32 fsm = rd32_epcs(hw, 0x78010);
+ u32 rdata = rd32_epcs(hw, 0x78002);
+
+ BP_LOG("-----count----- %d - fsm: %x\n", count, fsm);
+ BP_LOG("read 78002 data %0x and clear pacv\n", rdata);
+ an_int = rdata;
+ set_fields_e56(&rdata, 2, 2, 0x0);
+ wr32_epcs(hw, 0x78002, rdata);
+ if (an_int & VR_AN_INTR_PG_RCV) {
+ u32 addr;
+
+ txgbe_e56_print_page_status(hw, &local_ability, &lp_ability);
+ addr = base_page == 0 ? 0x70013 : 0x70019;
+ rdata = rd32_epcs(hw, addr);
+ if (rdata & BIT(14)) {
+ if (rdata & BIT(15)) {
+ /* always set null message */
+ wr32_epcs(hw, 0x70016, 0x2001);
+ BP_LOG("write 70016 0x%0x\n",
+ 0x2001);
+ }
+ base_page = 1;
+ }
+ }
+ if ((fsm & 0x8) == 0x8) {
+ hw->fsm = 0x8;
+ goto check_ability;
+ }
+ usec_delay(100);
+ }
+
+check_ability:
+ return chk_bkp_ability(hw, local_ability, lp_ability);
+}
+
+static int txgbe_e56_cl72_trainning(struct txgbe_hw *hw)
+{
+ u32 bylinkmode = hw->bp_link_mode;
+ u8 bypass_ctle = hw->bypass_ctle;
+ int status = 0, temp_data = 0;
+ u32 lane_num = 0, lane_idx = 0;
+ u32 __rte_unused pmd_ctrl = 0, txffe = 0;
+ int ret = 0;
+ u32 rdata;
+
+ u8 pll_en_cfg = 0;
+ u8 pmd_mode = 0;
+
+ switch (bylinkmode) {
+ case 10:
+ bylinkmode = 10;
+ lane_num = 1;
+ pll_en_cfg = 3;
+ pmd_mode = 0;
+ break;
+ case 40:
+ bylinkmode = 40;
+ lane_num = 4;
+ pll_en_cfg = 0; /* pll_en_cfg : single link to 0 */
+ pmd_mode = 1; /* pmd mode : 1 - single link */
+ break;
+ case 25:
+ bylinkmode = 25;
+ lane_num = 1;
+ pll_en_cfg = 3;
+ pmd_mode = 0;
+ break;
+ default:
+ BP_LOG("%s %d :Invalid speed\n", __func__, __LINE__);
+ break;
+ }
+
+ BP_LOG("2.3 Wait %dG KR phy mode init ....\n", bylinkmode);
+ status = txgbe_set_phy_link_mode(hw, bylinkmode);
+
+ /* 13. set phy an status to 1 - AN_CFG[0]: 4-7 lane0-lane3 */
+ rdata = rd32_ephy(hw, 0x1434);
+ set_fields_e56(&rdata, 7, 4, GENMASK(lane_num - 1, 0));
+ wr32_ephy(hw, 0x1434, rdata);
+
+ /* 14 and 15. kr training: set BASER_PMD_CONTROL[0, 7] for lane0-4 */
+ rdata = rd32_ephy(hw, 0x1640);
+ set_fields_e56(&rdata, 7, 0, GENMASK(2 * lane_num - 1, 0));
+ wr32_ephy(hw, 0x1640, rdata);
+
+ /* 16. enable CMS and its internal PLL */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 21, 20, pll_en_cfg);
+ set_fields_e56(&rdata, 19, 12, 0); /* tx/rx off */
+ set_fields_e56(&rdata, 8, 8, pmd_mode);
+ set_fields_e56(&rdata, 1, 1, 0x1); /* pmd en */
+ wr32_ephy(hw, 0x1400, rdata);
+
+ /* 17. tx enable PMD_CFG[0] */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 15, 12, GENMASK(lane_num - 1, 0)); /* tx en */
+ wr32_ephy(hw, 0x1400, rdata);
+
+ /* 18 */
+ /* 19. rxs calibration and adaotation sequeence */
+ BP_LOG("2.4 Wait %dG RXS.... fsm: %x\n",
+ bylinkmode, rd32_epcs(hw, 0x78010));
+ status = txgbe_e56_phy_rxs_calib_adapt_seq(hw, bylinkmode, bypass_ctle);
+ ret |= status;
+ /* 20 */
+ BP_LOG("2.5 Wait %dG phy calibration.... fsm: %x\n",
+ bylinkmode, rd32_epcs(hw, 0x78010));
+ txgbe_e56_set_rxs_ufine_le_max(hw, bylinkmode);
+ status = txgbe_e56_get_temp(hw, &temp_data);
+ if (bylinkmode == 40)
+ status = txgbe_temp_track_seq_40g(hw, TXGBE_LINK_SPEED_40GB_FULL);
+ else
+ status = txgbe_e56_rxs_post_cdr_lock_temp_track_seq(hw, bylinkmode);
+ /* 21 */
+ BP_LOG("2.6 Wait %dG phy kr training check.... fsm: %x\n",
+ bylinkmode, rd32_epcs(hw, 0x78010));
+ status = kr_read_poll(rd32_ephy, rdata,
+ ((rdata & 0xe) & GENMASK(lane_num, 1)) ==
+ (0xe & GENMASK(lane_num, 1)), 100,
+ 10000, hw, 0x163c);
+ pmd_ctrl = rd32_ephy(hw, 0x1644);
+ BP_LOG("KR TRAINNING CHECK = %x, %s. pmd_ctrl:%lx-%lx-%lx-%lx\n",
+ rdata, status ? "FAILED" : "SUCCESS",
+ FIELD_GET_M(GENMASK(3, 0), pmd_ctrl),
+ FIELD_GET_M(GENMASK(7, 4), pmd_ctrl),
+ FIELD_GET_M(GENMASK(11, 8), pmd_ctrl),
+ FIELD_GET_M(GENMASK(15, 12), pmd_ctrl));
+ ret |= status;
+ BP_LOG("before: %x-%x-%x-%x\n",
+ rd32_ephy(hw, 0x141c), rd32_ephy(hw, 0x1420),
+ rd32_ephy(hw, 0x1424), rd32_ephy(hw, 0x1428));
+
+ for (lane_idx = 0; lane_idx < lane_num; lane_idx++) {
+ txffe = rd32_ephy(hw, 0x828 + lane_idx * 0x100);
+ BP_LOG("after[%x]: %lx-%lx-%lx-%lx\n", lane_idx,
+ FIELD_GET_M(GENMASK(6, 0), txffe),
+ FIELD_GET_M(GENMASK(21, 16), txffe),
+ FIELD_GET_M(GENMASK(29, 24), txffe),
+ FIELD_GET_M(GENMASK(13, 8), txffe));
+ }
+
+ /* 22 */
+ BP_LOG("2.7 Wait %dG phy Rx adc.... fsm:%x\n",
+ bylinkmode, rd32_epcs(hw, 0x78010));
+ status = txgbe_e56_rxs_adc_adapt_seq(hw, bypass_ctle);
+
+ return ret;
+}
+
+int handle_e56_bkp_an73_flow(struct txgbe_hw *hw)
+{
+ int status = 0;
+ u32 rdata;
+
+ BP_LOG("2.1 Wait page changed ....\n");
+ status = txgbe_e56_exchange_page(hw);
+ if (status) {
+ BP_LOG("Exchange page failed\n");
+ return status;
+ }
+
+ BP_LOG("2.2 Wait page changed ..done..\n");
+ wr32_epcs(hw, 0x100ab, 0);
+ if (AN_TRAINNING_MODE) {
+ rdata = rd32_epcs(hw, 0x70000);
+ BP_LOG("read 0x70000 data %0x\n", rdata);
+ wr32_epcs(hw, 0x70000, 0);
+ BP_LOG("write 0x70000 0x%0x\n", 0);
+ }
+
+ rdata = rd32_epcs(hw, 0x78002);
+ BP_LOG("read 78002 data %0x and clear page int\n", rdata);
+ set_fields_e56(&rdata, 2, 2, 0x0);
+ wr32_epcs(hw, 0x78002, rdata);
+
+ /* dis phy tx/rx lane */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 19, 16, 0x0);
+ set_fields_e56(&rdata, 15, 12, 0x0);
+ set_fields_e56(&rdata, 1, 1, 0x0);
+ wr32_ephy(hw, 0x1400, rdata);
+ BP_LOG("Ephy Write A: 0x%x, D: 0x%x\n", 0x1400, rdata);
+
+ /* wait rx/tx/cm powerdn_st */
+ status = kr_read_poll(rd32_ephy, rdata,
+ (rdata & GENMASK(3, 0)) == 0x9, 100,
+ 2000, hw, 0x14d4);
+ BP_LOG("wait ctrl_fsm_cm_st = %x, %s.\n",
+ rdata, status ? "FAILED" : "SUCCESS");
+
+ if (hw->phy.fec_mode & TXGBE_25G_RS_FEC_REQ) {
+ wr32_epcs(hw, 0x180a3, 0x68c1);
+ wr32_epcs(hw, 0x180a4, 0x3321);
+ wr32_epcs(hw, 0x180a5, 0x973e);
+ wr32_epcs(hw, 0x180a6, 0xccde);
+
+ wr32_epcs(hw, 0x38018, 1024);
+ rdata = rd32_epcs(hw, 0x100c8);
+ set_fields_e56(&rdata, 2, 2, 1);
+ wr32_epcs(hw, 0x100c8, rdata);
+ BP_LOG("Advertised FEC modes : %s\n", "RS-FEC");
+ hw->cur_fec_link = TXGBE_PHY_FEC_RS;
+ } else if (hw->phy.fec_mode & TXGBE_25G_BASE_FEC_REQ) {
+ /* FEC: FC-FEC/BASE-R */
+ wr32_epcs(hw, 0x100ab, BIT(0));
+ BP_LOG("Epcs Write A: 0x%x, D: 0x%x\n", 0x100ab, 1);
+ PMD_DRV_LOG(INFO, "Advertised FEC modes : %s", "25GBASE-R");
+ hw->cur_fec_link = TXGBE_PHY_FEC_BASER;
+ } else if (hw->fec_mode & (TXGBE_10G_FEC_REQ)) {
+ /* FEC: FC-FEC/BASE-R */
+ wr32_epcs(hw, 0x100ab, BIT(0));
+ BP_LOG("Epcs Write A: 0x%x, D: 0x%x\n", 0x100ab, 1);
+ PMD_DRV_LOG(INFO, "Advertised FEC modes : %s", "BASE-R");
+ hw->cur_fec_link = TXGBE_PHY_FEC_BASER;
+ } else {
+ PMD_DRV_LOG(INFO, "Advertised FEC modes : %s", "NONE");
+ hw->cur_fec_link = TXGBE_PHY_FEC_OFF;
+ }
+
+ status = txgbe_e56_cl72_trainning(hw);
+
+ rdata = rd32_ephy(hw, E56PHY_RXS_IDLE_DETECT_1_ADDR);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0x28);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0xa);
+ wr32_ephy(hw, E56PHY_RXS_IDLE_DETECT_1_ADDR, rdata);
+ wr32_ephy(hw, E56PHY_INTR_0_ADDR, E56PHY_INTR_0_IDLE_ENTRY1);
+ wr32_ephy(hw, E56PHY_INTR_1_ADDR, E56PHY_INTR_1_IDLE_EXIT1);
+ wr32_ephy(hw, E56PHY_INTR_0_ENABLE_ADDR, E56PHY_INTR_0_IDLE_ENTRY1);
+ wr32_ephy(hw, E56PHY_INTR_1_ENABLE_ADDR, E56PHY_INTR_1_IDLE_EXIT1);
+
+ return status;
+}
diff --git a/drivers/net/txgbe/base/txgbe_e56_bp.h b/drivers/net/txgbe/base/txgbe_e56_bp.h
index 97d5656cad..9329387334 100644
--- a/drivers/net/txgbe/base/txgbe_e56_bp.h
+++ b/drivers/net/txgbe/base/txgbe_e56_bp.h
@@ -276,4 +276,7 @@ typedef union {
#define E56PHY_CMS_ANA_OVRDVAL_10_ADDR (E56PHY_CMS_BASE_ADDR + 0xD8)
#define E56PHY_CMS_ANA_OVRDVAL_7_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I 8, 4
+int txgbe_e56_set_phy_link_mode(struct txgbe_hw *hw,
+ u8 bp_link_mode, u32 need_restart);
+int handle_e56_bkp_an73_flow(struct txgbe_hw *hw);
#endif
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 0c6a74c562..6d76b4854c 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -4071,6 +4071,12 @@ s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
return err;
}
+bool txgbe_is_backplane(struct txgbe_hw *hw)
+{
+ return hw->phy.get_media_type(hw) == txgbe_media_type_backplane ?
+ true : false;
+}
+
bool txgbe_gpio_ext_check(struct txgbe_hw *hw, u8 gpio_ext_mask)
{
u32 gpio_ext = rd32(hw, TXGBE_GPIOEXT);
diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h
index bc34d639eb..b44190bc34 100644
--- a/drivers/net/txgbe/base/txgbe_hw.h
+++ b/drivers/net/txgbe/base/txgbe_hw.h
@@ -118,6 +118,6 @@ s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw);
bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw);
s32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr);
s32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr, u32 *data);
-s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed,
- bool *link_up);
+bool txgbe_is_backplane(struct txgbe_hw *hw);
+bool txgbe_gpio_ext_check(struct txgbe_hw *hw, u8 gpio_ext_mask);
#endif /* _TXGBE_HW_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_osdep.h b/drivers/net/txgbe/base/txgbe_osdep.h
index f4282b3241..da069e94f6 100644
--- a/drivers/net/txgbe/base/txgbe_osdep.h
+++ b/drivers/net/txgbe/base/txgbe_osdep.h
@@ -162,6 +162,10 @@ static inline u64 REVERT_BIT_MASK64(u64 mask)
((mask & 0xFFFFFFFF00000000) >> 32);
}
+#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
+#define GENMASK(h, l) \
+ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+
#define IOMEM
#define BIT(nr) (1UL << (nr))
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index bf7260a295..f3e3491b30 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -2503,6 +2503,27 @@ void txgbe_set_phy_temp(struct txgbe_hw *hw)
}
}
+int txgbe_is_dac_cable(struct txgbe_hw *hw)
+{
+ if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1 ||
+ hw->phy.sfp_type == txgbe_sfp_type_da_act_lmt_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_da_act_lmt_core1 ||
+ hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core0 ||
+ hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core1)
+ return true;
+
+ return false;
+}
+
+int txgbe_xpcs_an_enabled(struct txgbe_hw *hw)
+{
+ if (!(txgbe_is_dac_cable(hw) || txgbe_is_backplane(hw)))
+ return false;
+
+ return hw->devarg.auto_neg ? true : false;
+}
+
/**
* txgbe_kr_handle - Handle the interrupt of auto-negotiation
* @hw: pointer to hardware structure
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index c02be3cc34..3fe7a34409 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -105,6 +105,8 @@
#define VR_AN_INTR_CMPLT MS16(0, 0x1)
#define VR_AN_INTR_LINK MS16(1, 0x1)
#define VR_AN_INTR_PG_RCV MS16(2, 0x1)
+#define TXGBE_E56_AN_TXDIS MS16(3, 0x1)
+#define TXGBE_E56_AN_PG_RCV MS16(4, 0x1)
#define VR_AN_KR_MODE_CL 0x078003
#define VR_AN_KR_MODE_CL_PDET MS16(0, 0x1)
#define VR_XS_OR_PCS_MMD_DIGI_CTL1 0x038000
@@ -428,6 +430,24 @@
#define TXGBE_BP_M_NAUTO 0
#define TXGBE_BP_M_AUTO 1
+#define kr_read_poll(op, val, cond, sleep_us, \
+ times, args...) \
+({ \
+ unsigned long __sleep_us = (sleep_us); \
+ u32 __times = (times); \
+ u32 i; \
+ int __cond = 0; \
+ for (i = 0; i < __times; i++) { \
+ (val) = op(args); \
+ if (cond) { \
+ __cond = 1; \
+ break; \
+ } \
+ usleep(__sleep_us);\
+ } \
+ (__cond) ? 0 : -1; \
+})
+
#ifndef CL72_KRTR_PRBS_MODE_EN
#define CL72_KRTR_PRBS_MODE_EN 0xFFFF /* open kr prbs check */
#endif
@@ -490,6 +510,8 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 value);
void txgbe_bp_mode_set(struct txgbe_hw *hw);
void txgbe_set_phy_temp(struct txgbe_hw *hw);
void txgbe_bp_down_event(struct txgbe_hw *hw);
+int txgbe_is_dac_cable(struct txgbe_hw *hw);
+int txgbe_xpcs_an_enabled(struct txgbe_hw *hw);
s32 txgbe_kr_handle(struct txgbe_hw *hw);
#endif /* _TXGBE_PHY_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 7fb4bcc513..47629aa9e0 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -719,6 +719,7 @@ struct txgbe_phy_info {
u32 addr;
u32 id;
enum txgbe_sfp_type sfp_type;
+ u32 fiber_suppport_speed;
bool sfp_setup_needed;
u32 revision;
u32 media_type;
@@ -740,6 +741,7 @@ struct txgbe_phy_info {
u16 ffe_pre2;
u16 ffe_post;
u16 fec_mode;
+ u16 bp_capa;
};
#define TXGBE_DEVARG_BP_AUTO "auto_neg"
@@ -899,7 +901,28 @@ struct txgbe_hw {
u32 cur_fec_link;
int temperature;
u32 bp_link_mode;
-};
+ bool dac_sfp;
+ bool bypass_ctle;
+ u32 curbp_link_mode;
+ bool an_done;
+ u32 fsm;
+ u64 bp_event_interval;
+};
+
+typedef enum {
+ ABILITY_1000BASE_KX,
+ ABILITY_10GBASE_KX4,
+ ABILITY_10GBASE_KR,
+ ABILITY_40GBASE_KR4,
+ ABILITY_40GBASE_CR4,
+ ABILITY_100GBASE_CR10,
+ ABILITY_100GBASE_KP4,
+ ABILITY_100GBASE_KR4,
+ ABILITY_100GBASE_CR4,
+ ABILITY_25GBASE_KRCR_S,
+ ABILITY_25GBASE_KRCR,
+ ABILITY_MAX,
+} ability_filed_encding;
struct txgbe_backplane_ability {
u32 next_page; /* Next Page (bit0) */
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 02c3305712..56987ae028 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -2010,6 +2010,10 @@ txgbe_dev_start(struct rte_eth_dev *dev)
txgbe_l2_tunnel_conf(dev);
txgbe_filter_restore(dev);
+ hw->bp_event_interval = 100 * 1000;
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ rte_eal_alarm_set(hw->bp_event_interval, txgbe_dev_e56_check_bp_event, dev);
+
if (tm_conf->root && !tm_conf->committed)
PMD_DRV_LOG(WARNING,
"please call hierarchy_commit() "
@@ -2054,8 +2058,10 @@ txgbe_dev_stop(struct rte_eth_dev *dev)
PMD_INIT_FUNC_TRACE();
- if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ rte_eal_alarm_cancel(txgbe_dev_e56_check_bp_event, dev);
rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler_aml, hw);
+ }
rte_eal_alarm_cancel(txgbe_dev_detect_sfp, dev);
rte_eal_alarm_cancel(txgbe_tx_queue_clear_error, dev);
@@ -2926,6 +2932,107 @@ txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements)
return NULL;
}
+void txgbe_dev_e56_check_bp_event(void *param)
+{
+ struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ u32 an_int1 = 0, value = 0, fsm = 0;
+ u32 __rte_unused an_int = 0;
+ int ret = 0;
+ bool need_link_update = false;
+
+ if (!hw)
+ return;
+
+ if (!(txgbe_xpcs_an_enabled(hw)))
+ return;
+
+ if (!hw->devarg.auto_neg)
+ return;
+
+ /* only continue if link is down */
+ if (dev->data->dev_link.link_status)
+ goto out;
+
+ value = rd32_epcs(hw, VR_AN_INTR);
+ an_int = value;
+ if (value & 0xF)
+ hw->bp_event_interval = 100 * 1000;
+
+ if (value & VR_AN_INTR_CMPLT) {
+ hw->an_done = true;
+ need_link_update = true;
+ value &= ~VR_AN_INTR_CMPLT;
+ wr32_epcs(hw, VR_AN_INTR, value);
+ }
+
+ if (value & VR_AN_INTR_LINK) {
+ value &= ~VR_AN_INTR_LINK;
+ wr32_epcs(hw, VR_AN_INTR, value);
+ }
+
+ if (value & TXGBE_E56_AN_TXDIS) {
+ value &= ~TXGBE_E56_AN_TXDIS;
+ wr32_epcs(hw, VR_AN_INTR, value);
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_set_phy_link_mode(hw, 10, hw->bypass_ctle);
+ rte_spinlock_unlock(&hw->phy_lock);
+ goto an_status;
+ }
+
+ if (value & VR_AN_INTR_PG_RCV) {
+ BP_LOG("%d Enter training\n", hw->port_id);
+ ret = handle_e56_bkp_an73_flow(hw);
+ if (!AN_TRAINNING_MODE) {
+ fsm = rd32_epcs(hw, 0x78010);
+ if (fsm & 0x8)
+ goto an_status;
+ if (ret) {
+ BP_LOG("Training FAILED, do reset\n");
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_set_phy_link_mode(hw, 10, hw->bypass_ctle);
+ rte_spinlock_unlock(&hw->phy_lock);
+ } else {
+ BP_LOG("ALL SUCCEEDED\n");
+ }
+ } else {
+ if (ret) {
+ BP_LOG("Training FAILED, do reset\n");
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_set_phy_link_mode(hw, 10, hw->bypass_ctle);
+ rte_spinlock_unlock(&hw->phy_lock);
+ } else {
+ hw->an_done = true;
+ }
+ }
+ }
+
+an_status:
+ an_int1 = rd32_epcs(hw, 0x78002);
+ if (an_int1 & VR_AN_INTR_CMPLT) {
+ hw->an_done = true;
+ need_link_update = true;
+ }
+
+ BP_LOG("%d RLU:%x MLU:%x INT:%x-%x CTL:%x fsm:%x pmd_cfg0:%x an_done:%d\n",
+ hw->port_id, rd32_epcs(hw, 0x30001), rd32(hw, 0x14404),
+ an_int, an_int1,
+ rd32_epcs(hw, 0x70000),
+ rd32_epcs(hw, 0x78010),
+ rd32_ephy(hw, 0x1400),
+ hw->an_done);
+
+ if (need_link_update)
+ txgbe_dev_link_update(dev, 0);
+
+ if (dev->data->dev_link.link_status)
+ hw->bp_event_interval = 2000 * 1000;
+
+out:
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ rte_eal_alarm_set(hw->bp_event_interval, txgbe_dev_e56_check_bp_event, dev);
+}
+
static void
txgbe_dev_detect_sfp(void *param)
{
diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h
index 1ec8e096cc..309db3bfe9 100644
--- a/drivers/net/txgbe/txgbe_ethdev.h
+++ b/drivers/net/txgbe/txgbe_ethdev.h
@@ -747,5 +747,5 @@ void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
uint16_t queue, bool on);
void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
int mask);
-
+void txgbe_dev_e56_check_bp_event(void *param);
#endif /* _TXGBE_ETHDEV_H_ */
--
2.21.0.windows.1
^ permalink raw reply related
* [PATCH v4 13/20] net/txgbe: fix link stability for 40G NIC
From: Zaiyu Wang @ 2026-05-11 10:35 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
The link was previously configured via firmware, but this approach
resulted in unstable link behavior. To resolve the issue, re-add the
PHY configuration flow directly into the driver.
Fixes: ead3616f630d ("net/txgbe: support PHY configuration via SW-FW mailbox")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_aml40.c | 70 +-
drivers/net/txgbe/base/txgbe_aml40.h | 6 +-
drivers/net/txgbe/base/txgbe_e56.c | 1471 ++++++++++++++++++++++++--
drivers/net/txgbe/txgbe_ethdev.c | 4 +-
4 files changed, 1438 insertions(+), 113 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c
index eefd7119fd..84c130704a 100644
--- a/drivers/net/txgbe/base/txgbe_aml40.c
+++ b/drivers/net/txgbe/base/txgbe_aml40.c
@@ -13,6 +13,7 @@
#include "txgbe_hw.h"
#include "txgbe_aml.h"
#include "txgbe_aml40.h"
+#include "txgbe_e56.h"
void txgbe_init_ops_aml40(struct txgbe_hw *hw)
{
@@ -24,6 +25,7 @@ void txgbe_init_ops_aml40(struct txgbe_hw *hw)
/* PHY */
phy->get_media_type = txgbe_get_media_type_aml40;
+ phy->setup_link_core = txgbe_setup_phy_link_aml40;
/* LINK */
mac->init_mac_link_ops = txgbe_init_mac_link_ops_aml40;
@@ -52,6 +54,13 @@ s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw, u32 *speed,
if (link_up_wait_to_complete) {
for (i = 0; i < hw->mac.max_link_up_time; i++) {
+ if (!hw->link_valid) {
+ *link_up = false;
+
+ msleep(100);
+ continue;
+ }
+
if (!(links_reg & TXGBE_PORTSTAT_UP)) {
*link_up = false;
} else {
@@ -68,6 +77,9 @@ s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw, u32 *speed,
*link_up = false;
}
+ if (!hw->link_valid)
+ *link_up = false;
+
if (*link_up) {
if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) ==
TXGBE_CFG_PORT_ST_AML_LINK_40G)
@@ -107,20 +119,24 @@ u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw)
return txgbe_media_type_fiber_qsfp;
}
-s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw,
- u32 speed,
- bool autoneg_wait_to_complete)
+s32 txgbe_setup_phy_link_aml40(struct txgbe_hw *hw,
+ u32 speed,
+ bool autoneg_wait_to_complete,
+ bool *need_reset)
{
bool autoneg = false;
s32 status = 0;
+ s32 ret_status = 0;
u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
bool link_up = false;
+ int i;
u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
+ u32 value;
- if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
- DEBUGOUT("SFP not detected, skip setup mac link");
- return 0;
- }
+ *need_reset = false;
+
+ if (hw->phy.sfp_type == txgbe_sfp_type_not_present)
+ hw->phy.identify_sfp(hw);
/* Check to see if speed passed in is supported. */
status = hw->mac.get_link_capabilities(hw,
@@ -132,18 +148,43 @@ s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw,
if (speed == TXGBE_LINK_SPEED_UNKNOWN)
return TXGBE_ERR_LINK_SETUP;
- status = hw->mac.check_link(hw, &link_speed, &link_up,
- autoneg_wait_to_complete);
+ for (i = 0; i < 4; i++) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up)
+ break;
+ msleep(250);
+ }
if (link_speed == speed && link_up)
- return status;
+ goto out;
- if (speed & TXGBE_LINK_SPEED_40GB_FULL)
- speed = 0x20;
+ rte_spinlock_lock(&hw->phy_lock);
+ ret_status = txgbe_set_link_to_amlite(hw, speed);
+ rte_spinlock_unlock(&hw->phy_lock);
- status = hw->phy.set_link_hostif(hw, (u8)speed, autoneg, true);
+ if (ret_status == TXGBE_ERR_TIMEOUT)
+ hw->link_valid = false;
+
+ for (i = 0; i < 4; i++) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up)
+ goto out;
+ msleep(250);
+ }
- txgbe_wait_for_link_up_aml(hw, speed);
+out:
+ if (link_up) {
+ value = rd32(hw, TXGBE_PORTSTAT);
+ if (!(value & TXGBE_PORTSTAT_UP)) {
+ DEBUGOUT("MAC link 0x14404: 0x%x", value);
+ *need_reset = true;
+ value = rd32(hw, 0x110b0);
+ DEBUGOUT("MAC intr status 0x110b0: 0x%x", value);
+ }
+ } else {
+ *need_reset = true;
+ DEBUGOUT("Link reconfiguration required. Reset scheduled in 2000ms.");
+ }
return status;
}
@@ -159,6 +200,5 @@ void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw)
mac->flap_tx_laser =
txgbe_flap_tx_laser_multispeed_fiber;
- mac->setup_link = txgbe_setup_mac_link_aml40;
mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
}
diff --git a/drivers/net/txgbe/base/txgbe_aml40.h b/drivers/net/txgbe/base/txgbe_aml40.h
index f31360c899..d97654fbf8 100644
--- a/drivers/net/txgbe/base/txgbe_aml40.h
+++ b/drivers/net/txgbe/base/txgbe_aml40.h
@@ -14,7 +14,9 @@ s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw,
s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw,
u32 *speed, bool *autoneg);
u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw);
-s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw, u32 speed,
- bool autoneg_wait_to_complete);
+s32 txgbe_setup_phy_link_aml40(struct txgbe_hw *hw,
+ u32 speed,
+ bool autoneg_wait_to_complete,
+ bool *need_reset);
void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw);
#endif /* _TXGBE_AML40_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_e56.c b/drivers/net/txgbe/base/txgbe_e56.c
index e4ed1f95fc..c6fb2627d4 100644
--- a/drivers/net/txgbe/base/txgbe_e56.c
+++ b/drivers/net/txgbe/base/txgbe_e56.c
@@ -102,11 +102,29 @@ u32 txgbe_e56_tx_ffe_cfg(struct txgbe_hw *hw, u32 speed)
} else if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
+ ffe_main = S25G_TX_FFE_CFG_DAC_MAIN;
+ pre1 = S25G_TX_FFE_CFG_DAC_PRE1;
+ pre2 = S25G_TX_FFE_CFG_DAC_PRE2;
+ post = S25G_TX_FFE_CFG_DAC_POST;
+ } else {
ffe_main = S25G_TX_FFE_CFG_MAIN;
pre1 = S25G_TX_FFE_CFG_PRE1;
pre2 = S25G_TX_FFE_CFG_PRE2;
post = S25G_TX_FFE_CFG_POST;
}
+ } else if (speed == TXGBE_LINK_SPEED_40GB_FULL) {
+ ffe_main = S10G_TX_FFE_CFG_MAIN;
+ pre1 = S10G_TX_FFE_CFG_PRE1;
+ pre2 = S10G_TX_FFE_CFG_PRE2;
+ post = S10G_TX_FFE_CFG_POST;
+
+ if (hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core0 ||
+ hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core1) {
+ ffe_main = S40G_TX_FFE_CFG_MAIN;
+ pre1 = S40G_TX_FFE_CFG_PRE1;
+ pre2 = S40G_TX_FFE_CFG_PRE2;
+ post = S40G_TX_FFE_CFG_POST;
+ }
}
if (hw->phy.ffe_set) {
@@ -154,6 +172,416 @@ txgbe_e56_get_temp(struct txgbe_hw *hw, int *temp)
return 0;
}
+u32 txgbe_e56_cfg_40g(struct txgbe_hw *hw)
+{
+ u32 addr;
+ u32 rdata = 0;
+ int i;
+
+ /* CMS Config Master */
+ addr = E56G_CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDVAL_7 *)&rdata)->ana_lcpll_lf_vco_swing_ctrl_i = 0xf;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_vco_swing_ctrl_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G_CMS_ANA_OVRDVAL_9_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 0, 0x260000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_test_in_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ /* TXS Config Master */
+ for (i = 0; i < 4; i++) {
+ addr = E56PHY_TXS_TXS_CFG_1_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256, 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_WKUP_CNT_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32, 0xff);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_PIN_OVRDVAL_6_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 19, 16, 0x6);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_PIN_OVRDEN_0_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_ANA_OVRDVAL_1_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_ANA_OVRDEN_0_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ }
+ /* Setting TX FFE */
+ txgbe_e56_tx_ffe_cfg(hw, TXGBE_LINK_SPEED_40GB_FULL);
+
+ /* RXS Config master */
+ for (i = 0; i < 4; i++) {
+ addr = E56PHY_RXS_RXS_CFG_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN, 0x1fff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->prediv0 = 0xfa0;
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->target_cnt0 = 0x203a;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_range_sel0 = 0x2;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->vco_code_init = 0x7ff;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_current_boost_en0 = 0x1;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->bbcdr_current_boost0 = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK, 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK, 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK, 0xc);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK, 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK, 0x7);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_INTL_CONFIG_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_0 *)&rdata)->adc_intl2slice_delay0 = 0x5555;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_INTL_CONFIG_2_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_2 *)&rdata)->interleaver_hbw_disable0 = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH, 0x56);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH, 0x6a);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH, 0x1e8);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH, 0x78);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_2_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH, 0x100);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_3_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH, 0x4);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH, 0x37);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE, 0x38);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET, 0x34);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123, 0xa);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0, 0x9);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT, 0x1ffffea);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_2_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1,
+ S10G_PHY_RX_CTLE_TAP_FRACP1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2,
+ S10G_PHY_RX_CTLE_TAP_FRACP2);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3,
+ S10G_PHY_RX_CTLE_TAP_FRACP3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_3_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1,
+ S10G_PHY_RX_CTLE_TAPWT_WEIGHT1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2,
+ S10G_PHY_RX_CTLE_TAPWT_WEIGHT2);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3,
+ S10G_PHY_RX_CTLE_TAPWT_WEIGHT3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8,
+ 0xc);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_FFE_TRAINING_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN, 0xf9ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_IDLE_DETECT_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS3_ANA_OVRDVAL_11_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G__RXS3_ANA_OVRDVAL_11 *)&rdata)->ana_test_adc_clkgen_i = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_2_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G__RXS0_ANA_OVRDEN_2 *)&rdata)->ovrd_en_ana_test_adc_clkgen_i = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_6_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 4, 0, 0x6);
+ set_fields_e56(&rdata, 14, 13, 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I,
+ 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_15_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 2, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_17_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_3_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_14_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_4_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_EYE_SCAN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER, 0x400);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_RINGO_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 9, 4, 0x366);
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ /* PDIG Config master */
+ addr = E56PHY_PMD_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K, 0x80);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K, 0x18);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K, 0x3e);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL, 0x3);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN, 0x40);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN, 0x4bf);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN, 0xc4bf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_8_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN, 0x47ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_12_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN, 0x67ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_13_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN, 0x8001);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN, 0x8002);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN, 0x8008);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN, 0x8004);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN, 0x20c0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_18_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_29_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN, 0x3f6d);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_33_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_34_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_KRT_TFSM_CFG_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K, 0x49);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K, 0x37);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K, 0x2f);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2, 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ return 0;
+}
+
u32
txgbe_e56_cfg_25g(struct txgbe_hw *hw)
{
@@ -1298,6 +1726,46 @@ txgbe_e56_rxs_osc_init_for_temp_track_range(struct txgbe_hw *hw, u32 speed)
return status;
}
+static int txgbe_e56_set_rxs_ufine_le_max_40g(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0;
+ unsigned int rdata;
+ unsigned int ULTRAFINE_CODE;
+ int i = 0;
+ unsigned int CMVAR_UFINE_MAX = 0;
+ u32 addr;
+
+ for (i = 0; i < 4; i++) {
+ if (speed == TXGBE_LINK_SPEED_10GB_FULL || speed == TXGBE_LINK_SPEED_40GB_FULL)
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ else if (speed == TXGBE_LINK_SPEED_25GB_FULL)
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+
+ /* a. Assign software defined variables as below */
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ /* b. Perform the below logic sequence */
+ while (ULTRAFINE_CODE > CMVAR_UFINE_MAX) {
+ ULTRAFINE_CODE = ULTRAFINE_CODE - 1;
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i) = ULTRAFINE_CODE;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+
+ /* Wait until 1milliseconds or greater */
+ msleep(10);
+ }
+ }
+ return status;
+}
+
static inline
int txgbe_e56_set_rxs_ufine_le_max(struct txgbe_hw *hw, u32 speed)
{
@@ -1332,38 +1800,269 @@ int txgbe_e56_set_rxs_ufine_le_max(struct txgbe_hw *hw, u32 speed)
return status;
}
-int txgbe_e56_rx_rd_second_code(struct txgbe_hw *hw, int *SECOND_CODE)
-{
- int status = 0, i, N, median;
- unsigned int rdata;
- int array_size, RXS_BBCDR_SECOND_ORDER_ST[5];
+int txgbe_e56_rx_rd_second_code_40g(struct txgbe_hw *hw, int *SECOND_CODE, int lane)
+{
+ int status = 0, i, N, median;
+ unsigned int rdata;
+ u32 addr;
+ int array_size, RXS_BBCDR_SECOND_ORDER_ST[5];
+
+ /* Set ovrd_en=0 to read ASIC value */
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (lane * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_int_cstm_i) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ /*
+ * As status update from RXS hardware is asynchronous to read status of SECOND_ORDER,
+ * follow sequence mentioned below.
+ */
+ N = 5;
+ for (i = 0; i < N; i = i + 1) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (lane * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ RXS_BBCDR_SECOND_ORDER_ST[i] = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_int_cstm_i);
+ usec_delay(100);
+ }
+
+ /* sort array RXS_BBCDR_SECOND_ORDER_ST[i] */
+ array_size = ARRAY_SIZE(RXS_BBCDR_SECOND_ORDER_ST);
+ qsort(RXS_BBCDR_SECOND_ORDER_ST, array_size, sizeof(int), txgbe_e56_int_cmp);
+
+ median = ((N + 1) / 2) - 1;
+ *SECOND_CODE = RXS_BBCDR_SECOND_ORDER_ST[median];
+
+ return status;
+}
+
+int txgbe_e56_rx_rd_second_code(struct txgbe_hw *hw, int *SECOND_CODE)
+{
+ int status = 0, i, N, median;
+ unsigned int rdata;
+ int array_size, RXS_BBCDR_SECOND_ORDER_ST[5];
+
+
+ /* Set ovrd_en=0 to read ASIC value */
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_int_cstm_i, 0);
+
+ /*
+ * As status update from RXS hardware is asynchronous to read status
+ * of SECOND_ORDER, follow sequence mentioned below.
+ */
+ N = 5;
+ for (i = 0; i < N; i = i + 1) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ RXS_BBCDR_SECOND_ORDER_ST[i] = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_int_cstm_i);
+ usec_delay(100);
+ }
+
+ /* sort array RXS_BBCDR_SECOND_ORDER_ST[i] */
+ array_size = ARRAY_SIZE(RXS_BBCDR_SECOND_ORDER_ST);
+ qsort(RXS_BBCDR_SECOND_ORDER_ST, array_size, sizeof(int), txgbe_e56_int_cmp);
+
+ median = ((N + 1) / 2) - 1;
+ *SECOND_CODE = RXS_BBCDR_SECOND_ORDER_ST[median];
+
+ return status;
+}
+
+/*
+ * 2.3.4 RXS post CDR lock temperature tracking sequence
+ *
+ * Below sequence must be run before the temperature drifts by >5degC
+ * after the CDR locks for the first time or after the ious time this
+ * sequence was run. It is recommended to call this sequence periodically
+ * (eg: once every 100ms) or trigger sequence if the temperature drifts
+ * by >=5degC. Temperature must be read from an on-die temperature sensor.
+ */
+int txgbe_temp_track_seq_40g(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0;
+ unsigned int rdata;
+ int SECOND_CODE;
+ int COARSE_CODE;
+ int FINE_CODE;
+ int ULTRAFINE_CODE;
+
+ int CMVAR_SEC_LOW_TH;
+ int CMVAR_UFINE_MAX = 0;
+ int CMVAR_FINE_MAX;
+ int CMVAR_UFINE_UMAX_WRAP = 0;
+ int CMVAR_COARSE_MAX;
+ int CMVAR_UFINE_FMAX_WRAP = 0;
+ int CMVAR_FINE_FMAX_WRAP = 0;
+ int CMVAR_SEC_HIGH_TH;
+ int CMVAR_UFINE_MIN;
+ int CMVAR_FINE_MIN;
+ int CMVAR_UFINE_UMIN_WRAP;
+ int CMVAR_COARSE_MIN;
+ int CMVAR_UFINE_FMIN_WRAP;
+ int CMVAR_FINE_FMIN_WRAP;
+ int i;
+ u32 addr;
+ int temperature;
+
+ for (i = 0; i < 4; i++) {
+ if (speed == TXGBE_LINK_SPEED_10GB_FULL || speed == TXGBE_LINK_SPEED_40GB_FULL) {
+ CMVAR_SEC_LOW_TH = S10G_CMVAR_SEC_LOW_TH;
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ CMVAR_FINE_MAX = S10G_CMVAR_FINE_MAX;
+ CMVAR_UFINE_UMAX_WRAP = S10G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S10G_CMVAR_COARSE_MAX;
+ CMVAR_UFINE_FMAX_WRAP = S10G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S10G_CMVAR_FINE_FMAX_WRAP;
+ CMVAR_SEC_HIGH_TH = S10G_CMVAR_SEC_HIGH_TH;
+ CMVAR_UFINE_MIN = S10G_CMVAR_UFINE_MIN;
+ CMVAR_FINE_MIN = S10G_CMVAR_FINE_MIN;
+ CMVAR_UFINE_UMIN_WRAP = S10G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S10G_CMVAR_COARSE_MIN;
+ CMVAR_UFINE_FMIN_WRAP = S10G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S10G_CMVAR_FINE_FMIN_WRAP;
+ } else if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ CMVAR_SEC_LOW_TH = S25G_CMVAR_SEC_LOW_TH;
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+ CMVAR_FINE_MAX = S25G_CMVAR_FINE_MAX;
+ CMVAR_UFINE_UMAX_WRAP = S25G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S25G_CMVAR_COARSE_MAX;
+ CMVAR_UFINE_FMAX_WRAP = S25G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S25G_CMVAR_FINE_FMAX_WRAP;
+ CMVAR_SEC_HIGH_TH = S25G_CMVAR_SEC_HIGH_TH;
+ CMVAR_UFINE_MIN = S25G_CMVAR_UFINE_MIN;
+ CMVAR_FINE_MIN = S25G_CMVAR_FINE_MIN;
+ CMVAR_UFINE_UMIN_WRAP = S25G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S25G_CMVAR_COARSE_MIN;
+ CMVAR_UFINE_FMIN_WRAP = S25G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S25G_CMVAR_FINE_FMIN_WRAP;
+ } else {
+ DEBUGOUT("Error Speed\n");
+ return 0;
+ }
+ status = txgbe_e56_get_temp(hw, &temperature);
+ if (status)
+ return 0;
- /* Set ovrd_en=0 to read ASIC value */
- txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_int_cstm_i, 0);
+ hw->temperature = temperature;
- /*
- * As status update from RXS hardware is asynchronous to read status
- * of SECOND_ORDER, follow sequence mentioned below.
- */
- N = 5;
- for (i = 0; i < N; i = i + 1) {
- /* set RXS_BBCDR_SECOND_ORDER_ST[i] =
- * RXS::ANA_OVRDVAL[5]::ana_bbcdr_int_cstm_i[4:0]
+ /* Assign software defined variables as below */
+ /* a. SECOND_CODE = ALIAS::RXS::SECOND_ORDER */
+ status |= txgbe_e56_rx_rd_second_code_40g(hw, &SECOND_CODE, i);
+
+ /*
+ * b. COARSE_CODE = ALIAS::RXS::COARSE
+ * c. FINE_CODE = ALIAS::RXS::FINE
+ * d. ULTRAFINE_CODE = ALIAS::RXS::ULTRAFINE
*/
- EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
- RXS_BBCDR_SECOND_ORDER_ST[i] = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
- ana_bbcdr_int_cstm_i);
- usec_delay(100);
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ COARSE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i);
+ FINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ if (SECOND_CODE <= CMVAR_SEC_LOW_TH) {
+ if (ULTRAFINE_CODE < CMVAR_UFINE_MAX) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = ULTRAFINE_CODE + 1;
+ wr32_ephy(hw, addr, rdata);
+
+ /* Set ovrd_en=1 to override ASIC value */
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1,
+ ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else if (FINE_CODE < CMVAR_FINE_MAX) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_fine_i) = FINE_CODE + 1;
+ wr32_ephy(hw, addr, rdata);
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1,
+ ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else if (COARSE_CODE < CMVAR_COARSE_MAX) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_fine_i) = CMVAR_FINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_coarse_i) = COARSE_CODE + 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1,
+ ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else {
+ DEBUGOUT("ERROR: (SECOND_CODE <= CMVAR_SEC_LOW_TH) temperature "
+ "tracking occurs Error condition");
+ }
+ } else if (SECOND_CODE >= CMVAR_SEC_HIGH_TH) {
+ if (ULTRAFINE_CODE > CMVAR_UFINE_MIN) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = ULTRAFINE_CODE - 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1,
+ ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else if (FINE_CODE > CMVAR_FINE_MIN) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_fine_i) = FINE_CODE - 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1,
+ ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else if (COARSE_CODE > CMVAR_COARSE_MIN) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_fine_i) = CMVAR_FINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_coarse_i) = COARSE_CODE - 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1,
+ ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else {
+ DEBUGOUT("ERROR: (SECOND_CODE >= CMVAR_SEC_HIGH_TH) temperature "
+ "tracking occurs Error condition");
+ }
+ }
}
-
- /* sort array RXS_BBCDR_SECOND_ORDER_ST[i] */
- array_size = ARRAY_SIZE(RXS_BBCDR_SECOND_ORDER_ST);
- qsort(RXS_BBCDR_SECOND_ORDER_ST, array_size, sizeof(int), txgbe_e56_int_cmp);
-
- median = ((N + 1) / 2) - 1;
- *SECOND_CODE = RXS_BBCDR_SECOND_ORDER_ST[median];
-
return status;
}
@@ -1538,78 +2237,410 @@ int txgbe_temp_track_seq(struct txgbe_hw *hw, u32 speed)
PMD_DRV_LOG(ERR, "ERROR: (SECOND_CODE >= CMVAR_SEC_HIGH_TH) "
"temperature tracking occurs Error condition");
}
- }
+ }
+
+ return status;
+}
+
+static inline int
+txgbe_e56_ctle_bypass_seq(struct txgbe_hw *hw, u32 speed)
+{
+ unsigned int rdata;
+
+ /* 1. Program the following RXS registers as mentioned below. */
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+
+ /* 2. Program the following PDIG registers as mentioned below. */
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDVAL_1);
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDEN_1);
+
+ if (speed == TXGBE_LINK_SPEED_40GB_FULL) {
+ /* 1. Program the following RXS registers as mentioned below. */
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+
+ /* 2. Program the following PDIG registers as mentioned below. */
+ EPHY_RREG(E56G__PMD_RXS1_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS1_OVRDVAL_1);
+ EPHY_RREG(E56G__PMD_RXS2_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS2_OVRDVAL_1);
+ EPHY_RREG(E56G__PMD_RXS3_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS3_OVRDVAL_1);
+
+ EPHY_RREG(E56G__PMD_RXS1_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDEN_1, ovrd_en_rxs1_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDEN_1, ovrd_en_rxs1_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS1_OVRDEN_1);
+ EPHY_RREG(E56G__PMD_RXS2_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDEN_1, ovrd_en_rxs2_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDEN_1, ovrd_en_rxs2_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS2_OVRDEN_1);
+ EPHY_RREG(E56G__PMD_RXS3_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDEN_1, ovrd_en_rxs3_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDEN_1, ovrd_en_rxs3_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS3_OVRDEN_1);
+ }
+ return 0;
+}
+
+static int txgbe_e56_rxs_calib_adapt_seq_40G(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0, i, j;
+ u32 addr, timer;
+ u32 rdata = 0x0;
+ u32 bypass_ctle = true;
+
+ for (i = 0; i < 4; i++) {
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_INTL_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ if (bypass_ctle == 1)
+ txgbe_e56_ctle_bypass_seq(hw, speed);
+
+ /*
+ * 2. Follow sequence described in 2.3.2 RXS Osc Initialization for temperature tracking
+ * range here. RXS would be enabled at the end of this sequence. For the case when PAM4 KR
+ * training is not enabled (including PAM4 mode without KR training), wait until
+ * ALIAS::PDIG::CTRL_FSM_RX_ST would return RX_TRAIN_15_ST (RX_RDY_ST).
+ */
+ txgbe_e56_rxs_osc_init_for_temp_track_range(hw, speed);
+
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ timer = 0;
+ rdata = 0;
+ while (EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx0_st) != E56PHY_RX_RDY_ST ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx1_st) != E56PHY_RX_RDY_ST ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx2_st) != E56PHY_RX_RDY_ST ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx3_st) != E56PHY_RX_RDY_ST) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ return TXGBE_ERR_TIMEOUT;
+ }
+ }
+
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS1_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS2_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS3_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+
+ for (i = 0; i < 4; i++) {
+ /* 4. Disable VGA and CTLE training so they don't interfere with ADC calibration */
+ /* a. Set ALIAS::RXS::VGA_TRAIN_EN = 0b0 */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_VGA_TRAIN_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_VGA_TRAIN_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* b. Set ALIAS::RXS::CTLE_TRAIN_EN = 0b0 */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_CTLE_TRAIN_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_CTLE_TRAIN_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* 5. Perform ADC interleaver calibration */
+ /* a. Remove the OVERRIDE on ALIAS::RXS::ADC_INTL_CAL_DONE */
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ timer = 0;
+ while (((rdata >> E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O_LSB)
+ & 1) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(1000);
+
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+
+ /*
+ * 6. Perform ADC offset adaptation and ADC gain adaptation, repeat them a few
+ * times and after that keep it disabled.
+ */
+ for (j = 0; j < 16; j++) {
+ /* a. ALIAS::RXS::ADC_OFST_ADAPT_EN = 0b1 */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* b. Wait for 1ms or greater */
+ addr = E56G__PMD_RXS0_OVRDEN_2_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1,
+ rxs0_rx0_adc_ofst_adapt_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+
+ /* c. ALIAS::RXS::ADC_OFST_ADAPT_EN = 0b0 */
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ /* d. ALIAS::RXS::ADC_GAIN_ADAPT_EN = 0b1 */
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* e. Wait for 1ms or greater */
+ addr = E56G__PMD_RXS0_OVRDEN_2_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ timer = 0;
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1,
+ rxs0_rx0_adc_gain_adapt_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+
+ /* f. ALIAS::RXS::ADC_GAIN_ADAPT_EN = 0b0 */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ }
+ /* g. Repeat #a to #f total 16 times */
- return status;
-}
-static inline int
-txgbe_e56_ctle_bypass_seq(struct txgbe_hw *hw, u32 speed)
-{
- unsigned int rdata;
+ /*
+ * 7. Perform ADC interleaver adaptation for 10ms or greater,
+ * and after that disable it
+ * a. ALIAS::RXS::ADC_INTL_ADAPT_EN = 0b1
+ */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ /* b. Wait for 10ms or greater */
+ msleep(10);
- /* 1. Program the following RXS registers as mentioned below. */
- txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
- txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+ /* c. ALIAS::RXS::ADC_INTL_ADAPT_EN = 0b0 */
+ addr = E56G__PMD_RXS0_OVRDEN_2_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_2, ovrd_en_rxs0_rx0_adc_intl_adapt_en_i) = 0;
+ wr32_ephy(hw, addr, rdata);
- txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
- txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+ /*
+ * 8. Now re-enable VGA and CTLE trainings, so that it continues to adapt tracking
+ * changes in temperature or voltage
+ */
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_vga_train_en_i) = 1;
+ if (bypass_ctle == 0)
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 1;
+ wr32_ephy(hw, addr, rdata);
- /* 2. Program the following PDIG registers as mentioned below. */
- EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
- EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 0;
- EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_done_o) = 1;
- EPHY_WREG(E56G__PMD_RXS0_OVRDVAL_1);
+ addr = E56G__PMD_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_vga_train_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
- EPHY_RREG(E56G__PMD_RXS0_OVRDEN_1);
- EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 1;
- EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_done_o) = 1;
- EPHY_WREG(E56G__PMD_RXS0_OVRDEN_1);
+ rdata = 0;
+ timer = 0;
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_vga_train_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
- if (speed == TXGBE_LINK_SPEED_40GB_FULL) {
- /* 1. Program the following RXS registers as mentioned below. */
- txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
- txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
- txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
- txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
- txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
- txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
- txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
- txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
- txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
- txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
- txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
- txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+ if (bypass_ctle == 0) {
+ addr = E56G__PMD_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
- /* 2. Program the following PDIG registers as mentioned below. */
- EPHY_RREG(E56G__PMD_RXS1_OVRDVAL_1);
- EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_ctle_train_en_i) = 0;
- EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_ctle_train_done_o) = 1;
- EPHY_WREG(E56G__PMD_RXS1_OVRDVAL_1);
- EPHY_RREG(E56G__PMD_RXS2_OVRDVAL_1);
- EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_ctle_train_en_i) = 0;
- EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_ctle_train_done_o) = 1;
- EPHY_WREG(E56G__PMD_RXS2_OVRDVAL_1);
- EPHY_RREG(E56G__PMD_RXS3_OVRDVAL_1);
- EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_ctle_train_en_i) = 0;
- EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_ctle_train_done_o) = 1;
- EPHY_WREG(E56G__PMD_RXS3_OVRDVAL_1);
+ rdata = 0;
+ timer = 0;
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1,
+ rxs0_rx0_ctle_train_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+ }
+
+ /* a. Remove the OVERRIDE on ALIAS::RXS::VGA_TRAIN_EN */
+ addr = E56G__PMD_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_vga_train_en_i) = 0;
+ /* b. Remove the OVERRIDE on ALIAS::RXS::CTLE_TRAIN_EN */
+ if (bypass_ctle == 0)
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 0;
+ wr32_ephy(hw, addr, rdata);
- EPHY_RREG(E56G__PMD_RXS1_OVRDEN_1);
- EPHY_XFLD(E56G__PMD_RXS1_OVRDEN_1, ovrd_en_rxs1_rx0_ctle_train_en_i) = 1;
- EPHY_XFLD(E56G__PMD_RXS1_OVRDEN_1, ovrd_en_rxs1_rx0_ctle_train_done_o) = 1;
- EPHY_WREG(E56G__PMD_RXS1_OVRDEN_1);
- EPHY_RREG(E56G__PMD_RXS2_OVRDEN_1);
- EPHY_XFLD(E56G__PMD_RXS2_OVRDEN_1, ovrd_en_rxs2_rx0_ctle_train_en_i) = 1;
- EPHY_XFLD(E56G__PMD_RXS2_OVRDEN_1, ovrd_en_rxs2_rx0_ctle_train_done_o) = 1;
- EPHY_WREG(E56G__PMD_RXS2_OVRDEN_1);
- EPHY_RREG(E56G__PMD_RXS3_OVRDEN_1);
- EPHY_XFLD(E56G__PMD_RXS3_OVRDEN_1, ovrd_en_rxs3_rx0_ctle_train_en_i) = 1;
- EPHY_XFLD(E56G__PMD_RXS3_OVRDEN_1, ovrd_en_rxs3_rx0_ctle_train_done_o) = 1;
- EPHY_WREG(E56G__PMD_RXS3_OVRDEN_1);
}
- return 0;
+ return status;
}
static inline int
@@ -1982,20 +3013,42 @@ txgbe_e56_cfg_temp(struct txgbe_hw *hw)
return 0;
}
-static int txgbe_e56_config_rx(struct txgbe_hw *hw, u32 speed)
+static int txgbe_e56_config_rx_40G(struct txgbe_hw *hw, u32 speed)
{
s32 status;
- status = txgbe_e56_rxs_calib_adapt_seq(hw, speed);
+ status = txgbe_e56_rxs_calib_adapt_seq_40G(hw, speed);
if (status)
return status;
/* Step 2 of 2.3.4 */
- txgbe_e56_set_rxs_ufine_le_max(hw, speed);
+ txgbe_e56_set_rxs_ufine_le_max_40g(hw, speed);
/* 2.3.4 RXS post CDR lock temperature tracking sequence */
- txgbe_temp_track_seq(hw, speed);
+ txgbe_temp_track_seq_40g(hw, speed);
+
+ hw->link_valid = true;
+
+ return 0;
+}
+static int txgbe_e56_config_rx(struct txgbe_hw *hw, u32 speed)
+{
+ s32 status;
+
+ if (speed == TXGBE_LINK_SPEED_40GB_FULL) {
+ txgbe_e56_config_rx_40G(hw, speed);
+ } else {
+ status = txgbe_e56_rxs_calib_adapt_seq(hw, speed);
+ if (status)
+ return status;
+
+ /* Step 2 of 2.3.4 */
+ txgbe_e56_set_rxs_ufine_le_max(hw, speed);
+
+ /* 2.3.4 RXS post CDR lock temperature tracking sequence */
+ txgbe_temp_track_seq(hw, speed);
+ }
return 0;
}
@@ -2005,6 +3058,151 @@ static int txgbe_e56_config_rx(struct txgbe_hw *hw, u32 speed)
* Completion of RXS powerdown can be confirmed by
* observing ALIAS::PDIG::CTRL_FSM_RX_ST = POWERDN_ST
*/
+static int txgbe_e56_disable_rx40G(struct txgbe_hw *hw)
+{
+ int status = 0;
+ unsigned int rdata, timer;
+ unsigned int addr, temp;
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ /* 1. Disable OVERRIDE on below aliases */
+ /* a. ALIAS::RXS::RANGE_SEL */
+ rdata = 0x0000;
+ addr = E56G__RXS0_ANA_OVRDEN_0_ADDR + (i * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_bbcdr_osc_range_sel_i) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (i * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ /* b. ALIAS::RXS::COARSE */
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 0;
+ /* c. ALIAS::RXS::FINE */
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 0;
+ /* d. ALIAS::RXS::ULTRAFINE */
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ /* e. ALIAS::RXS::SAMP_CAL_DONE */
+ addr = E56G__PMD_RXS0_OVRDEN_0_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_0, ovrd_en_rxs0_rx0_samp_cal_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__PMD_RXS0_OVRDEN_2_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ /* f. ALIAS::RXS::ADC_OFST_ADAPT_EN */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_2, ovrd_en_rxs0_rx0_adc_ofst_adapt_en_i) = 0;
+ /* g. ALIAS::RXS::ADC_GAIN_ADAPT_EN */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_2, ovrd_en_rxs0_rx0_adc_gain_adapt_en_i) = 0;
+ /* j. ALIAS::RXS::ADC_INTL_ADAPT_EN */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_2, ovrd_en_rxs0_rx0_adc_intl_adapt_en_i) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__PMD_RXS0_OVRDEN_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ /* h. ALIAS::RXS::ADC_INTL_CAL_EN */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_adc_intl_cal_en_i) = 0;
+ /* i. ALIAS::RXS::ADC_INTL_CAL_DONE */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_adc_intl_cal_done_o) = 0;
+ /* k. ALIAS::RXS::CDR_EN */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_cdr_en_i) = 0;
+ /* l. ALIAS::RXS::VGA_TRAIN_EN */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_vga_train_en_i) = 0;
+ /* m. ALIAS::RXS::CTLE_TRAIN_EN */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 0;
+ /* p. ALIAS::RXS::RX_FETX_TRAIN_DONE */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_txffe_train_done_o) = 0;
+ /* r. ALIAS::RXS::RX_TXFFE_COEFF_CHANGE */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_txffe_coeff_change_o) = 0;
+ /* s. ALIAS::RXS::RX_TXFFE_TRAIN_ENACK */
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_txffe_train_enack_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__PMD_RXS0_OVRDEN_3_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ /* n. ALIAS::RXS::RX_FETX_MOD_TYPE */
+ /* o. ALIAS::RXS::RX_FETX_MOD_TYPE_UPDATE */
+ temp = EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_3, ovrd_en_rxs0_rx0_spareout_o);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_3, ovrd_en_rxs0_rx0_spareout_o) = temp & 0x8F;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_DIG_OVRDEN_1_ADDR + (i * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ /* q. ALIAS::RXS::SLICER_THRESHOLD_OVRD_EN */
+ EPHY_XFLD(E56G__RXS0_DIG_OVRDEN_1, top_comp_th_ovrd_en) = 0;
+ EPHY_XFLD(E56G__RXS0_DIG_OVRDEN_1, mid_comp_th_ovrd_en) = 0;
+ EPHY_XFLD(E56G__RXS0_DIG_OVRDEN_1, bot_comp_th_ovrd_en) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ /* 2. Disable pattern checker */
+ addr = E56G__RXS0_DFT_1_ADDR + (i * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_DFT_1, ber_en) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ /* 3. Disable internal serial loopback mode */
+ addr = E56G__RXS0_ANA_OVRDEN_3_ADDR + (i * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_3, ovrd_en_ana_sel_lpbk_i) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_2_ADDR + (i * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_2, ovrd_en_ana_en_adccal_lpbk_i) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ /* 4. Enable bypass of clock gates in RXS - */
+ addr = E56G__RXS0_RXS_CFG_0_ADDR + (i * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_RXS_CFG_0, train_clk_gate_bypass_en) = 0x1FFF;
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ /* 5. Disable KR training mode */
+ /* a. ALIAS::PDIG::KR_TRAINING_MODE = 0b0 */
+ addr = E56G__PMD_BASER_PMD_CONTROL_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln0) = 0;
+ EPHY_XFLD(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln1) = 0;
+ EPHY_XFLD(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln2) = 0;
+ EPHY_XFLD(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln3) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ /* 6. Disable RX to TX parallel loopback */
+ /* a. ALIAS::PDIG::RX_TO_TX_LPBK_EN = 0b0 */
+ addr = E56G__PMD_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_PMD_CFG_5, rx_to_tx_lpbk_en) = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ /*
+ * The FSM to disable RXS is present in PDIG. The FSM disables the RXS when
+ * PDIG::PMD_CFG[0]::rx_en_cfg[<lane no.>] = 0b0
+ */
+ txgbe_e56_ephy_config(E56G__PMD_PMD_CFG_0, rx_en_cfg, 0);
+
+ /* Wait RX FSM to be POWERDN_ST */
+ timer = 0;
+
+ while (EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx0_st) != 0x21 ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx1_st) != 0x21 ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx2_st) != 0x21 ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx3_st) != 0x21) {
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(100);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ DEBUGOUT("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!\n");
+ break;
+ }
+ }
+
+ return status;
+}
+
static int txgbe_e56_disable_rx(struct txgbe_hw *hw)
{
int status = 0;
@@ -2137,8 +3335,13 @@ int txgbe_e56_reconfig_rx(struct txgbe_hw *hw, u32 speed)
* 14. Do SEQ::RX_DISABLE to disable RXS. Poll ALIAS::PDIG::CTRL_FSM_RX_ST
* and confirm its value is POWERDN_ST
*/
- txgbe_e56_disable_rx(hw);
- status = txgbe_e56_config_rx(hw, speed);
+ if (hw->mac.type == txgbe_mac_aml40) {
+ txgbe_e56_disable_rx40G(hw);
+ status = txgbe_e56_config_rx_40G(hw, speed);
+ } else {
+ txgbe_e56_disable_rx(hw);
+ status = txgbe_e56_config_rx(hw, speed);
+ }
addr = E56PHY_INTR_0_ADDR;
wr32_ephy(hw, addr, E56PHY_INTR_0_IDLE_ENTRY1);
@@ -2205,6 +3408,86 @@ int txgbe_set_link_to_amlite(struct txgbe_hw *hw, u32 speed)
set_fields_e56(&value, 12, 12, 0);
wr32_epcs(hw, SR_AN_CTRL, value);
+ if (speed == TXGBE_LINK_SPEED_40GB_FULL) {
+ value = rd32_epcs(hw, SR_PCS_CTRL1);
+ set_fields_e56(&value, 5, 2, 0x3);
+ wr32_epcs(hw, SR_PCS_CTRL1, value);
+
+ value = rd32_epcs(hw, SR_PCS_CTRL2);
+ set_fields_e56(&value, 3, 0, 0x4);
+ wr32_epcs(hw, SR_PCS_CTRL2, value);
+
+ value = rd32_ephy(hw, ANA_OVRDVAL0);
+ set_fields_e56(&value, 29, 29, 0x1);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL0, value);
+
+ value = rd32_ephy(hw, ANA_OVRDVAL5);
+ set_fields_e56(&value, 24, 24, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL5, value);
+
+ value = rd32_ephy(hw, ANA_OVRDEN0);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN0, value);
+
+ value = rd32_ephy(hw, ANA_OVRDEN1);
+ set_fields_e56(&value, 30, 30, 0x1);
+ set_fields_e56(&value, 25, 25, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN1, value);
+
+ value = rd32_ephy(hw, PLL0_CFG0);
+ set_fields_e56(&value, 25, 24, 0x1);
+ set_fields_e56(&value, 17, 16, 0x3);
+ wr32_ephy(hw, PLL0_CFG0, value);
+
+ value = rd32_ephy(hw, PLL0_CFG2);
+ set_fields_e56(&value, 12, 8, 0x4);
+ wr32_ephy(hw, PLL0_CFG2, value);
+
+ value = rd32_ephy(hw, PLL1_CFG0);
+ set_fields_e56(&value, 25, 24, 0x1);
+ set_fields_e56(&value, 17, 16, 0x3);
+ wr32_ephy(hw, PLL1_CFG0, value);
+
+ value = rd32_ephy(hw, PLL1_CFG2);
+ set_fields_e56(&value, 12, 8, 0x8);
+ wr32_ephy(hw, PLL1_CFG2, value);
+
+ value = rd32_ephy(hw, PLL0_DIV_CFG0);
+ set_fields_e56(&value, 18, 8, 0x294);
+ set_fields_e56(&value, 4, 0, 0x8);
+ wr32_ephy(hw, PLL0_DIV_CFG0, value);
+
+ value = rd32_ephy(hw, DATAPATH_CFG0);
+ set_fields_e56(&value, 30, 28, 0x7);
+ set_fields_e56(&value, 26, 24, 0x5);
+ set_fields_e56(&value, 18, 16, 0x5);
+ set_fields_e56(&value, 14, 12, 0x5);
+ set_fields_e56(&value, 10, 8, 0x5);
+ wr32_ephy(hw, DATAPATH_CFG0, value);
+
+ value = rd32_ephy(hw, DATAPATH_CFG1);
+ set_fields_e56(&value, 26, 24, 0x5);
+ set_fields_e56(&value, 10, 8, 0x5);
+ set_fields_e56(&value, 18, 16, 0x5);
+ set_fields_e56(&value, 2, 0, 0x5);
+ wr32_ephy(hw, DATAPATH_CFG1, value);
+
+ value = rd32_ephy(hw, AN_CFG1);
+ set_fields_e56(&value, 4, 0, 0x2);
+ wr32_ephy(hw, AN_CFG1, value);
+
+ txgbe_e56_cfg_temp(hw);
+ txgbe_e56_cfg_40g(hw);
+
+ value = rd32_ephy(hw, PMD_CFG0);
+ set_fields_e56(&value, 21, 20, 0x3);
+ set_fields_e56(&value, 19, 12, 0xf);
+ set_fields_e56(&value, 8, 8, 0x0);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, PMD_CFG0, value);
+ }
+
if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
value = rd32_epcs(hw, SR_PCS_CTRL1);
set_fields_e56(&value, 5, 2, 5);
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 0e3d7649d8..02c3305712 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -2054,7 +2054,7 @@ txgbe_dev_stop(struct rte_eth_dev *dev)
PMD_INIT_FUNC_TRACE();
- if (hw->mac.type == txgbe_mac_aml)
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler_aml, hw);
rte_eal_alarm_cancel(txgbe_dev_detect_sfp, dev);
@@ -3206,7 +3206,7 @@ txgbe_dev_setup_link_thread_handler(void *param)
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
rte_thread_detach(rte_thread_self());
- if (hw->mac.type == txgbe_mac_aml)
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
txgbe_dev_setup_link_alarm_handler_aml(hw);
else
txgbe_dev_setup_link_alarm_handler(dev);
--
2.21.0.windows.1
^ permalink raw reply related
* [PATCH v4 11/20] net/txgbe: fix traffic class priority configuration
From: Zaiyu Wang @ 2026-05-11 10:35 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, stable, Jiawen Wu, Ferruh Yigit
In-Reply-To: <20260511103604.19724-1-zaiyuwang@trustnetic.com>
After applying the following testpmd command, 802.1Q packets with specific
priorities were not properly directed to the corresponding traffic classes:
port config 0 dcb vt off 4 pfc off
The old driver had two issues:
1. The hardware uses a 4-bit mapping register per traffic class for
priority-to-TC mapping, but the driver incorrectly configured it
as 3 bits.
2. The DCB TX configuration mistakenly wrote to the RX register.
Fix both issues, ensuring that tc-prio mapping works as expected.
Additionally, remove the stale and inconsistent TXGBE_DCBUP2TC_DEC macro as
it has no callers.
Fixes: 8bdc7882f376 ("net/txgbe: support DCB")
Cc: stable@dpdk.org
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_dcb_hw.c | 2 +-
drivers/net/txgbe/base/txgbe_regs.h | 6 ++----
drivers/net/txgbe/txgbe_rxtx.c | 7 ++-----
3 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_dcb_hw.c b/drivers/net/txgbe/base/txgbe_dcb_hw.c
index 75c91a6b6a..79e1da447b 100644
--- a/drivers/net/txgbe/base/txgbe_dcb_hw.c
+++ b/drivers/net/txgbe/base/txgbe_dcb_hw.c
@@ -154,7 +154,7 @@ s32 txgbe_dcb_config_tx_data_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,
for (i = 0; i < TXGBE_DCB_UP_MAX; i++)
reg |= TXGBE_DCBUP2TC_MAP(i, map[i]);
- wr32(hw, TXGBE_PBRXUP2TC, reg);
+ wr32(hw, TXGBE_PBTXUP2TC, reg);
/* Configure traffic class credits and priority */
for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index de382601c9..25aaf8ea68 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -503,10 +503,8 @@
#define TXGBE_PBRXCTL 0x019000
#define TXGBE_PBRXCTL_ST MS(0, 0x1)
#define TXGBE_PBRXCTL_ENA MS(31, 0x1)
-#define TXGBE_PBRXUP2TC 0x019008
#define TXGBE_PBTXUP2TC 0x01C800
-#define TXGBE_DCBUP2TC_MAP(tc, v) LS(v, 3 * (tc), 0x7)
-#define TXGBE_DCBUP2TC_DEC(tc, r) RS(r, 3 * (tc), 0x7)
+#define TXGBE_DCBUP2TC_MAP(tc, v) LS(v, 4 * (tc), 0x7)
#define TXGBE_PBRXSIZE(tc) (0x019020 + (tc) * 4)
#define TXGBE_PBRXSIZE_KB(v) LS(v, 10, 0x3FF)
@@ -1703,7 +1701,7 @@ enum txgbe_5tuple_protocol {
#define TXGBE_RDM_PF_HIDE(_i) (0x12090 + ((_i) * 4))
#define TXGBE_RPUP2TC 0x019008
-#define TXGBE_RPUP2TC_UP_SHIFT 3
+#define TXGBE_RPUP2TC_UP_SHIFT 4
#define TXGBE_RPUP2TC_UP_MASK 0x7
#define TXGBE_RDM_DCACHE_CTL 0x0120A8
diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c
index be279dc4ec..851cd122d8 100644
--- a/drivers/net/txgbe/txgbe_rxtx.c
+++ b/drivers/net/txgbe/txgbe_rxtx.c
@@ -3385,11 +3385,8 @@ txgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
queue_mapping = 0;
for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++)
- /*
- * mapping is done with 3 bits per priority,
- * so shift by i*3 each time
- */
- queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
+ queue_mapping |= ((cfg->dcb_tc[i] & TXGBE_RPUP2TC_UP_MASK) <<
+ (i * TXGBE_RPUP2TC_UP_SHIFT));
wr32(hw, TXGBE_RPUP2TC, queue_mapping);
--
2.21.0.windows.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox