* [PATCH 04/13] drivers/bus: cleanup device freeing in NXP bus
From: David Marchand @ 2026-06-11 9:45 UTC (permalink / raw)
To: dev
Cc: thomas, stephen, bruce.richardson, fengchengwen, Hemant Agrawal,
Sachin Saxena
In-Reply-To: <20260611094551.1514962-1-david.marchand@redhat.com>
Following the scan/probe refactoring, in the DPAA bus driver scan method,
the device list is empty at the time the pthread key object is allocated.
This leaves only one location that wants to release the whole device
list, so remove the dpaa_clean_device_list() helper.
Remove the same helper in FSLMC bus for consistency.
Fixes: cdefd2e980bd ("drivers/bus: initialize NXP bus specifics in scan")
Signed-off-by: David Marchand <david.marchand@redhat.com>
---
drivers/bus/dpaa/dpaa_bus.c | 15 ++-------------
drivers/bus/fslmc/fslmc_bus.c | 21 ++++++---------------
2 files changed, 8 insertions(+), 28 deletions(-)
diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c
index ee467b94d5..a439c22071 100644
--- a/drivers/bus/dpaa/dpaa_bus.c
+++ b/drivers/bus/dpaa/dpaa_bus.c
@@ -193,8 +193,6 @@ dpaa_sec_available(void)
return -1;
}
-static void dpaa_clean_device_list(void);
-
static int
dpaa_create_device_list(void)
{
@@ -336,21 +334,13 @@ dpaa_create_device_list(void)
return 0;
cleanup:
- dpaa_clean_device_list();
- return ret;
-}
-
-static void
-dpaa_clean_device_list(void)
-{
- struct rte_dpaa_device *dev = NULL;
-
RTE_BUS_FOREACH_DEV(dev, &rte_dpaa_bus) {
rte_bus_remove_device(&rte_dpaa_bus, &dev->device);
rte_intr_instance_free(dev->intr_handle);
free(dev);
- dev = NULL;
}
+
+ return ret;
}
RTE_EXPORT_INTERNAL_SYMBOL(rte_dpaa_portal_init)
@@ -699,7 +689,6 @@ rte_dpaa_bus_scan(void)
ret = pthread_key_create(&dpaa_portal_key, dpaa_portal_finish);
if (ret) {
DPAA_BUS_LOG(DEBUG, "Unable to create pthread key. (%d)", ret);
- dpaa_clean_device_list();
return ret;
}
diff --git a/drivers/bus/fslmc/fslmc_bus.c b/drivers/bus/fslmc/fslmc_bus.c
index 88511d4dc7..5870863189 100644
--- a/drivers/bus/fslmc/fslmc_bus.c
+++ b/drivers/bus/fslmc/fslmc_bus.c
@@ -43,19 +43,6 @@ rte_fslmc_get_device_count(enum rte_dpaa2_dev_type device_type)
return fslmc_bus_device_count[device_type];
}
-static void
-cleanup_fslmc_device_list(void)
-{
- struct rte_dpaa2_device *dev;
-
- RTE_BUS_FOREACH_DEV(dev, &rte_fslmc_bus) {
- rte_bus_remove_device(&rte_fslmc_bus, &dev->device);
- rte_intr_instance_free(dev->intr_handle);
- free(dev);
- dev = NULL;
- }
-}
-
static int
compare_dpaa2_devname(struct rte_dpaa2_device *dev1,
struct rte_dpaa2_device *dev2)
@@ -305,6 +292,7 @@ fslmc_dev_compare(const char *name1, const char *name2)
static int
rte_fslmc_scan(void)
{
+ struct rte_dpaa2_device *dev;
int ret;
char fslmc_dirpath[PATH_MAX];
DIR *dir;
@@ -314,7 +302,6 @@ rte_fslmc_scan(void)
char *group_name;
if (process_once) {
- struct rte_dpaa2_device *dev;
DPAA2_BUS_DEBUG("Fslmc bus already scanned. Not rescanning");
RTE_BUS_FOREACH_DEV(dev, &rte_fslmc_bus) {
@@ -416,7 +403,11 @@ rte_fslmc_scan(void)
closedir(dir);
/* Remove all devices in the list */
- cleanup_fslmc_device_list();
+ RTE_BUS_FOREACH_DEV(dev, &rte_fslmc_bus) {
+ rte_bus_remove_device(&rte_fslmc_bus, &dev->device);
+ rte_intr_instance_free(dev->intr_handle);
+ free(dev);
+ }
scan_fail:
DPAA2_BUS_DEBUG("FSLMC Bus Not Available. Skipping (%d)", ret);
/* Irrespective of failure, scan only return success */
--
2.53.0
^ permalink raw reply related
* [PATCH 03/13] bus/vdev: remove driver setting in probe
From: David Marchand @ 2026-06-11 9:45 UTC (permalink / raw)
To: dev; +Cc: thomas, stephen, bruce.richardson, fengchengwen
In-Reply-To: <20260611094551.1514962-1-david.marchand@redhat.com>
Setting the device driver field is now the responsibility of EAL
(see local_dev_probe).
Yet, because of the VDEV API, rte_vdev_init() must be updated to mark
the device as probed.
Fixes: f282771a04ef ("bus: factorize driver reference")
Signed-off-by: David Marchand <david.marchand@redhat.com>
---
drivers/bus/vdev/vdev.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/bus/vdev/vdev.c b/drivers/bus/vdev/vdev.c
index 3bddf8938c..673e8a73b2 100644
--- a/drivers/bus/vdev/vdev.c
+++ b/drivers/bus/vdev/vdev.c
@@ -188,7 +188,6 @@ vdev_probe_device(struct rte_driver *drv, struct rte_device *dev)
struct rte_vdev_driver *vdev_drv = RTE_BUS_DRIVER(drv, *vdev_drv);
const char *name;
enum rte_iova_mode iova_mode;
- int ret;
name = rte_vdev_device_name(vdev_dev);
VDEV_LOG(DEBUG, "Search driver to probe device %s", name);
@@ -200,10 +199,7 @@ vdev_probe_device(struct rte_driver *drv, struct rte_device *dev)
return -1;
}
- ret = vdev_drv->probe(vdev_dev);
- if (ret == 0)
- vdev_dev->device.driver = &vdev_drv->driver;
- return ret;
+ return vdev_drv->probe(vdev_dev);
}
/* The caller shall be responsible for thread-safe */
@@ -337,6 +333,8 @@ rte_vdev_init(const char *name, const char *args)
free(dev);
} else if (ret > 0) {
goto next_driver;
+ } else {
+ dev->device.driver = drv;
}
}
rte_spinlock_recursive_unlock(&vdev_device_list_lock);
--
2.53.0
^ permalink raw reply related
* [PATCH 02/13] dma/idxd: remove next pointer in bus specific device
From: David Marchand @ 2026-06-11 9:45 UTC (permalink / raw)
To: dev; +Cc: thomas, stephen, bruce.richardson, fengchengwen, Kevin Laatz
In-Reply-To: <20260611094551.1514962-1-david.marchand@redhat.com>
The dma/idxd devices are now stored in a list of generic rte_device
objects.
Fixes: b4f0974a995b ("bus: factorize device list")
Signed-off-by: David Marchand <david.marchand@redhat.com>
---
drivers/dma/idxd/idxd_bus.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/dma/idxd/idxd_bus.c b/drivers/dma/idxd/idxd_bus.c
index 4810d52f2a..2ec526ec09 100644
--- a/drivers/dma/idxd/idxd_bus.c
+++ b/drivers/dma/idxd/idxd_bus.c
@@ -34,7 +34,6 @@ struct dsa_wq_addr {
/** a DSA device instance */
struct rte_dsa_device {
struct rte_device device; /**< Inherit core device */
- TAILQ_ENTRY(rte_dsa_device) next; /**< next dev in list */
char wq_name[32]; /**< the workqueue name/number e.g. wq0.1 */
struct dsa_wq_addr addr; /**< Identifies the specific WQ */
--
2.53.0
^ permalink raw reply related
* [PATCH 01/13] bus: fix reference to plug callback
From: David Marchand @ 2026-06-11 9:45 UTC (permalink / raw)
To: dev; +Cc: thomas, stephen, bruce.richardson, fengchengwen
In-Reply-To: <20260611094551.1514962-1-david.marchand@redhat.com>
Update documentation and some log following the callback rename.
Fixes: 76622feba9e6 ("bus: refactor device probe")
Signed-off-by: David Marchand <david.marchand@redhat.com>
---
doc/guides/prog_guide/device_hotplug.rst | 2 +-
lib/eal/common/eal_common_dev.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/doc/guides/prog_guide/device_hotplug.rst b/doc/guides/prog_guide/device_hotplug.rst
index 9896a097f3..7eb7fbcc2b 100644
--- a/doc/guides/prog_guide/device_hotplug.rst
+++ b/doc/guides/prog_guide/device_hotplug.rst
@@ -234,7 +234,7 @@ When ``rte_dev_probe()`` is called, the following sequence occurs:
and the attach operation fails if the device is not found.
#. **Device Probe**:
- The bus's ``plug()`` method is called, which triggers the device driver's probe function.
+ The bus's ``probe_device()`` method is called, which triggers the device driver's probe function.
The probe function typically allocates device-specific resources,
maps device memory regions, initializes device hardware,
and registers the device with the appropriate subsystem (e.g., ethdev for network devices).
diff --git a/lib/eal/common/eal_common_dev.c b/lib/eal/common/eal_common_dev.c
index 48b631532a..2a2103ec57 100644
--- a/lib/eal/common/eal_common_dev.c
+++ b/lib/eal/common/eal_common_dev.c
@@ -193,7 +193,7 @@ local_dev_probe(const char *devargs, struct rte_device **new_dev)
goto err_devarg;
if (da->bus->probe_device == NULL) {
- EAL_LOG(ERR, "Function plug not supported by bus (%s)",
+ EAL_LOG(ERR, "Function probe_device not supported by bus (%s)",
da->bus->name);
ret = -ENOTSUP;
goto err_devarg;
--
2.53.0
^ permalink raw reply related
* [PATCH 00/13] Bus cleanup infrastructure and fixes
From: David Marchand @ 2026-06-11 9:45 UTC (permalink / raw)
To: dev; +Cc: thomas, stephen, bruce.richardson, fengchengwen
This is a followup of the previous bus refactoring.
See https://inbox.dpdk.org/dev/CAJFAV8zvFpLwz8SY8DUUezyJyM43eRZ17Yj30ex808eHC4ZE=g@mail.gmail.com/.
This series refactors the bus cleanup infrastructure to reduce code
duplication and fix resource leaks in several bus drivers.
It should address the leak Thomas pointed at.
The first part of the series (patches 1-8) addresses several bugs and
inconsistencies:
- Documentation and log message inconsistencies from earlier bus
refactoring
- Device list management issues in dma/idxd and bus/vdev
- Resource leaks in PCI and VMBUS bus cleanup (mappings and interrupts)
- Simplified device freeing in NXP buses (DPAA and FSLMC)
- Deferred interrupt allocation to probe time (NXP buses, VMBUS)
The core infrastructure changes (patches 9-10) introduce the generic
cleanup framework:
- Refactors unplug operations to be the counterpart of probe_device
- Implements rte_bus_generic_cleanup() to centralize cleanup logic
- Adds .free_device operation to struct rte_bus
- Adds compile-time verification that rte_device is at offset 0
The final patches (11-13) convert remaining buses to use the generic
cleanup helper:
- DPAA bus: add unplug support
- VMBUS bus: switch to embedded device name and add unplug support
After this series, most buses use the generic cleanup helper, eliminating
duplicated code and ensuring consistent cleanup behavior across the
codebase.
--
David Marchand
David Marchand (13):
bus: fix reference to plug callback
dma/idxd: remove next pointer in bus specific device
bus/vdev: remove driver setting in probe
drivers/bus: cleanup device freeing in NXP bus
drivers/bus: allocate interrupt during probing in NXP bus
bus/pci: fix mapping leak in bus cleanup
bus/vmbus: fix interrupt leak in cleanup
bus/vmbus: allocate interrupt during probing
bus: align unplug with device probe
bus: implement cleanup in EAL
bus/dpaa: support unplug
bus/vmbus: store name in bus specific device
bus/vmbus: support unplug
doc/guides/prog_guide/device_hotplug.rst | 20 +++--
doc/guides/rel_notes/release_26_07.rst | 8 ++
drivers/bus/auxiliary/auxiliary_common.c | 56 +++-----------
drivers/bus/cdx/cdx.c | 31 ++------
drivers/bus/dpaa/dpaa_bus.c | 96 ++++++++++--------------
drivers/bus/fslmc/fslmc_bus.c | 55 ++++++--------
drivers/bus/ifpga/ifpga_bus.c | 65 ++++------------
drivers/bus/pci/pci_common.c | 69 +++--------------
drivers/bus/platform/platform.c | 28 ++-----
drivers/bus/uacce/uacce.c | 61 ++-------------
drivers/bus/vdev/vdev.c | 71 ++++++------------
drivers/bus/vmbus/bus_vmbus_driver.h | 1 +
drivers/bus/vmbus/linux/vmbus_bus.c | 16 +---
drivers/bus/vmbus/vmbus_common.c | 56 ++++++++------
drivers/dma/idxd/idxd_bus.c | 3 +-
lib/eal/common/eal_common_bus.c | 33 +++++++-
lib/eal/common/eal_common_dev.c | 10 ++-
lib/eal/include/bus_driver.h | 42 ++++++++++-
18 files changed, 268 insertions(+), 453 deletions(-)
--
2.53.0
^ permalink raw reply
* Technical board meeting minutes for June 10th 2026
From: Maxime Coquelin @ 2026-06-11 9:30 UTC (permalink / raw)
To: dev, DPDK Techboard
Attendees:
========
Maxime Coquelin (Chair)
Thomas Monjalon
Bruce Richardson
Stephen Hemminger
Konstantin Ananyev
Aaron Conole
Jerin Jacob
Hemant Agrawal
Morten Brørup
Topics:
======
* Security reports (Thomas)
- Discussion on the CVE filing process using Red Hat as CNA.
- Maxime will file CVEs for vhost-related vulnerabilities.
- Need to identify who handles CVEs for other components (e.g., crypto).
- 10 security reports on Marvell drivers; 5-6 already fixed as bugs.
* Jerin to follow up with Akhil to reply to reporters.
* Discussion on distinguishing bugs vs. security vulnerabilities.
- AI-generated security reports are becoming common.
* Aaron suggested treating AI-detected issues as public since
anyone can run AI tools.
* Stephen noted duplicate reports for already-fixed issues.
- Vote: Create a Slack channel for security coordination.
* Members: Techboard members, release maintainers, and component
maintainers as needed.
* Vote passed.
* Next Step: Thomas will create the Slack channel.
* Loongarch Lab (Thomas)
- Lab was producing systematic failures and erratic results.
- Thomas disabled access to test-report mailing list (reports now in
moderation queue).
- Next Step: Aaron will raise the issue at the DPDK CI meeting to
coordinate with Loongson.
* New PTP example (Thomas)
- Thomas merged a PTP relay example (ptp_tap_relay_software) without
prior Techboard approval.
- Concern about naming inconsistency with existing PTP client example.
- Stephen will review the example and consider renaming for consistency.
* Release update (Thomas)
- BPF patches from Marat Khalili have compilation failures when
applying patch-by-patch.
* Marat will fix the bisect issue.
- Ring library patches from Stephen also have compilation failures;
Thomas will send details.
- Power library patches still to be reviewed for RC1.
^ permalink raw reply
* [PATCH v4] net/mlx5: fix counter TAILQ race between free and query callback
From: Linhu Li @ 2026-06-11 7:51 UTC (permalink / raw)
To: dev; +Cc: stable, dsosnowski, Linhu Li
In-Reply-To: <20260604101112.72177-1-lilinhu618@gmail.com>
flow_dv_counter_free() inserts counters into
pool->counters[pool->query_gen] under pool->csl. Meanwhile,
mlx5_flow_async_pool_query_handle() moves counters from
pool->counters[query_gen ^ 1] to the global free list via
TAILQ_CONCAT while holding only cmng->csl, not pool->csl.
The comment in flow_dv_counter_free() claims the lock is not needed
because the query callback and the release function operate on
different lists. That holds only if the free path always observes
the up-to-date query_gen. It can be violated:
1. A counter free thread (non-PMD, e.g. OVS offload thread) reads
pool->query_gen == 0 and is about to insert into counters[0].
2. The free thread is preempted by the OS scheduler; it is a regular
pthread, not pinned to a core.
3. The eal-intr-thread alarm fires: query_gen++ (now 1) and the async
query is sent.
4. Hardware completes the query and the callback runs TAILQ_CONCAT on
counters[0] (= query_gen ^ 1).
5. The free thread resumes and runs TAILQ_INSERT_TAIL on counters[0]
concurrently with step 4 on another core.
Because the two paths take different locks, TAILQ_INSERT_TAIL and
TAILQ_CONCAT run concurrently on the same list with no synchronization
and corrupt it: the pool-local list ends up with a NULL head but a
dangling tqh_last, and the global free list tail no longer points to
the real tail. The just-freed counter and every counter inserted
afterwards become unreachable and are leaked.
Non-PMD threads can be preempted for hundreds of microseconds under
CPU pressure, which is well within the async query round-trip time,
so the window is reachable in practice.
Fix it by taking pool->csl in the query completion callback before
operating on pool->counters[query_gen], serializing the CONCAT with
any concurrent INSERT. The lock is taken once per pool per query
completion in the eal-intr-thread context, not on the datapath, so
the cost is negligible. Lock order is pool->csl then cmng->csl,
matching all other sites.
Also handle the error path: previously the counters accumulated in
pool->counters[query_gen] were abandoned when a query failed. Move
them back to the global free list to avoid a leak on persistent
query failures.
Fixes: ac79183dc6f7 ("net/mlx5: optimize free counter lookup")
Cc: stable@dpdk.org
Signed-off-by: Linhu Li <lilinhu618@gmail.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
doc/guides/rel_notes/release_26_07.rst | 21 +++++++++++++++++
drivers/net/mlx5/mlx5_flow.c | 31 ++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/doc/guides/rel_notes/release_26_07.rst b/doc/guides/rel_notes/release_26_07.rst
index b8a3e2ced9..30a9564884 100644
--- a/doc/guides/rel_notes/release_26_07.rst
+++ b/doc/guides/rel_notes/release_26_07.rst
@@ -153,6 +153,27 @@ ABI Changes
* No ABI change that would break compatibility with 25.11.
+Fixed Issues
+------------
+
+.. This section should contain fixed issues in this release. Sample format:
+
+ * **Add a title in the past tense with a full stop.**
+
+ Add a short 1-2 sentence description of the fix in the past tense.
+
+ This section is a comment. Do not overwrite or remove it.
+ Also, make sure to start the actual text at the margin.
+ =======================================================
+
+* **net/mlx5: Fixed counter TAILQ race between free and query callback.**
+
+ Fixed a race condition where concurrent counter free operations and async
+ query completions could corrupt the counter free list, causing counter leaks.
+ The issue occurred when non-PMD threads were preempted between reading
+ ``query_gen`` and inserting into the counter list.
+
+
Known Issues
------------
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 915ea29a5a..2f785d58ec 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -9893,6 +9893,13 @@ void
mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
uint64_t async_id, int status)
{
+ /*
+ * Handle async counter pool query completion.
+ * query_gen is flipped each round: freed counters go into [query_gen],
+ * while this callback moves [query_gen ^ 1] to the global free list.
+ * pool->csl must be held when operating on pool->counters[] to serialize
+ * with concurrent free-path insertions.
+ */
struct mlx5_flow_counter_pool *pool =
(struct mlx5_flow_counter_pool *)(uintptr_t)async_id;
struct mlx5_counter_stats_raw *raw_to_free;
@@ -9904,6 +9911,21 @@ mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
if (unlikely(status)) {
raw_to_free = pool->raw_hw;
+ /*
+ * The query failed, so the freed counters accumulated
+ * in the old-gen list would otherwise be stranded.
+ * Move them back to the global free list. This is safe
+ * for both transient and persistent failures: the
+ * counters are still valid and can be reused.
+ */
+ if (!TAILQ_EMPTY(&pool->counters[query_gen])) {
+ rte_spinlock_lock(&pool->csl);
+ rte_spinlock_lock(&cmng->csl[cnt_type]);
+ TAILQ_CONCAT(&cmng->counters[cnt_type],
+ &pool->counters[query_gen], next);
+ rte_spinlock_unlock(&cmng->csl[cnt_type]);
+ rte_spinlock_unlock(&pool->csl);
+ }
} else {
raw_to_free = pool->raw;
if (pool->is_aged)
@@ -9913,11 +9935,20 @@ mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
rte_spinlock_unlock(&pool->sl);
/* Be sure the new raw counters data is updated in memory. */
rte_io_wmb();
+ /*
+ * A counter free thread may have read a stale query_gen
+ * before the generation was flipped and could still be
+ * inserting into this same old-gen list. Hold pool->csl to
+ * serialize TAILQ_CONCAT with that TAILQ_INSERT_TAIL and
+ * avoid corrupting the list.
+ */
if (!TAILQ_EMPTY(&pool->counters[query_gen])) {
+ rte_spinlock_lock(&pool->csl);
rte_spinlock_lock(&cmng->csl[cnt_type]);
TAILQ_CONCAT(&cmng->counters[cnt_type],
&pool->counters[query_gen], next);
rte_spinlock_unlock(&cmng->csl[cnt_type]);
+ rte_spinlock_unlock(&pool->csl);
}
}
LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, raw_to_free, next);
--
2.39.3 (Apple Git-146)
^ permalink raw reply related
* Re: [PATCH] gpu/metax: add new driver for Metax GPU
From: Thomas Monjalon @ 2026-06-11 9:17 UTC (permalink / raw)
To: 许玲燕; +Cc: dev, eagostini, 王冬冬
In-Reply-To: <f4c779a6-8bff-4fda-bf76-6ddc3df6d4af.lingyan.xu@metax-tech.com>
11/06/2026 09:10:
> Both libmcruntime.so and the corresponding gdrapi libraries
> are proprietary user-space libraries provided by Metax.
> They are not upstreamed to the DPDK mainline repository.
> However, please rest assured that the current patch interacts
> with them via standard dlopen (dynamic loading) at runtime.
> We do not link directly against their source code
> or require them as hard build-time dependencies.
> Therefore, this approach will not introduce any additional
> compilation dependencies or licensing issues to the DPDK main tree.
What about the kernel dependency?
Are libraries and kernel module freely available for download?
Can you provide a link?
^ permalink raw reply
* Re: [PATCH v3 01/10] eal: add interface to check if lcore is EAL managed
From: Thomas Monjalon @ 2026-06-11 9:10 UTC (permalink / raw)
To: lihuisong (C)
Cc: anatoly.burakov, sivaprasad.tummala, dev, stephen, fengchengwen,
yangxingui, zhanjie9
In-Reply-To: <e616b775-d447-47c3-bc79-e67b2efad636@huawei.com>
11/06/2026 08:16, lihuisong (C):
> On 6/11/2026 7:28 AM, Thomas Monjalon wrote:
> > 22/05/2026 06:11, Huisong Li:
> >> Add a new helper function rte_lcore_is_eal_managed() to determine
> >> if a logical core is managed by EAL.
> >>
> >> This interface returns true if the lcore role is either ROLE_RTE
> >> (standard worker/main cores) or ROLE_SERVICE (service cores).
> > [...]
> >> +RTE_EXPORT_EXPERIMENTAL_SYMBOL(rte_lcore_is_eal_managed, 26.07)
> >> +int rte_lcore_is_eal_managed(unsigned int lcore_id)
> >> +{
> >> + struct rte_config *cfg = rte_eal_get_configuration();
> >> +
> >> + if (lcore_id >= RTE_MAX_LCORE)
> >> + return 0;
> >> + return cfg->lcore_role[lcore_id] == ROLE_RTE ||
> >> + cfg->lcore_role[lcore_id] == ROLE_SERVICE;
> >> +}
> > I'm not sure about adding this function in the API.
> > We already have rte_eal_lcore_role()
> > and I feel having this explicit ROLE_RTE || ROLE_SERVICE
> > in the code where needed may be less confusing.
>
> Ack.
>
> >
> > Note: we should prefix these constants with RTE_LCORE_
>
> Yeah, it's good.
>
> This will break API. And we can do this in 26.11.
We can keep the old names as aliases.
Better to not break the API, even in 26.11.
We could decide later, after some time, to remove the aliases.
^ permalink raw reply
* [DPDK/core Bug 1954] [dpdk26.07-rc1] DPDK build failed with EXTRA_CFLAGS='-O1' on Redhat9.6 and Ubuntu26.04
From: bugzilla @ 2026-06-11 9:09 UTC (permalink / raw)
To: dev
http://bugs.dpdk.org/show_bug.cgi?id=1954
Bug ID: 1954
Summary: [dpdk26.07-rc1] DPDK build failed with
EXTRA_CFLAGS='-O1' on Redhat9.6 and Ubuntu26.04
Product: DPDK
Version: 26.07
Hardware: All
OS: All
Status: UNCONFIRMED
Severity: normal
Priority: Normal
Component: core
Assignee: dev@dpdk.org
Reporter: daxuex.gao@intel.com
Target Milestone: ---
[Environment]
DPDK version:
commit c429b06df56788795f886eca748420e2248da784 (HEAD -> main, tag: v26.07-rc1,
origin/main, origin/HEAD)
OS: (RHEL9.6/5.14.0-570.12.1.el9_6.x86_64)/(Ubuntu26.04/7.0.0-14-generic)
Compiler: gcc (GCC) 11.5.0 20240719 (Red Hat 11.5.0-5)/gcc (Ubuntu
15.2.0-16ubuntu1) 15.2.0
[Test Setup]
# build cmd:
CC=gcc meson --optimization=1 --werror -Dlibdir=lib --default-library=static
x86_64-native-linuxapp-gcc
ninja -C x86_64-native-linuxapp-gcc
[Output]
Found ninja-1.10.2.git.kitware.jobserver-1 at /usr/local/bin/ninja
Cleaning... 0 files.
[11/3422] Compiling C object
lib/librte_eal.a.p/eal_common_eal_common_tailqs.c.o
FAILED: lib/librte_eal.a.p/eal_common_eal_common_tailqs.c.o
gcc -Ilib/librte_eal.a.p -Ilib -I../lib -Ilib/eal/common -I../lib/eal/common
-I. -I.. -Iconfig -I../config -Ilib/eal/include -I../lib/eal/include
-Ilib/eal/linux/include -I../lib/eal/linux/include -Ilib/eal/x86/include
-I../lib/eal/x86/include -I../kernel/linux -Ilib/eal -I../lib/eal -Ilib/kvargs
-I../lib/kvargs -Ilib/log -I../lib/log -Ilib/metrics -I../lib/metrics
-Ilib/telemetry -I../lib/telemetry -Ilib/argparse -I../lib/argparse
-fdiagnostics-color=always -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra
-Werror -std=c11 -O1 -include rte_config.h -Wvla -Wcast-qual -Wdeprecated
-Wformat -Wformat-nonliteral -Wformat-security -Wmissing-declarations
-Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith
-Wshadow -Wsign-compare -Wstrict-prototypes -Wundef -Wwrite-strings
-Wno-packed-not-aligned -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC
-march=native -mrtm -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API
'-DABI_VERSION="26.1"' -DRTE_EAL_PTHREAD_ATTR_SETAFFINITY_NP
-DRTE_LOG_DEFAULT_LOGTYPE=lib.eal -MD -MQ
lib/librte_eal.a.p/eal_common_eal_common_tailqs.c.o -MF
lib/librte_eal.a.p/eal_common_eal_common_tailqs.c.o.d -o
lib/librte_eal.a.p/eal_common_eal_common_tailqs.c.o -c
../lib/eal/common/eal_common_tailqs.c
In file included from ../lib/eal/common/eal_common_tailqs.c:13:
../lib/eal/common/eal_common_tailqs.c: In function ‘rte_eal_tailq_update’:
../lib/eal/include/rte_string_fns.h:63:24: error: ‘snprintf’ output may be
truncated before the last format character [-Werror=format-truncation=]
63 | return (size_t)snprintf(dst, size, "%s", src);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../lib/eal/include/rte_string_fns.h:63:24: note: ‘snprintf’ output between 1
and 32 bytes into a destination of size 31
cc1: all warnings being treated as errors
[22/3422] Compiling C object lib/librte_eal.a.p/eal_common_rte_service.c.o
ninja: build stopped: subcommand failed.
[Expected Result]
Build Passed
[Regression]
Is this issue a regression: (Y/N)N
First bad commit:
de2604d55cb7098a941db696248c4d4d00abff43 is the first bad commit
commit de2604d55cb7098a941db696248c4d4d00abff43 (HEAD)
Author: Stephen Hemminger <stephen@networkplumber.org>
Date: Wed Jan 28 17:41:20 2026 -0800
lib: enable format overflow warnings
Enable compiler checking of format overflow.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
lib/meson.build | 4 ----
1 file changed, 4 deletions(-)
--
You are receiving this mail because:
You are the assignee for the bug.
^ permalink raw reply
* RE: [PATCH v6] net/iavf: fix duplicate VF reset during PF reset recovery
From: Loftus, Ciara @ 2026-06-11 8:52 UTC (permalink / raw)
To: Mandal, Anurag, dev@dpdk.org
Cc: Richardson, Bruce, Medvedkin, Vladimir, stable@dpdk.org
In-Reply-To: <20260610154306.371431-1-anurag.mandal@intel.com>
> Subject: [PATCH v6] net/iavf: fix duplicate VF reset during PF reset recovery
>
> During PF initiated reset recovery, iavf_dev_close() sends an
> extra 'VIRTCHNL_OP_RESET_VF' while recovery is already in progress.
> That second reset can leave PF/VF virtchnl state inconsistent and
> cause 'VIRTCHNL_OP_CONFIG_VSI_QUEUES' to fail with 'ERR_PARAM' after
> ToR link flap/power-cycle, leaving the VF unable to recover.
> This results in connection loss.
>
> This patch introduces a new flag 'pf_reset_in_progress', which
> is set only when iavf_handle_hw_reset() is entered for a
> PF-initiated reset (vf_initiated_reset is false), and
> it is cleared on exit.
> The aforesaid flag is used to prevent sending close-time VF
> reset and related close-time virtchnl operation messages to the
> AdminQ when PF triggered reset recovery is set.
> This is done to avoid duplicate VF reset requests while preserving
> normal behavior for application-driven close or VF-initiated reinit.
>
> Fixes: 675a104e2e94 ("net/iavf: fix abnormal disable HW interrupt")
> Fixes: b34fe66ea893 ("net/iavf: delay VF reset command")
> Fixes: 5e03e316c753 ("net/iavf: handle virtchnl event message without
> interrupt")
> Cc: stable@dpdk.org
>
> Signed-off-by: Anurag Mandal <anurag.mandal@intel.com>
Thanks Anurag.
Acked-by: Ciara Loftus <ciara.loftus@intel.com>
> ---
> V6: Addressed Ciara Loftus's review comments
> - changed to concise relase note
> - removed unwarranted comment
> - added proper comments in two places
> - aligned commits with latest 'next-net-intel-for-next-net' branch
> V5: Addressed Ciara Loftus's review comments
> - added separate flag for PF initiated reset recovery
> V4: Addressed Ciara Loftus's review comments
> - split VF reset from other code changes
> V3: Addressed latest ai-code-review comments
> V2: Addressed ai-code-review comments
>
^ permalink raw reply
* [v1] crypto/qat: require IPsec MB for HMAC precomputes
From: Emma Finn @ 2026-06-11 8:52 UTC (permalink / raw)
To: Kai Ji; +Cc: dev, Emma Finn
IPsec MB library (v1.4.0+) is now required for HMAC precomputes as
OpenSSL 3.0 removed SHA*_Transform APIs. OpenSSL remains optional
for DOCSIS BPI cipher fallback via EVP API.
On x86: IPsec MB required, OpenSSL optional (DOCSIS fallback)
On ARM: IPsec MB required, OpenSSL required (DOCSIS support)
Signed-off-by: Emma Finn <emma.finn@intel.com>
---
doc/guides/cryptodevs/qat.rst | 28 +-
drivers/common/qat/meson.build | 69 +++--
drivers/crypto/qat/qat_sym_session.c | 412 +--------------------------
3 files changed, 74 insertions(+), 435 deletions(-)
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 0c2b85444e..4e60e8343c 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -352,15 +352,25 @@ To use this feature the user must set the devarg on process start as a device ad
-a 03:01.1,qat_sym_cipher_crc_enable=1
-Running QAT PMD with Intel IPsec MB library for symmetric precomputes function
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The QAT PMD uses Intel IPsec MB library for partial hash calculation
-in symmetric precomputes function by default,
-the minimum required version of IPsec MB library is v1.4.
-If this version of IPsec is not met, it will fallback to use OpenSSL.
-ARM will always default to using OpenSSL
-as ARM IPsec MB does not support the necessary algorithms.
+Running QAT PMD with Intel IPsec MB library
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The QAT PMD requires IPsec MB library for HMAC partial hash calculation
+in symmetric precomputes function. OpenSSL 3.0+ removed the low-level SHA*_Transform APIs
+that were previously used for HMAC precomputes.
+
+**On x86 platforms:**
+
+* Intel IPsec MB library (v1.4.0+) is required for HMAC precomputes
+* OpenSSL (3.0+) is optional for DOCSIS BPI cipher fallback
+
+**On ARM platforms:**
+
+* ARM IPsec MB library from ``gitlab.arm.com/arm-reference-solutions/ipsec-mb``
+ is required for HMAC precomputes.
+* OpenSSL (3.0+) is required for DOCSIS BPI cipher algorithms. ARM IPsec MB does not
+ implement CFB-one-byte cipher modes needed for DOCSIS. Without OpenSSL, DOCSIS
+ algorithms will not be available on ARM.
Device and driver naming
diff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build
index 31e06f4376..4f516dea2a 100644
--- a/drivers/common/qat/meson.build
+++ b/drivers/common/qat/meson.build
@@ -27,47 +27,58 @@ if disable_drivers.contains(qat_compress_path)
'Explicitly disabled via build config')
endif
-libcrypto = dependency('libcrypto', required: false, method: 'pkg-config')
+# IPsec MB is REQUIRED for HMAC precomputes (no OpenSSL 3.0 alternative)
+# OpenSSL is OPTIONAL for DOCSIS BPI cipher fallback
+IMB_required_ver = '1.4.0'
if arch_subdir == 'arm'
- if libcrypto.found()
- ext_deps += libcrypto
- dpdk_conf.set('RTE_QAT_OPENSSL', true)
+ IMB_header = '#include<ipsec-mb.h>'
+else
+ IMB_header = '#include<intel-ipsec-mb.h>'
+endif
+
+# Check for IPsec MB library (required)
+libipsecmb = cc.find_library('IPSec_MB', required: false)
+if libipsecmb.found() and cc.links(
+ 'int main(void) {return 0;}', dependencies: libipsecmb)
+ imb_ver = cc.get_define('IMB_VERSION_STR',
+ prefix : IMB_header).split('"')[1]
+
+ if (imb_ver.version_compare('>=' + IMB_required_ver))
+ ext_deps += libipsecmb
+ dpdk_conf.set('RTE_QAT_IPSECMB', true)
else
qat_crypto = false
dpdk_drvs_disabled += qat_crypto_path
set_variable('drv_' + qat_crypto_path.underscorify() + '_disable_reason',
- 'missing dependency for Arm, libcrypto')
+ 'IPSec_MB version >= @0@ is required, found version @1@'.format(
+ IMB_required_ver, imb_ver))
endif
else
- IMB_required_ver = '1.4.0'
- IMB_header = '#include<intel-ipsec-mb.h>'
- libipsecmb = cc.find_library('IPSec_MB', required: false)
- if libipsecmb.found() and cc.links(
- 'int main(void) {return 0;}', dependencies: libipsecmb)
- # version comes with quotes, so we split based on " and take the middle
- imb_ver = cc.get_define('IMB_VERSION_STR',
- prefix : IMB_header).split('"')[1]
+ qat_crypto = false
+ dpdk_drvs_disabled += qat_crypto_path
+ set_variable('drv_' + qat_crypto_path.underscorify() + '_disable_reason',
+ 'missing required dependency, libIPSec_MB >= @0@'.format(IMB_required_ver))
+endif
- if (imb_ver.version_compare('>=' + IMB_required_ver))
- ext_deps += libipsecmb
- elif libcrypto.found()
- ext_deps += libcrypto
- dpdk_conf.set('RTE_QAT_OPENSSL', true)
- else
- qat_crypto = false
- dpdk_drvs_disabled += qat_crypto_path
- set_variable('drv_' + qat_crypto_path.underscorify() + '_disable_reason',
- 'missing dependency, libipsecmb or libcrypto')
- endif
- elif libcrypto.found()
+# Check for OpenSSL (optional, for DOCSIS BPI cipher fallback)
+openssl_required_ver = '3.0.0'
+if qat_crypto
+ libcrypto = dependency('libcrypto', required: false, method: 'pkg-config', version: '>= ' + openssl_required_ver)
+ if libcrypto.found()
ext_deps += libcrypto
dpdk_conf.set('RTE_QAT_OPENSSL', true)
+ if arch_subdir == 'arm'
+ message('QAT: Using OpenSSL @0@ for DOCSIS on ARM'.format(libcrypto.version()))
+ else
+ message('QAT: OpenSSL @0@ available for DOCSIS fallback'.format(libcrypto.version()))
+ endif
else
- qat_crypto = false
- dpdk_drvs_disabled += qat_crypto_path
- set_variable('drv_' + qat_crypto_path.underscorify() + '_disable_reason',
- 'missing dependency, libipsecmb or libcrypto')
+ if arch_subdir == 'arm'
+ warning('QAT: OpenSSL >= @0@ not found - DOCSIS algorithms will not be available on ARM'.format(openssl_required_ver))
+ else
+ message('QAT: OpenSSL >= @0@ not found - DOCSIS will use IPsec MB only'.format(openssl_required_ver))
+ endif
endif
endif
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index ff01db4372..8be8802e8d 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -2,19 +2,18 @@
* Copyright(c) 2015-2022 Intel Corporation
*/
-#define OPENSSL_API_COMPAT 0x10100000L
-
-#ifdef RTE_QAT_OPENSSL
-#include <openssl/sha.h> /* Needed to calculate pre-compute values */
-#include <openssl/aes.h> /* Needed to calculate pre-compute values */
-#include <openssl/md5.h> /* Needed to calculate pre-compute values */
-#include <openssl/evp.h> /* Needed for bpi runt block processing */
-#endif
-
-#ifndef RTE_QAT_OPENSSL
-#ifndef RTE_ARCH_ARM
+/* IPsec MB is required for HMAC precomputes (OpenSSL 3.0 removed Transform APIs)
+ * OpenSSL is optional for DOCSIS BPI cipher fallback
+ */
+#ifdef RTE_ARCH_ARM
+#include <ipsec-mb.h>
+#else
#include <intel-ipsec-mb.h>
#endif
+
+#ifdef RTE_QAT_OPENSSL
+#define OPENSSL_API_COMPAT 0x30000000L
+#include <openssl/evp.h> /* For DOCSIS BPI cipher fallback */
#endif
#include <rte_memcpy.h>
@@ -38,9 +37,8 @@
static OSSL_PROVIDER * legacy_lib;
static OSSL_PROVIDER *default_lib;
-/* Some cryptographic algorithms such as MD and DES are now considered legacy
- * and not enabled by default in OpenSSL 3.0. Load up lagacy provider as MD5
- * DES are needed in QAT pre-computes and secure session creation.
+/* DES is considered legacy and not enabled by default in OpenSSL 3.0.
+ * Load legacy provider for DES-DOCSISBPI cipher fallback support.
*/
static int ossl_legacy_provider_load(void)
{
@@ -1412,339 +1410,9 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
#define HMAC_OPAD_VALUE 0x5c
#define HASH_XCBC_PRECOMP_KEY_NUM 3
-#ifdef RTE_QAT_OPENSSL
-static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)
-{
- SHA_CTX ctx;
-
- if (!SHA1_Init(&ctx))
- return -EFAULT;
- SHA1_Transform(&ctx, data_in);
- rte_memcpy(data_out, &ctx, SHA_DIGEST_LENGTH);
- return 0;
-}
-
-static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)
-{
- SHA256_CTX ctx;
-
- if (!SHA224_Init(&ctx))
- return -EFAULT;
- SHA256_Transform(&ctx, data_in);
- rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
- return 0;
-}
-
-static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
-{
- SHA256_CTX ctx;
-
- if (!SHA256_Init(&ctx))
- return -EFAULT;
- SHA256_Transform(&ctx, data_in);
- rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
- return 0;
-}
-
-static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
-{
- SHA512_CTX ctx;
-
- if (!SHA384_Init(&ctx))
- return -EFAULT;
- SHA512_Transform(&ctx, data_in);
- rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
- return 0;
-}
-
-static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
-{
- SHA512_CTX ctx;
-
- if (!SHA512_Init(&ctx))
- return -EFAULT;
- SHA512_Transform(&ctx, data_in);
- rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
- return 0;
-}
-
-static int partial_hash_md5(uint8_t *data_in, uint8_t *data_out)
-{
- MD5_CTX ctx;
-
- if (!MD5_Init(&ctx))
- return -EFAULT;
- MD5_Transform(&ctx, data_in);
- rte_memcpy(data_out, &ctx, MD5_DIGEST_LENGTH);
-
- return 0;
-}
-
-static void aes_cmac_key_derive(uint8_t *base, uint8_t *derived)
-{
- int i;
-
- derived[0] = base[0] << 1;
- for (i = 1; i < ICP_QAT_HW_AES_BLK_SZ ; i++) {
- derived[i] = base[i] << 1;
- derived[i - 1] |= base[i] >> 7;
- }
-
- if (base[0] & 0x80)
- derived[ICP_QAT_HW_AES_BLK_SZ - 1] ^= QAT_AES_CMAC_CONST_RB;
-}
-
-static int
-partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
- uint8_t *data_in, uint8_t *data_out)
-{
- int digest_size;
- uint8_t digest[qat_hash_get_digest_size(
- ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
- uint32_t *hash_state_out_be32;
- uint64_t *hash_state_out_be64;
- int i;
-
- /* Initialize to avoid gcc warning */
- memset(digest, 0, sizeof(digest));
-
- digest_size = qat_hash_get_digest_size(hash_alg);
- if (digest_size <= 0)
- return -EFAULT;
-
- hash_state_out_be32 = (uint32_t *)data_out;
- hash_state_out_be64 = (uint64_t *)data_out;
-
- switch (hash_alg) {
- case ICP_QAT_HW_AUTH_ALGO_SHA1:
- if (partial_hash_sha1(data_in, digest))
- return -EFAULT;
- for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
- *hash_state_out_be32 =
- rte_bswap32(*(((uint32_t *)digest)+i));
- break;
- case ICP_QAT_HW_AUTH_ALGO_SHA224:
- if (partial_hash_sha224(data_in, digest))
- return -EFAULT;
- for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
- *hash_state_out_be32 =
- rte_bswap32(*(((uint32_t *)digest)+i));
- break;
- case ICP_QAT_HW_AUTH_ALGO_SHA256:
- if (partial_hash_sha256(data_in, digest))
- return -EFAULT;
- for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
- *hash_state_out_be32 =
- rte_bswap32(*(((uint32_t *)digest)+i));
- break;
- case ICP_QAT_HW_AUTH_ALGO_SHA384:
- if (partial_hash_sha384(data_in, digest))
- return -EFAULT;
- for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
- *hash_state_out_be64 =
- rte_bswap64(*(((uint64_t *)digest)+i));
- break;
- case ICP_QAT_HW_AUTH_ALGO_SHA512:
- if (partial_hash_sha512(data_in, digest))
- return -EFAULT;
- for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
- *hash_state_out_be64 =
- rte_bswap64(*(((uint64_t *)digest)+i));
- break;
- case ICP_QAT_HW_AUTH_ALGO_MD5:
- if (partial_hash_md5(data_in, data_out))
- return -EFAULT;
- break;
- default:
- QAT_LOG(ERR, "invalid hash alg %u", hash_alg);
- return -EFAULT;
- }
-
- return 0;
-}
-
-static const uint8_t AES_CMAC_SEED[ICP_QAT_HW_AES_128_KEY_SZ];
-
-static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
- const uint8_t *auth_key,
- uint16_t auth_keylen,
- uint8_t *p_state_buf,
- uint16_t *p_state_len,
- uint8_t aes_cmac)
-{
- int block_size;
- uint8_t ipad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
- uint8_t opad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
- int i;
-
- if (hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {
-
- /* CMAC */
- if (aes_cmac) {
- AES_KEY enc_key;
- uint8_t *in = NULL;
- uint8_t k0[ICP_QAT_HW_AES_128_KEY_SZ];
- uint8_t *k1, *k2;
-
- auth_keylen = ICP_QAT_HW_AES_128_KEY_SZ;
-
- in = rte_zmalloc("AES CMAC K1",
- ICP_QAT_HW_AES_128_KEY_SZ, 16);
-
- if (in == NULL) {
- QAT_LOG(ERR, "Failed to alloc memory");
- return -ENOMEM;
- }
-
- rte_memcpy(in, AES_CMAC_SEED,
- ICP_QAT_HW_AES_128_KEY_SZ);
- rte_memcpy(p_state_buf, auth_key, auth_keylen);
-
- if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
- &enc_key) != 0) {
- rte_free_sensitive(in);
- return -EFAULT;
- }
-
- AES_encrypt(in, k0, &enc_key);
-
- k1 = p_state_buf + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
- k2 = k1 + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
-
- aes_cmac_key_derive(k0, k1);
- aes_cmac_key_derive(k1, k2);
-
- rte_memzero_explicit(k0, ICP_QAT_HW_AES_128_KEY_SZ);
- *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
- rte_free_sensitive(in);
- goto out;
- } else {
- static uint8_t qat_aes_xcbc_key_seed[
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- };
-
- uint8_t *in = NULL;
- uint8_t *out = p_state_buf;
- int x;
- AES_KEY enc_key;
-
- in = rte_zmalloc("working mem for key",
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
- if (in == NULL) {
- QAT_LOG(ERR, "Failed to alloc memory");
- return -ENOMEM;
- }
-
- rte_memcpy(in, qat_aes_xcbc_key_seed,
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
- for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
- if (AES_set_encrypt_key(auth_key,
- auth_keylen << 3,
- &enc_key) != 0) {
- rte_free_sensitive(in -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
- rte_memzero_explicit(out -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
- return -EFAULT;
- }
- AES_encrypt(in, out, &enc_key);
- in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
- out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
- }
- *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
- rte_free_sensitive(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
- goto out;
- }
-
- } else if ((hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
- (hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
- uint8_t *in = NULL;
- uint8_t *out = p_state_buf;
- AES_KEY enc_key;
-
- memset(p_state_buf, 0, ICP_QAT_HW_GALOIS_H_SZ +
- ICP_QAT_HW_GALOIS_LEN_A_SZ +
- ICP_QAT_HW_GALOIS_E_CTR0_SZ);
- in = rte_zmalloc("working mem for key",
- ICP_QAT_HW_GALOIS_H_SZ, 16);
- if (in == NULL) {
- QAT_LOG(ERR, "Failed to alloc memory");
- return -ENOMEM;
- }
-
- rte_memzero_explicit(in, ICP_QAT_HW_GALOIS_H_SZ);
- if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
- &enc_key) != 0) {
- return -EFAULT;
- }
- AES_encrypt(in, out, &enc_key);
- *p_state_len = ICP_QAT_HW_GALOIS_H_SZ +
- ICP_QAT_HW_GALOIS_LEN_A_SZ +
- ICP_QAT_HW_GALOIS_E_CTR0_SZ;
- rte_free_sensitive(in);
- return 0;
- }
-
- block_size = qat_hash_get_block_size(hash_alg);
- if (block_size < 0)
- return block_size;
- /* init ipad and opad from key and xor with fixed values */
- memset(ipad, 0, block_size);
- memset(opad, 0, block_size);
-
- if (auth_keylen > (unsigned int)block_size) {
- QAT_LOG(ERR, "invalid keylen %u", auth_keylen);
- return -EFAULT;
- }
-
- RTE_VERIFY(auth_keylen <= sizeof(ipad));
- RTE_VERIFY(auth_keylen <= sizeof(opad));
-
- rte_memcpy(ipad, auth_key, auth_keylen);
- rte_memcpy(opad, auth_key, auth_keylen);
-
- for (i = 0; i < block_size; i++) {
- uint8_t *ipad_ptr = ipad + i;
- uint8_t *opad_ptr = opad + i;
- *ipad_ptr ^= HMAC_IPAD_VALUE;
- *opad_ptr ^= HMAC_OPAD_VALUE;
- }
-
- /* do partial hash of ipad and copy to state1 */
- if (partial_hash_compute(hash_alg, ipad, p_state_buf)) {
- rte_memzero_explicit(ipad, block_size);
- rte_memzero_explicit(opad, block_size);
- QAT_LOG(ERR, "ipad precompute failed");
- return -EFAULT;
- }
-
- /*
- * State len is a multiple of 8, so may be larger than the digest.
- * Put the partial hash of opad state_len bytes after state1
- */
- *p_state_len = qat_hash_get_state1_size(hash_alg);
- if (partial_hash_compute(hash_alg, opad, p_state_buf + *p_state_len)) {
- rte_memzero_explicit(ipad, block_size);
- rte_memzero_explicit(opad, block_size);
- QAT_LOG(ERR, "opad precompute failed");
- return -EFAULT;
- }
-
- /* don't leave data lying around */
- rte_memzero_explicit(ipad, block_size);
- rte_memzero_explicit(opad, block_size);
-out:
- return 0;
-}
-
-#else
+/* HMAC precomputes always use IPsec MB (OpenSSL 3.0 removed SHA*_Transform APIs)
+ * OpenSSL is only used for DOCSIS BPI cipher fallback (via EVP API)
+ */
static int aes_ipsecmb_job(uint8_t *in, uint8_t *out, IMB_MGR *m,
const uint8_t *key, uint16_t auth_keylen)
@@ -1992,7 +1660,6 @@ static int qat_sym_do_precomputes_ipsec_mb(enum icp_qat_hw_auth_algo hash_alg,
free_mb_mgr(m);
return ret;
}
-#endif
static void
qat_sym_session_init_common_hdr(struct qat_sym_session *session)
@@ -2482,16 +2149,9 @@ static int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
break;
}
/* SHA-1 HMAC */
-#ifdef RTE_QAT_OPENSSL
- ret = qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1, authkey,
- authkeylen, cdesc->cd_cur_ptr, &state1_size,
- cdesc->aes_cmac);
-
-#else
ret = qat_sym_do_precomputes_ipsec_mb(ICP_QAT_HW_AUTH_ALGO_SHA1,
authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size,
cdesc->aes_cmac);
-#endif
if (ret) {
QAT_LOG(ERR, "(SHA)precompute failed");
@@ -2509,15 +2169,9 @@ static int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
break;
}
/* SHA-224 HMAC */
-#ifdef RTE_QAT_OPENSSL
- ret = qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224, authkey,
- authkeylen, cdesc->cd_cur_ptr, &state1_size,
- cdesc->aes_cmac);
-#else
ret = qat_sym_do_precomputes_ipsec_mb(ICP_QAT_HW_AUTH_ALGO_SHA224,
authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size,
cdesc->aes_cmac);
-#endif
if (ret) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
@@ -2534,15 +2188,9 @@ static int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
break;
}
/* SHA-256 HMAC */
-#ifdef RTE_QAT_OPENSSL
- ret = qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256, authkey,
- authkeylen, cdesc->cd_cur_ptr, &state1_size,
- cdesc->aes_cmac);
-#else
ret = qat_sym_do_precomputes_ipsec_mb(ICP_QAT_HW_AUTH_ALGO_SHA256,
authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size,
cdesc->aes_cmac);
-#endif
if (ret) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
@@ -2559,15 +2207,9 @@ static int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
break;
}
/* SHA-384 HMAC */
-#ifdef RTE_QAT_OPENSSL
- ret = qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384, authkey,
- authkeylen, cdesc->cd_cur_ptr, &state1_size,
- cdesc->aes_cmac);
-#else
ret = qat_sym_do_precomputes_ipsec_mb(ICP_QAT_HW_AUTH_ALGO_SHA384,
authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size,
cdesc->aes_cmac);
-#endif
if (ret) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
@@ -2584,15 +2226,9 @@ static int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
break;
}
/* SHA-512 HMAC */
-#ifdef RTE_QAT_OPENSSL
- ret = qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512, authkey,
- authkeylen, cdesc->cd_cur_ptr, &state1_size,
- cdesc->aes_cmac);
-#else
ret = qat_sym_do_precomputes_ipsec_mb(ICP_QAT_HW_AUTH_ALGO_SHA512,
authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size,
cdesc->aes_cmac);
-#endif
if (ret) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
@@ -2628,16 +2264,10 @@ static int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
if (cdesc->aes_cmac)
memset(cdesc->cd_cur_ptr, 0, state1_size);
-#ifdef RTE_QAT_OPENSSL
- ret = qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC,
- authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size, cdesc->aes_cmac);
-#else
ret = qat_sym_do_precomputes_ipsec_mb(
ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC,
authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
&state2_size, cdesc->aes_cmac);
-#endif
if (ret) {
QAT_LOG(ERR, "(%s)precompute failed",
cdesc->aes_cmac ? "CMAC" : "XCBC");
@@ -2654,15 +2284,9 @@ static int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
cdesc->qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
state1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;
-#ifdef RTE_QAT_OPENSSL
- ret = qat_sym_do_precomputes(cdesc->qat_hash_alg, authkey,
- authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size, cdesc->aes_cmac);
-#else
ret = qat_sym_do_precomputes_ipsec_mb(cdesc->qat_hash_alg, authkey,
authkeylen, cdesc->cd_cur_ptr + state1_size,
&state2_size, cdesc->aes_cmac);
-#endif
if (ret) {
QAT_LOG(ERR, "(GCM)precompute failed");
return -EFAULT;
@@ -2734,15 +2358,9 @@ static int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
auth_param->hash_state_sz = ICP_QAT_HW_ZUC_256_IV_SZ >> 3;
break;
case ICP_QAT_HW_AUTH_ALGO_MD5:
-#ifdef RTE_QAT_OPENSSL
- ret = qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5, authkey,
- authkeylen, cdesc->cd_cur_ptr, &state1_size,
- cdesc->aes_cmac);
-#else
ret = qat_sym_do_precomputes_ipsec_mb(ICP_QAT_HW_AUTH_ALGO_MD5,
authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size,
cdesc->aes_cmac);
-#endif
if (ret) {
QAT_LOG(ERR, "(MD5)precompute failed");
return -EFAULT;
--
2.43.0
^ permalink raw reply related
* [PATCH v1 6/6] net/r8169: fix segmentation fault during RTL8168 initialization
From: Howard Wang @ 2026-06-11 8:28 UTC (permalink / raw)
To: dev; +Cc: pro_nic_dpdk, Howard Wang, stable
In-Reply-To: <20260611083521.20669-1-howard_wang@realsil.com.cn>
In rtl_rx_init(), the configuration of RSS control and RX queue number
(which are specific to RTL8125) was incorrectly executed for all MAC
versions. Accessing RTL8125-specific registers (e.g., RSS_CTRL_8125)
on RTL8168 hardware causes a segmentation fault.
This patch fixes the issue by moving the RTL8125-specific RSS and VMQ
configurations into the existing `if (rtl_is_8125(hw))` block, ensuring
they are only executed on the correct hardware.
Fixes: 25e19d532b4b ("net/r8169: support multi-queues for 8126 and 8127")
Cc: stable@dpdk.org
Signed-off-by: Howard Wang <howard_wang@realsil.com.cn>
---
drivers/net/r8169/r8169_rxtx.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/net/r8169/r8169_rxtx.c b/drivers/net/r8169/r8169_rxtx.c
index e0154b7741..00de0471f4 100644
--- a/drivers/net/r8169/r8169_rxtx.c
+++ b/drivers/net/r8169/r8169_rxtx.c
@@ -672,7 +672,18 @@ rtl_rx_init(struct rte_eth_dev *dev)
rtl_enable_cfg9346_write(hw);
- if (!rtl_is_8125(hw)) {
+ if (rtl_is_8125(hw)) {
+ /* RSS_control_0 */
+ if (hw->EnableRss) {
+ rtl_init_rss(hw, nb_rx_queues);
+ rtl8125_config_rss(hw, nb_rx_queues);
+ } else {
+ RTL_W32(hw, RSS_CTRL_8125, 0x00);
+ }
+
+ /* VMQ_control */
+ rtl8125_set_rx_q_num(hw, nb_rx_queues);
+ } else {
/* RX ftr mcu enable */
csi_tmp = rtl_eri_read(hw, 0xDC, 1, ERIAR_ExGMAC);
csi_tmp &= ~BIT_0;
@@ -700,17 +711,6 @@ rtl_rx_init(struct rte_eth_dev *dev)
else
rtl_clear_rdu = rtl8168_clear_rdu;
- /* RSS_control_0 */
- if (hw->EnableRss) {
- rtl_init_rss(hw, nb_rx_queues);
- rtl8125_config_rss(hw, nb_rx_queues);
- } else {
- RTL_W32(hw, RSS_CTRL_8125, 0x00);
- }
-
- /* VMQ_control */
- rtl8125_set_rx_q_num(hw, nb_rx_queues);
-
RTL_W8(hw, ChipCmd, RTL_R8(hw, ChipCmd) | CmdRxEnb);
return 0;
--
2.43.0
^ permalink raw reply related
* [PATCH v1 5/6] net/r8169: update hardware configurations for 8125
From: Howard Wang @ 2026-06-11 8:28 UTC (permalink / raw)
To: dev; +Cc: pro_nic_dpdk, Howard Wang
In-Reply-To: <20260611083521.20669-1-howard_wang@realsil.com.cn>
Update hw configurations as below:
9151a's phy mcu,
9151a's phy config,
8125bp's mac mcu.
Signed-off-by: Howard Wang <howard_wang@realsil.com.cn>
---
drivers/net/r8169/base/rtl8125bp_mcu.c | 15 ++++++++-------
drivers/net/r8169/base/rtl9151a.c | 8 ++++++++
drivers/net/r8169/base/rtl9151a_mcu.c | 14 ++++++++++++--
drivers/net/r8169/r8169_hw.h | 2 +-
4 files changed, 29 insertions(+), 10 deletions(-)
diff --git a/drivers/net/r8169/base/rtl8125bp_mcu.c b/drivers/net/r8169/base/rtl8125bp_mcu.c
index a591988657..56b036314c 100644
--- a/drivers/net/r8169/base/rtl8125bp_mcu.c
+++ b/drivers/net/r8169/base/rtl8125bp_mcu.c
@@ -59,8 +59,8 @@ rtl_set_mac_mcu_8125bp_2(struct rtl_hw *hw)
{
u16 entry_cnt;
static const u16 mcu_patch_code[] = {
- 0xE010, 0xE033, 0xE046, 0xE04A, 0xE04D, 0xE050, 0xE054, 0xE056, 0xE058,
- 0xE05A, 0xE05C, 0xE05E, 0xE060, 0xE062, 0xE064, 0xE066, 0xB406, 0x1000,
+ 0xE010, 0xE033, 0xE046, 0xE04A, 0xE04D, 0xE050, 0xE054, 0xE058, 0xE05A,
+ 0xE05C, 0xE05E, 0xE060, 0xE062, 0xE064, 0xE066, 0xE068, 0xB406, 0x1000,
0xF016, 0xC61F, 0x400E, 0xF012, 0x218E, 0x25BE, 0x1300, 0xF007, 0x7340,
0xC618, 0x400E, 0xF102, 0x48B0, 0x8320, 0xB400, 0x2402, 0x1000, 0xF003,
0x7342, 0x8322, 0xB000, 0xE007, 0x7322, 0x9B42, 0x7320, 0x9B40, 0x0300,
@@ -69,10 +69,10 @@ rtl_set_mac_mcu_8125bp_2(struct rtl_hw *hw)
0x9B20, 0x1B00, 0x9BA0, 0xC602, 0xBE00, 0x4392, 0xE6E0, 0xE6E2, 0xC01C,
0x4166, 0x9CF6, 0xC002, 0xB800, 0x143C, 0x49D1, 0xC602, 0xBE00, 0x3FC4,
0x49D1, 0xC602, 0xBE00, 0x405A, 0xC104, 0xC202, 0xBA00, 0x22E6, 0xD116,
- 0xC602, 0xBE00, 0x0000, 0xC102, 0xB900, 0x0000, 0xC002, 0xB800, 0x0000,
- 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000,
- 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000,
- 0xC602, 0xBE00, 0x0000, 0x6936, 0x0119, 0x030E, 0x0B18
+ 0x1BC8, 0x46EB, 0xC302, 0xBB00, 0x0F14, 0xC102, 0xB900, 0x0000, 0xC002,
+ 0xB800, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602,
+ 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602,
+ 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0x1171, 0x011A, 0x041D, 0x131A
};
entry_cnt = ARRAY_SIZE(mcu_patch_code);
@@ -92,8 +92,9 @@ rtl_set_mac_mcu_8125bp_2(struct rtl_hw *hw)
rtl_mac_ocp_write(hw, 0xFC2E, 0x3FC2);
rtl_mac_ocp_write(hw, 0xFC30, 0x4058);
rtl_mac_ocp_write(hw, 0xFC32, 0x22E4);
+ rtl_mac_ocp_write(hw, 0xFC34, 0x0F10);
- rtl_mac_ocp_write(hw, 0xFC48, 0x003F);
+ rtl_mac_ocp_write(hw, 0xFC48, 0x007F);
}
/* ------------------------------------PHY 8125BP--------------------------------------- */
diff --git a/drivers/net/r8169/base/rtl9151a.c b/drivers/net/r8169/base/rtl9151a.c
index 4eca5fb96b..54ea424703 100644
--- a/drivers/net/r8169/base/rtl9151a.c
+++ b/drivers/net/r8169/base/rtl9151a.c
@@ -38,6 +38,14 @@ rtl_hw_phy_config_9151a_1(struct rtl_hw *hw)
rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x80B6);
rtl_mdio_direct_write_phy_ocp(hw, 0xA438, 0xB6C3);
+
+ rtl_set_phy_mcu_patch_request(hw);
+
+ rtl_set_eth_phy_ocp_bit(hw, 0xA466, BIT_1);
+ rtl_mdio_direct_write_phy_ocp(hw, 0xA436, 0x837C);
+ rtl_clear_eth_phy_ocp_bit(hw, 0xA438, BIT_14);
+
+ rtl_clear_phy_mcu_patch_request(hw);
}
static void
diff --git a/drivers/net/r8169/base/rtl9151a_mcu.c b/drivers/net/r8169/base/rtl9151a_mcu.c
index 50a2cd90e6..d338daafce 100644
--- a/drivers/net/r8169/base/rtl9151a_mcu.c
+++ b/drivers/net/r8169/base/rtl9151a_mcu.c
@@ -31,8 +31,18 @@ static const u16 phy_mcu_ram_code_9151a_1_1[] = {
0xa436, 0xA108, 0xa438, 0xffff, 0xa436, 0xA106, 0xa438, 0xffff,
0xa436, 0xA104, 0xa438, 0xffff, 0xa436, 0xA102, 0xa438, 0x0cb4,
0xa436, 0xA100, 0xa438, 0x1398, 0xa436, 0xA110, 0xa438, 0x0003,
- 0xb820, 0x0010, 0xB82E, 0x0000, 0xa436, 0x8023, 0xa438, 0x0000,
- 0xB820, 0x0000, 0xFFFF, 0xFFFF
+ 0xb820, 0x0010, 0xa436, 0x844e, 0xa438, 0xaf84, 0xa438, 0x66af,
+ 0xa438, 0x847b, 0xa438, 0xaf84, 0xa438, 0x7baf, 0xa438, 0x847b,
+ 0xa438, 0xaf84, 0xa438, 0x7baf, 0xa438, 0x847b, 0xa438, 0xaf84,
+ 0xa438, 0x7baf, 0xa438, 0x847b, 0xa438, 0xd400, 0xa438, 0x04bf,
+ 0xa438, 0x645d, 0xa438, 0x026a, 0xa438, 0x4cd4, 0xa438, 0x0004,
+ 0xa438, 0xbf64, 0xa438, 0x6002, 0xa438, 0x6a4c, 0xa438, 0xaf61,
+ 0xa438, 0x1600, 0xa436, 0xb818, 0xa438, 0x6110, 0xa436, 0xb81a,
+ 0xa438, 0xffff, 0xa436, 0xb81c, 0xa438, 0xffff, 0xa436, 0xb81e,
+ 0xa438, 0xffff, 0xa436, 0xb850, 0xa438, 0x03d1, 0xa436, 0xb852,
+ 0xa438, 0xffff, 0xa436, 0xb878, 0xa438, 0xffff, 0xa436, 0xb884,
+ 0xa438, 0xffff, 0xa436, 0xb832, 0xa438, 0x0001, 0xB82E, 0x0000,
+ 0xa436, 0x8023, 0xa438, 0x0000, 0xB820, 0x0000, 0xFFFF, 0xFFFF
};
static void
diff --git a/drivers/net/r8169/r8169_hw.h b/drivers/net/r8169/r8169_hw.h
index 65007c2a7e..475bbbb016 100644
--- a/drivers/net/r8169/r8169_hw.h
+++ b/drivers/net/r8169/r8169_hw.h
@@ -138,7 +138,7 @@ extern const struct rtl_hw_ops rtl8125cp_ops;
#define NIC_RAMCODE_VERSION_CFG_METHOD_56 (0x0027)
#define NIC_RAMCODE_VERSION_CFG_METHOD_57 (0x0034)
#define NIC_RAMCODE_VERSION_CFG_METHOD_58 (0x0024)
-#define NIC_RAMCODE_VERSION_CFG_METHOD_60 (0x0003)
+#define NIC_RAMCODE_VERSION_CFG_METHOD_60 (0x0017)
#define NIC_RAMCODE_VERSION_CFG_METHOD_70 (0x0033)
#define NIC_RAMCODE_VERSION_CFG_METHOD_71 (0x0060)
#define NIC_RAMCODE_VERSION_CFG_METHOD_91 (0x0051)
--
2.43.0
^ permalink raw reply related
* [PATCH v1 4/6] net/r8169: remove RTL9151 CSI (DBI) channel support
From: Howard Wang @ 2026-06-11 8:28 UTC (permalink / raw)
To: dev; +Cc: pro_nic_dpdk, Howard Wang
In-Reply-To: <20260611083521.20669-1-howard_wang@realsil.com.cn>
RTL9151 CSI (DBI) channel access is handled by FW. But FW may take
time to handle driver CSI channel access request and cause a HwIoErr.
For the reason mentioned above, remove RTL9151 CSI channel support.
Signed-off-by: Howard Wang <howard_wang@realsil.com.cn>
---
drivers/net/r8169/r8169_hw.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c
index 53d0620422..f15bd579fd 100644
--- a/drivers/net/r8169/r8169_hw.c
+++ b/drivers/net/r8169/r8169_hw.c
@@ -467,6 +467,9 @@ rtl_csi_other_fun_read(struct rtl_hw *hw, u8 multi_fun_sel_bit, u32 addr)
int i;
u32 value = 0xffffffff;
+ if (hw->mcfg == CFG_METHOD_60)
+ goto exit;
+
cmd = CSIAR_Read | CSIAR_ByteEn << CSIAR_ByteEn_shift |
(addr & CSIAR_Addr_Mask);
@@ -506,6 +509,9 @@ rtl_csi_other_fun_write(struct rtl_hw *hw, u8 multi_fun_sel_bit, u32 addr,
u32 cmd;
int i;
+ if (hw->mcfg == CFG_METHOD_60)
+ return;
+
RTL_W32(hw, CSIDR, value);
cmd = CSIAR_Write | CSIAR_ByteEn << CSIAR_ByteEn_shift |
(addr & CSIAR_Addr_Mask);
--
2.43.0
^ permalink raw reply related
* [PATCH v1 3/6] net/r8169: improve RTL8125+ flow control
From: Howard Wang @ 2026-06-11 8:28 UTC (permalink / raw)
To: dev; +Cc: pro_nic_dpdk, Howard Wang
In-Reply-To: <20260611083521.20669-1-howard_wang@realsil.com.cn>
Improve it by using formula to set H/W nearfull and nearempty.
Signed-off-by: Howard Wang <howard_wang@realsil.com.cn>
---
drivers/net/r8169/r8169_hw.c | 67 +++++++++++++++++++++++++++++++++---
1 file changed, 62 insertions(+), 5 deletions(-)
diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c
index e5434165ba..53d0620422 100644
--- a/drivers/net/r8169/r8169_hw.c
+++ b/drivers/net/r8169/r8169_hw.c
@@ -1979,6 +1979,66 @@ rtl8168_switch_to_sgmii_mode(struct rtl_hw *hw)
rtl8168_set_mcu_ocp_bit(hw, 0xEB16, BIT_1);
}
+static u16
+rtl8125_get_fifo_nf(struct rtl_hw *hw)
+{
+ u32 magic = 0;
+ u32 mtu;
+
+ mtu = hw->mtu;
+
+ if (hw->mcfg >= CFG_METHOD_48 && hw->mcfg <= CFG_METHOD_61) {
+ if (mtu < 9500)
+ magic = 14215 + mtu;
+ else
+ return 0x5CA;
+ } else if (hw->mcfg >= CFG_METHOD_70 && hw->mcfg <= CFG_METHOD_71) {
+ if (mtu < 9500)
+ magic = 14447;
+ else
+ magic = 4947;
+
+ magic += mtu * (mtu < 9500 ? 1 : 2);
+ } else if (hw->mcfg >= CFG_METHOD_91) {
+ if (mtu < 9500)
+ magic = 17171;
+ else
+ magic = 7671;
+
+ magic += mtu * (mtu < 9500 ? 1 : 2);
+ }
+
+ return (u16)(magic >> 4);
+}
+
+static u16
+rtl8125_get_fifo_ne(struct rtl_hw *hw)
+{
+ u32 magic = 0;
+ u32 mtu;
+
+ mtu = hw->mtu;
+
+ if (hw->mcfg >= CFG_METHOD_48 && hw->mcfg <= CFG_METHOD_61) {
+ return 0x6BE;
+ } else if (hw->mcfg >= CFG_METHOD_70 && hw->mcfg <= CFG_METHOD_71) {
+ if (mtu < 9500)
+ return 0x107C;
+
+ magic = 77033;
+ } else if (hw->mcfg >= CFG_METHOD_91) {
+ if (mtu < 9500)
+ return 0x2C4A;
+
+ magic = 190910;
+ }
+
+ if (magic > mtu)
+ return (u16)((magic - mtu) >> 4);
+ else
+ return 0;
+}
+
static void
rtl_exit_oob(struct rtl_hw *hw)
{
@@ -2007,12 +2067,9 @@ rtl_exit_oob(struct rtl_hw *hw)
rtl_wait_ll_share_fifo_ready(hw);
if (rtl_is_8125(hw)) {
- rtl_mac_ocp_write(hw, 0xC0AA, 0x07D0);
-
- rtl_mac_ocp_write(hw, 0xC0A6, 0x01B5);
-
+ rtl_mac_ocp_write(hw, 0xC0A6, rtl8125_get_fifo_nf(hw));
+ rtl_mac_ocp_write(hw, 0xC0AA, rtl8125_get_fifo_ne(hw));
rtl_mac_ocp_write(hw, 0xC01E, 0x5555);
-
} else {
data16 = rtl_mac_ocp_read(hw, 0xE8DE) | BIT_15;
rtl_mac_ocp_write(hw, 0xE8DE, data16);
--
2.43.0
^ permalink raw reply related
* [PATCH v1 2/6] net/r8169: optimize Tx datapath by removing redundant packet checks
From: Howard Wang @ 2026-06-11 8:28 UTC (permalink / raw)
To: dev; +Cc: pro_nic_dpdk, Howard Wang
In-Reply-To: <20260611083521.20669-1-howard_wang@realsil.com.cn>
Malformed packets (e.g., pkt_len == 0 or nb_segs == 0) should never
be passed down to the PMD by the upper layers. The current handling
of such abnormal packets in the Tx datapath not only introduces
unnecessary branch overhead but can also lead to unexpected behaviors.
To adhere to DPDK's high-performance design principles, we should not
penalize the datapath to cover up upper-layer errors. Therefore, this
patch removes the runtime 'if' conditions for these anomalies. Instead,
RTE_ASSERT is introduced to help catch such issues during debugging.
Signed-off-by: Howard Wang <howard_wang@realsil.com.cn>
---
drivers/net/r8169/r8169_rxtx.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/net/r8169/r8169_rxtx.c b/drivers/net/r8169/r8169_rxtx.c
index a2e9139ec6..e0154b7741 100644
--- a/drivers/net/r8169/r8169_rxtx.c
+++ b/drivers/net/r8169/r8169_rxtx.c
@@ -1621,8 +1621,7 @@ rtl_xmit_pkt(struct rtl_hw *hw, struct rtl_tx_queue *txq,
len = m_seg->data_len;
- if (len == 0)
- break;
+ RTE_ASSERT(len > 0);
txd = &txq->hw_ring[tail];
@@ -1971,10 +1970,7 @@ rtl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
if (txq->tx_free < tx_pkt->nb_segs)
break;
- /* Check mbuf is valid */
- if (tx_pkt->nb_segs == 0 || tx_pkt->pkt_len == 0 ||
- (tx_pkt->nb_segs > 1 && tx_pkt->next == NULL))
- break;
+ RTE_ASSERT(tx_pkt->pkt_len > 0);
rtl_xmit_pkt(hw, txq, tx_pkt);
}
--
2.43.0
^ permalink raw reply related
* [PATCH v1 1/6] net/r8169: disable RX CRC drop for RTL8125BP and later
From: Howard Wang @ 2026-06-11 8:28 UTC (permalink / raw)
To: dev; +Cc: pro_nic_dpdk, Howard Wang
In-Reply-To: <20260611083521.20669-1-howard_wang@realsil.com.cn>
When RX drop CRC is enabled, the hardware will not DMA the RX CRC,
and the packet length in the RX descriptor will not include the CRC
length.
Other OS drivers might leave this feature enabled instead of disabling
it during their shutdown sequence. To avoid driver conflicts and
unexpected behavior upon reboot or driver reload, explicitly disable
this feature for RTL8125BP and all subsequent MAC versions.
Signed-off-by: Howard Wang <howard_wang@realsil.com.cn>
---
drivers/net/r8169/r8169_compat.h | 1 +
drivers/net/r8169/r8169_hw.c | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/drivers/net/r8169/r8169_compat.h b/drivers/net/r8169/r8169_compat.h
index 91c84c7633..28f0bfc246 100644
--- a/drivers/net/r8169/r8169_compat.h
+++ b/drivers/net/r8169/r8169_compat.h
@@ -347,6 +347,7 @@ enum RTL_register_content {
RxCfg_pause_slot_en = (1 << 11),
RxCfg_9356SEL = (1 << 6),
EnableRxDescV4_0 = (1 << 1), /* Not in rcr */
+ RX_CRC_DROP_EN = (1 << 0),
/* TX config bits */
TxInterFrameGapShift = 24,
diff --git a/drivers/net/r8169/r8169_hw.c b/drivers/net/r8169/r8169_hw.c
index 27d52c81c9..e5434165ba 100644
--- a/drivers/net/r8169/r8169_hw.c
+++ b/drivers/net/r8169/r8169_hw.c
@@ -911,6 +911,29 @@ rtl8125_set_rx_desc_type(struct rtl_hw *hw)
}
}
+static void
+rtl8125_set_rx_crc_drop(struct rtl_hw *hw, bool enable)
+{
+ switch (hw->mcfg) {
+ case CFG_METHOD_54:
+ case CFG_METHOD_55:
+ case CFG_METHOD_56:
+ case CFG_METHOD_57:
+ case CFG_METHOD_58:
+ case CFG_METHOD_59:
+ case CFG_METHOD_60:
+ case CFG_METHOD_61:
+ case CFG_METHOD_70:
+ case CFG_METHOD_71:
+ case CFG_METHOD_91:
+ if (enable)
+ RTL_W8(hw, 0xD8, RTL_R8(hw, 0xD8) | RX_CRC_DROP_EN);
+ else
+ RTL_W8(hw, 0xD8, RTL_R8(hw, 0xD8) & ~RX_CRC_DROP_EN);
+ break;
+ }
+}
+
static void
rtl8125_hw_config(struct rtl_hw *hw)
{
@@ -967,6 +990,8 @@ rtl8125_hw_config(struct rtl_hw *hw)
rtl8125_set_rx_desc_type(hw);
+ rtl8125_set_rx_crc_drop(hw, false);
+
if (hw->mcfg == CFG_METHOD_58 || hw->mcfg == CFG_METHOD_91) {
rtl_clear_mac_ocp_bit(hw, 0xE00C, BIT_12);
rtl_clear_mac_ocp_bit(hw, 0xC0C2, BIT_6);
--
2.43.0
^ permalink raw reply related
* [PATCH v1 0/6] net/r8169: hardware updates, optimizations, and a bug fix
From: Howard Wang @ 2026-06-11 8:28 UTC (permalink / raw)
To: dev; +Cc: pro_nic_dpdk, Howard Wang
This patch series primarily focuses on updating hardware configurations,
optimizing the datapath, and refining device behaviors for the net/r8169 PMD.
Additionally, it includes one bug fix for a segmentation fault encountered
during initialization.
Summary of the series:
- Patch 1: Updates RX CRC drop behavior for RTL8125BP and later MAC versions
to align with device shutdown sequences and prevent cross-driver states.
- Patch 2: Optimizes the Tx datapath performance by removing redundant branch
checks for malformed packets, replacing them with RTE_ASSERT.
- Patch 3: Enhances RTL8125+ flow control by utilizing a new formula for
nearfull and nearempty thresholds.
- Patch 4: Removes RTL9151 CSI (DBI) channel support, as firmware handling
latency makes it no longer suitable for the driver.
- Patch 5: Updates PHY and MAC MCU configurations for RTL9151A and RTL8125BP.
- Patch 6: Fixes a segmentation fault during RTL8168 initialization by
restricting RTL8125-specific RSS/VMQ configurations to the correct hardware.
Howard Wang (6):
net/r8169: disable RX CRC drop for RTL8125BP and later
net/r8169: optimize Tx datapath by removing redundant packet checks
net/r8169: improve RTL8125+ flow control
net/r8169: remove RTL9151 CSI (DBI) channel support
net/r8169: update hardware configurations for 8125
net/r8169: fix segmentation fault during RTL8168 initialization
drivers/net/r8169/base/rtl8125bp_mcu.c | 15 ++--
drivers/net/r8169/base/rtl9151a.c | 8 +++
drivers/net/r8169/base/rtl9151a_mcu.c | 14 +++-
drivers/net/r8169/r8169_compat.h | 1 +
drivers/net/r8169/r8169_hw.c | 98 ++++++++++++++++++++++++--
drivers/net/r8169/r8169_hw.h | 2 +-
drivers/net/r8169/r8169_rxtx.c | 32 ++++-----
7 files changed, 137 insertions(+), 33 deletions(-)
--
2.43.0
^ permalink raw reply
* [PATCH 17/17] common/cnxk: add auth key len check in inbound SA
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Archana Muniganti, Vidya Sagar Velumuri,
Akhil Goyal
Cc: jerinj, Aarnav JP, stable
In-Reply-To: <20260611073311.3129711-1-rbhansali@marvell.com>
From: Aarnav JP <ajp@marvell.com>
Add auth key length validation before memcpy in
cnxk_on_ipsec_inb_sa_create() to prevent caller-provided
keys from overflowing fixed-size in-struct buffers and
corrupting adjacent fields.
Fixes: 532963b80707 ("crypto/cnxk: move IPsec SA creation to common")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/common/cnxk/cnxk_security.c | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index 6f46ad3276..228ff2781d 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -1199,22 +1199,33 @@ cnxk_on_ipsec_inb_sa_create(struct rte_security_ipsec_xform *ipsec,
break;
case RTE_CRYPTO_AUTH_MD5_HMAC:
case RTE_CRYPTO_AUTH_SHA1_HMAC:
- memcpy(in_sa->sha1_or_gcm.hmac_key, auth_key,
- auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- sha1_or_gcm.selector);
+ if (auth_key_len > (int)sizeof(in_sa->sha1_or_gcm.hmac_key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->sha1_or_gcm.hmac_key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
+ memcpy(in_sa->sha1_or_gcm.hmac_key, auth_key, auth_key_len);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, sha1_or_gcm.selector);
break;
case RTE_CRYPTO_AUTH_SHA256_HMAC:
case RTE_CRYPTO_AUTH_SHA384_HMAC:
case RTE_CRYPTO_AUTH_SHA512_HMAC:
+ if (auth_key_len > (int)sizeof(in_sa->sha2.hmac_key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->sha2.hmac_key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
memcpy(in_sa->sha2.hmac_key, auth_key, auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- sha2.selector);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, sha2.selector);
break;
case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+ if (auth_key_len > (int)sizeof(in_sa->aes_xcbc.key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->aes_xcbc.key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
memcpy(in_sa->aes_xcbc.key, auth_key, auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- aes_xcbc.selector);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, aes_xcbc.selector);
break;
default:
plt_err("Unsupported auth algorithm %u", auth_xform->auth.algo);
--
2.34.1
^ permalink raw reply related
* [PATCH 16/17] common/cnxk: fix Klocwork static analysis issues
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Satheesh Paul, Jerin Jacob,
Rakesh Kudurumalla
Cc: Aarnav JP, stable
In-Reply-To: <20260611073311.3129711-1-rbhansali@marvell.com>
From: Aarnav JP <ajp@marvell.com>
Fix NULL pointer dereferences (roc_dev.c, roc_npa.c, roc_nix_inl.c),
resource leaks in error paths (roc_dev.c, roc_dpi.c, roc_ree.c,
roc_nix.c, roc_emdev.c), uninitialized variables (roc_npa_debug.c,
roc_emdev.c), array out-of-bounds access (roc_npc_utils.c, roc_emdev.c),
bitwise operand size mismatches (roc_mbox.h, roc_emdev_irq.c), and
format string type mismatches (roc_cpt_debug.c).
Fixes: 5d8ff275433a ("common/cnxk: fix race condition between up and down mailbox")
Fixes: 9a92937cf0c8 ("common/cnxk: fix possible out-of-bounds access")
Fixes: 7557e3f5b9fa ("common/cnxk: replace direct API usage in REE")
Fixes: 3fdf3e53f3c4 ("common/cnxk: enable CPT CQ for inline IPsec inbound")
Fixes: c758279fee32 ("common/cnxk: support debug dump to file")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/common/cnxk/roc_cpt_debug.c | 29 ++++++++++++++---------------
drivers/common/cnxk/roc_dev.c | 15 +++++++++++----
drivers/common/cnxk/roc_mbox.h | 4 ++--
drivers/common/cnxk/roc_nix_inl.c | 3 +--
drivers/common/cnxk/roc_npa.c | 3 +++
drivers/common/cnxk/roc_npa_debug.c | 8 +++++++-
drivers/common/cnxk/roc_npc_utils.c | 10 +++++++---
drivers/common/cnxk/roc_ree.c | 17 ++++++++++++-----
8 files changed, 57 insertions(+), 32 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index 3b3e678c20..3c1c052e50 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -33,7 +33,7 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
cpth->w0.num_frags, cpth->w0.pkt_out);
/* W1 */
- cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t", cpth->wqe_ptr);
+ cpt_dump(file, "W1: wqe_ptr \t0x%016" PRIx64 "\t", cpth->wqe_ptr);
/* W2 */
cpt_dump(file, "W2: pkt_inline \t0x%x\t\torig_pkt_aura \t0x%x", cpth->w2.pkt_inline,
@@ -135,29 +135,28 @@ cpt_cn10k_parse_hdr_dump(FILE *file, const struct cpt_cn10k_parse_hdr_s *cpth)
cpt_dump(file, "W0: cookie \t0x%x\t\tmatch_id \t0x%04x \t",
cpth->w0.cookie, cpth->w0.match_id);
cpt_dump(file, "W0: err_sum \t%u \t", cpth->w0.err_sum);
- cpt_dump(file, "W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t",
- cpth->w0.reas_sts, cpth->w0.et_owr, cpth->w0.pkt_fmt);
- cpt_dump(file, "W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t",
- cpth->w0.pad_len, cpth->w0.num_frags, cpth->w0.pkt_out);
+ cpt_dump(file, "W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t", cpth->w0.reas_sts,
+ cpth->w0.et_owr, cpth->w0.pkt_fmt);
+ cpt_dump(file, "W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t", cpth->w0.pad_len,
+ cpth->w0.num_frags, cpth->w0.pkt_out);
/* W1 */
- cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t",
- plt_be_to_cpu_64(cpth->wqe_ptr));
+ cpt_dump(file, "W1: wqe_ptr \t0x%016" PRIx64 "\t",
+ (uint64_t)plt_be_to_cpu_64(cpth->wqe_ptr));
/* W2 */
- cpt_dump(file, "W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x",
- cpth->w2.frag_age, cpth->w2.orig_pf_func);
- cpt_dump(file, "W2: il3_off \t0x%x\t\tfi_pad \t0x%x \t",
- cpth->w2.il3_off, cpth->w2.fi_pad);
+ cpt_dump(file, "W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x", cpth->w2.frag_age,
+ cpth->w2.orig_pf_func);
+ cpt_dump(file, "W2: il3_off \t0x%x\t\tfi_pad \t0x%x \t", cpth->w2.il3_off, cpth->w2.fi_pad);
cpt_dump(file, "W2: fi_offset \t0x%x \t", cpth->w2.fi_offset);
/* W3 */
- cpt_dump(file, "W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x",
- cpth->w3.hw_ccode, cpth->w3.uc_ccode, cpth->w3.spi);
+ cpt_dump(file, "W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x", cpth->w3.hw_ccode,
+ cpth->w3.uc_ccode, cpth->w3.spi);
/* W4 */
- cpt_dump(file, "W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64,
- cpth->esn, plt_be_to_cpu_64(cpth->frag1_wqe_ptr));
+ cpt_dump(file, "W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64, cpth->esn,
+ (uint64_t)plt_be_to_cpu_64(cpth->frag1_wqe_ptr));
/* offset of 0 implies 256B, otherwise it implies offset*8B */
offset = cpth->w2.fi_offset;
diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index 32409f2ef3..61aa4b3075 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -1796,14 +1796,17 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
rc = npa_lf_init(dev, pci_dev);
if (rc)
- goto stop_msg_thrd;
+ goto vf_flr_unregister;
/* Setup LMT line base */
rc = dev_lmt_setup(dev);
if (rc)
- goto stop_msg_thrd;
+ goto vf_flr_unregister;
return rc;
+vf_flr_unregister:
+ if (!is_vf)
+ dev_vf_flr_unregister_irqs(pci_dev, dev);
stop_msg_thrd:
/* Exiting the mbox sync thread */
if (dev->sync.start_thread) {
@@ -1812,10 +1815,14 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
plt_thread_join(dev->sync.pfvf_msg_thread, NULL);
}
thread_fail:
- pthread_mutex_destroy(&dev->sync.mutex);
- pthread_cond_destroy(&dev->sync.pfvf_msg_cond);
+ if (pci_dev->max_vfs > 0) {
+ pthread_mutex_destroy(&dev->sync.mutex);
+ pthread_cond_destroy(&dev->sync.pfvf_msg_cond);
+ }
iounmap:
dev_vf_mbase_put(pci_dev, vf_mbase);
+ mbox_fini(&dev->mbox_vfpf);
+ mbox_fini(&dev->mbox_vfpf_up);
mbox_unregister:
dev_mbox_unregister_irq(pci_dev, dev);
if (dev->ops)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 1158ff50a7..52ecde6563 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -47,8 +47,8 @@ struct mbox_msghdr {
#define RVU_VF_VFPF_MBOX0 (0x0000)
#define RVU_VF_VFPF_MBOX1 (0x0008)
-#define MBOX_DOWN_MSG 1
-#define MBOX_UP_MSG 2
+#define MBOX_DOWN_MSG 1ULL
+#define MBOX_UP_MSG 2ULL
/* Mailbox message types */
#define MBOX_MSG_MASK 0xFFFF
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index b515d52534..db101e71a5 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -638,9 +638,8 @@ nix_inl_reass_inb_sa_tbl_setup(struct roc_nix *roc_nix)
res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
if (res_addr_offset)
res_addr_offset |= (1UL << 56);
+ cpt_cq_ena = (uint64_t)inl_dev->cpt_cq_ena << 63;
}
-
- cpt_cq_ena = (uint64_t)inl_dev->cpt_cq_ena << 63;
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id;
lf_cfg->rx_inline_sa_base = (uintptr_t)nix->inb_sa_base[profile_id] | cpt_cq_ena;
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 88e328105a..4a3e96a97a 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -1113,6 +1113,9 @@ roc_npa_pool_destroy(uint64_t aura_handle)
struct npa_lf *lf = idev_npa_obj_get();
int rc = 0, aura_id;
+ if (lf == NULL)
+ return NPA_ERR_DEVICE_NOT_BOUNDED;
+
plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle);
aura_id = roc_npa_aura_handle_to_aura(aura_handle);
diff --git a/drivers/common/cnxk/roc_npa_debug.c b/drivers/common/cnxk/roc_npa_debug.c
index e64696730f..f978be9642 100644
--- a/drivers/common/cnxk/roc_npa_debug.c
+++ b/drivers/common/cnxk/roc_npa_debug.c
@@ -283,6 +283,9 @@ roc_npa_ctx_dump(void)
if (lf->aura_attr[q].halo) {
aq->ctype = NPA_AQ_CTYPE_HALO;
rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
+ } else if (roc_model_is_cn20k()) {
+ aq->ctype = NPA_AQ_CTYPE_AURA;
+ rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
} else {
aq->ctype = NPA_AQ_CTYPE_AURA;
rc = mbox_process_msg(mbox, (void *)&rsp);
@@ -323,7 +326,10 @@ roc_npa_ctx_dump(void)
aq->ctype = NPA_AQ_CTYPE_POOL;
aq->op = NPA_AQ_INSTOP_READ;
- rc = mbox_process_msg(mbox, (void *)&rsp);
+ if (roc_model_is_cn20k())
+ rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
+ else
+ rc = mbox_process_msg(mbox, (void *)&rsp);
if (rc) {
plt_err("Failed to get pool(%d) context", q);
goto exit;
diff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c
index 3c05e46e1b..8e83b8662d 100644
--- a/drivers/common/cnxk/roc_npc_utils.c
+++ b/drivers/common/cnxk/roc_npc_utils.c
@@ -486,7 +486,7 @@ npc_process_ipv6_field_hash_o20k(const struct roc_npc_flow_item_ipv6 *ipv6_spec,
uint8_t hash_field[ROC_IPV6_ADDR_LEN];
struct npc_xtract_info *xinfo;
uint32_t hash = 0, mask;
- int intf, i, rc = 0;
+ int intf, i, hash_idx = 0, rc = 0;
memset(hash_field, 0, sizeof(hash_field));
@@ -505,14 +505,18 @@ npc_process_ipv6_field_hash_o20k(const struct roc_npc_flow_item_ipv6 *ipv6_spec,
if (rc == 0)
continue;
- rc = npc_ipv6_field_hash_get(pst->npc, (const uint32_t *)hash_field, intf, i,
- &hash);
+ if (hash_idx >= NPC_MAX_HASH)
+ break;
+
+ rc = npc_ipv6_field_hash_get(pst->npc, (const uint32_t *)hash_field, intf,
+ hash_idx, &hash);
if (rc)
return rc;
mask = GENMASK(31, 0);
memcpy(pst->mcam_mask + xinfo->key_off, (uint8_t *)&mask, 4);
memcpy(pst->mcam_data + xinfo->key_off, (uint8_t *)&hash, 4);
+ hash_idx++;
}
return 0;
diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
index b6392658c3..923d9251ad 100644
--- a/drivers/common/cnxk/roc_ree.c
+++ b/drivers/common/cnxk/roc_ree.c
@@ -592,14 +592,15 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
vf->block_address = ree_get_blkaddr(dev);
if (!vf->block_address) {
plt_err("Could not determine block PF number");
- goto fail;
+ rc = -ENODEV;
+ goto dev_fini;
}
/* Get number of queues available on the device */
rc = roc_ree_available_queues_get(vf, &nb_queues);
if (rc) {
plt_err("Could not determine the number of queues available");
- goto fail;
+ goto dev_fini;
}
/* Don't exceed the limits set per VF */
@@ -607,7 +608,8 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
if (nb_queues == 0) {
plt_err("No free queues available on the device");
- goto fail;
+ rc = -ENOSPC;
+ goto dev_fini;
}
vf->max_queues = nb_queues;
@@ -618,18 +620,23 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
rc = roc_ree_max_matches_get(vf, &max_matches);
if (rc) {
plt_err("Could not determine the maximum matches supported");
- goto fail;
+ goto dev_fini;
}
/* Don't exceed the limits set per VF */
max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
if (max_matches == 0) {
plt_err("Could not determine the maximum matches supported");
- goto fail;
+ rc = -EIO;
+ goto dev_fini;
}
vf->max_matches = max_matches;
plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
+
+ return 0;
+dev_fini:
+ dev_fini(dev, pci_dev);
fail:
return rc;
}
--
2.34.1
^ permalink raw reply related
* [PATCH 15/17] common/cnxk: add cipher key length check in key set
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Ankur Dwivedi, Akhil Goyal
Cc: jerinj, Aarnav JP, stable
In-Reply-To: <20260611073311.3129711-1-rbhansali@marvell.com>
From: Aarnav JP <ajp@marvell.com>
Add upper-bound checks before memcpy into encr_key[32]
in roc_se_ciph_key_set() to prevent buffer overflow into
adjacent encr_iv[16]. Covers all write paths including
AES-DOCSISBPI and DES-DOCSISBPI branches that bypass
the generic copy via goto.
Fixes: 5e076b609f2a ("common/cnxk: add SE set key for crypto")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/common/cnxk/roc_se.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c
index d841a926a4..1cec536169 100644
--- a/drivers/common/cnxk/roc_se.c
+++ b/drivers/common/cnxk/roc_se.c
@@ -545,12 +545,22 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
* less than 128. Pass it as regular AES-CBC cipher to CPT, but keep type in
* se_ctx as AES_DOCSISBPI to skip block size checks in instruction preparation.
*/
+ if (key_len > sizeof(fctx->enc.encr_key)) {
+ plt_err("Cipher key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key));
+ return -1;
+ }
cpt_ciph_aes_key_type_set(fctx, key_len);
fctx->enc.enc_cipher = ROC_SE_AES_CBC;
memcpy(fctx->enc.encr_key, key, key_len);
goto success;
case ROC_SE_DES_DOCSISBPI:
/* See case ROC_SE_DES3_CBC: for explanation */
+ if (key_len * 3 > sizeof(fctx->enc.encr_key)) {
+ plt_err("DES-DOCSISBPI key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key) / 3);
+ return -1;
+ }
for (i = 0; i < 3; i++)
memcpy(fctx->enc.encr_key + key_len * i, key, key_len);
/*
@@ -628,6 +638,11 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
if (se_ctx->hash_type != ROC_SE_GMAC_TYPE)
fctx->enc.enc_cipher = type;
+ if (key_len > sizeof(fctx->enc.encr_key)) {
+ plt_err("Cipher key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key));
+ return -1;
+ }
memcpy(fctx->enc.encr_key, key, key_len);
success:
--
2.34.1
^ permalink raw reply related
* [PATCH 14/17] net/cnxk: fix bitwise operand size mismatch in link mode
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Aarnav JP, stable
In-Reply-To: <20260611073311.3129711-1-rbhansali@marvell.com>
From: Aarnav JP <ajp@marvell.com>
Cast enum roc_nix_link_mode values to uint64_t before bitwise
OR with uint64_t advertise variable to ensure consistent
operand sizes.
Fixes: 292fcbb3d290 ("net/cnxk: support link mode configuration")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/net/cnxk/cnxk_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c
index dde2c3a313..f6682b4697 100644
--- a/drivers/net/cnxk/cnxk_link.c
+++ b/drivers/net/cnxk/cnxk_link.c
@@ -61,13 +61,13 @@ nix_link_advertising_get(struct cnxk_eth_dev *dev, struct roc_nix_link_info *lin
} else {
for (bit = 0; bit < ROC_NIX_LINK_SPEED_MAX; bit++) {
if (link_info->speed_bitmask & BIT_ULL(bit))
- advertise |= rte_to_ethtool_mode[bit];
+ advertise |= (uint64_t)rte_to_ethtool_mode[bit];
}
goto exit;
}
}
- advertise |= mac_to_ethtool_mode[linfo.lmac_type_id][link_info->full_duplex];
+ advertise |= (uint64_t)mac_to_ethtool_mode[linfo.lmac_type_id][link_info->full_duplex];
exit:
return advertise;
}
--
2.34.1
^ permalink raw reply related
* [PATCH 13/17] net/cnxk: derive ethdev from SA for inbound CPT CQ events
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Aarnav JP
In-Reply-To: <20260611073311.3129711-1-rbhansali@marvell.com>
From: Aarnav JP <ajp@marvell.com>
With inbound CPT CQ events, port_id is unavailable since the inline
device has no roc_nix. Resolve eth_dev for inbound CQ events in the
cn20k PMD callback via the SA private data chain instead of relying
on port_id.
Add an eth_dev back pointer to cnxk_eth_sec_sess, populated at
session creation, to complete the SA-to-ethdev lookup path
(inb_priv->eth_sec->eth_dev).
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/net/cnxk/cn20k_ethdev_sec.c | 22 ++++++++++++++++++++--
drivers/net/cnxk/cnxk_ethdev.h | 3 +++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index 31f2518ea3..a5be85901f 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -541,7 +541,6 @@ cn20k_eth_sec_sso_work_cb(uint64_t *gw, void *args, enum nix_inl_event_type type
uintptr_t nixtx;
uint8_t port;
- RTE_SET_USED(args);
plt_nix_dbg("Received %s event", get_inl_event_type(type));
switch ((gw[0] >> 28) & 0xF) {
@@ -561,8 +560,26 @@ cn20k_eth_sec_sso_work_cb(uint64_t *gw, void *args, enum nix_inl_event_type type
/* Fall through */
default:
if (type) {
- eth_dev = &rte_eth_devices[port_id];
struct cpt_cq_s *cqs = (struct cpt_cq_s *)cq_s;
+
+ if (type == NIX_INL_INB_CPT_CQ) {
+ struct cn20k_inb_priv_data *inb_priv;
+
+ inb_priv = roc_nix_inl_ow_ipsec_inb_sa_sw_rsvd(args);
+ if (inb_priv->eth_sec && inb_priv->eth_sec->eth_dev) {
+ eth_dev = inb_priv->eth_sec->eth_dev;
+ } else {
+ plt_err("Inbound CPT CQ event: no eth_dev in SA priv");
+ return;
+ }
+ } else {
+ if (port_id >= RTE_MAX_ETHPORTS) {
+ plt_err("CPT CQ event: invalid port_id %u", port_id);
+ return;
+ }
+ eth_dev = &rte_eth_devices[port_id];
+ }
+
if (type < NIX_INL_SSO) {
cn20k_eth_sec_post_event(eth_dev, args, type,
(uint16_t)cqs->w0.s.uc_compcode,
@@ -804,6 +821,7 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
inl_dev = !!dev->inb.inl_dev;
memset(eth_sec, 0, sizeof(struct cnxk_eth_sec_sess));
+ eth_sec->eth_dev = eth_dev;
sess_priv.u64 = 0;
lock = inbound ? &dev->inb.lock : &dev->outb.lock;
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index ea6a2be30e..6686fdba31 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -225,6 +225,9 @@ struct cnxk_eth_sec_sess {
/* Out-Of-Place processing */
bool inb_oop;
+
+ /* Back pointer to eth_dev for port_id derivation in CQ callbacks */
+ struct rte_eth_dev *eth_dev;
};
TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
--
2.34.1
^ permalink raw reply related
* [PATCH 12/17] net/cnxk: fix unsigned integer underflow in LSO calculation
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Pavan Nikhilesh, Jerin Jacob,
Rahul Bhansali
Cc: Aarnav JP, stable
In-Reply-To: <20260611073311.3129711-1-rbhansali@marvell.com>
From: Aarnav JP <ajp@marvell.com>
Replace branchless mask-based selection with a ternary operator
to resolve Coverity integer underflow warning. The expression
-(!w1.il3type) assigned -1 to a uint64_t variable, which is
well-defined but flagged as an unsigned integer underflow.
Coverity issue: 502004
Fixes: 19f3af2371a7 ("net/cnxk: add Tx burst for CN10K")
Fixes: 39dc567c1955 ("net/cnxk: add Tx burst for CN9K")
Fixes: 006c1daa89b9 ("net/cnxk: support Tx burst scalar for CN20K")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/net/cnxk/cn10k_tx.h | 8 ++------
drivers/net/cnxk/cn20k_tx.h | 8 ++------
drivers/net/cnxk/cn9k_tx.h | 8 ++------
3 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 8c912a1f35..d5cb2c3294 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -1138,10 +1138,8 @@ cn10k_nix_xmit_prepare(struct cn10k_eth_txq *txq,
if (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_TSO_F &&
(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -1766,13 +1764,11 @@ cn10k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1,
const uint64_t flags, const uint64_t lso_tun_fmt)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
diff --git a/drivers/net/cnxk/cn20k_tx.h b/drivers/net/cnxk/cn20k_tx.h
index 8e64d2e352..a1c71f2761 100644
--- a/drivers/net/cnxk/cn20k_tx.h
+++ b/drivers/net/cnxk/cn20k_tx.h
@@ -1117,10 +1117,8 @@ cn20k_nix_xmit_prepare(struct cn20k_eth_txq *txq, struct rte_mbuf *m, struct rte
if (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_TSO_F &&
(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -1732,13 +1730,11 @@ cn20k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1, union nix
uint64_t ol_flags, const uint64_t flags, const uint64_t lso_tun_fmt)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
index 0ec448e36c..2f9b936d56 100644
--- a/drivers/net/cnxk/cn9k_tx.h
+++ b/drivers/net/cnxk/cn9k_tx.h
@@ -478,10 +478,8 @@ cn9k_nix_xmit_prepare(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
if (flags & NIX_TX_OFFLOAD_TSO_F && (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -875,13 +873,11 @@ cn9k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1,
uint64_t flags)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
--
2.34.1
^ permalink raw reply related
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