* [PATCH] MAINTAINERS: update for ena
From: Stephen Hemminger @ 2026-06-20 16:40 UTC (permalink / raw)
To: dev; +Cc: shaibran, evgenys, amitbern, atrwajee, Stephen Hemminger
Email to Ron Beider <rbeider@amazon.com> bounced.
I assume he is no longer available and other listed maintainers
for ena driver will be enough.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4a68a19b32..700f607db0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -691,7 +691,6 @@ F: doc/guides/nics/features/af_xdp.ini
Amazon ENA
M: Shai Brandes <shaibran@amazon.com>
M: Evgeny Schemeilin <evgenys@amazon.com>
-M: Ron Beider <rbeider@amazon.com>
M: Amit Bernstein <amitbern@amazon.com>
M: Wajeeh Atrash <atrwajee@amazon.com>
F: drivers/net/ena/
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v1 0/5] prefix lcore role enum values
From: Stephen Hemminger @ 2026-06-20 16:42 UTC (permalink / raw)
To: Morten Brørup
Cc: Thomas Monjalon, Huisong Li, andrew.rybchenko, dev, zhanjie9
In-Reply-To: <98CBD80474FA8B44BF855DF32C47DC35F6592C@smartserver.smartshare.dk>
On Fri, 19 Jun 2026 22:11:02 +0200
Morten Brørup <mb@smartsharesystems.com> wrote:
> > From: Stephen Hemminger [mailto:stephen@networkplumber.org]
> > Sent: Friday, 19 June 2026 17.40
> >
> > On Fri, 19 Jun 2026 09:54:51 +0200
> > Morten Brørup <mb@smartsharesystems.com> wrote:
> >
> > > > > The problem with this patch it causes build failures now with abi
> > > > diff.
> > > >
> > > > It is probably a bug of an old version of abidiff.
> > > > I recommend updating.
> > >
> > > With the #define's the ABI has not changed. It's probably too
> > indirect for abidiff to understand.
> > > If we absolutely want to please abidiff, we could keep the existing
> > enums and #define RTE_LCORE_ROLE_RTE ROLE_RTE for now.
> > > But I'm in favor of what was done already.
> >
> > The build failures on github, not in my local builds.
> > https://github.com/ovsrobot/dpdk/actions/runs/27789889172/job/822359650
> > 90
> >
> > It makes looking at patchwork dashboard difficult, all patches show up
> > with red mark
>
> So maybe we can choose the path of pleasing abidiff...
> Keep the existing enums, and #define the new RTE_LCORE_ prefixed variants, and use those in the code.
>
> Later, with an ABI breaking release, we can swap.
> Or maybe we just wait until an ABI breaking release to fix this.
>
Since change is cosmetic, not functional. I think it should be reverted for 26.07
to get github CI to pass on all platforms.
It can be added back in 26.11
^ permalink raw reply
* Re: ARM v8 rte_power_pause
From: Wathsala Vithanage @ 2026-06-20 17:38 UTC (permalink / raw)
To: Hemant Agrawal, Morten Brørup
Cc: dev@dpdk.org, Maxime Leroy, Gagandeep Singh
In-Reply-To: <GV1PR04MB10750F8AC96BEFB29C1DD13BD89E32@GV1PR04MB10750.eurprd04.prod.outlook.com>
On 6/18/26 01:17, Hemant Agrawal wrote:
> Hi Watshala,
> I think WFET is not available on A72 core.
> Can you update your answer w.r.t Cortex-A72/Arm v8.0 architecture?
WFET is not available on A72. We enabled it in DPDK selectively for this
reason.
>
> Regards
> Hemant
>
>
>> -----Original Message-----
>> From: Wathsala Vithanage <wathsala.vithanage@arm.com>
>> Sent: 17 June 2026 17:27
>> To: Hemant Agrawal <hemant.agrawal@nxp.com>; Morten Brørup
>> <mb@smartsharesystems.com>
>> Cc: dev@dpdk.org; Maxime Leroy <maxime@leroys.fr>; Gagandeep Singh
>> <G.Singh@nxp.com>
>> Subject: Re: ARM v8 rte_power_pause
>> Importance: High
>>
>> Hi Morten and Hemant,
>>
>> YIELD is a NOP on non-SMT CPUs, such as Neoverse.
>>
>> WFE is universally available on AArch64, but it comes with a caveat: the CPU
>> can remain in a low-power state indefinitely unless an event is triggered. That
>> event can be generated explicitly via SEV/SEVL by a different CPU, or implicitly
>> through address monitoring (LDAXR).
>>
>> WFET is the safer variant because it includes a timeout, so explicit or implicit
>> event-register manipulation is not required.
>>
>> --wathsala
>>
>> On 6/12/26 01:11, Hemant Agrawal wrote:
>>> Hi Morten,
>>> On Cortex‑A72 (ARMv8), the only architectural primitives available are
>> YIELD, WFE, and WFI:
>>> YIELD is the only deterministic, low-overhead option (pure CPU relax,
>> no entry into low-power state)
>>> WFE can be used as a low-power idle hint, but it is event-driven and
>> not time-based (it may return immediately)
>>> WFI depends on interrupt wakeup and is therefore not suitable for
>>> tight latency loops
>>>
>>> For ~1 µs latency targets, the practical approach is a hybrid strategy:
>>>
>>> Short waits → spin using YIELD
>>> Slightly longer waits → opportunistically use WFE for power reduction
>>>
>>> A simple implementation could look like (not tested):
>>>
>>> static inline void rte_armv8_pause(unsigned int iters) {
>>> if (iters < 64) {
>>> for (unsigned int i = 0; i < iters; i++)
>>> asm volatile("yield");
>>> } else {
>>> asm volatile("sevl");
>>> asm volatile("wfe");
>>> }
>>> }
>>>
>>> @Wathsala Vithanage — would appreciate your thoughts, especially if there
>> are any micro-architectural nuances we should consider.
>>> Regards,
>>> Hemant
>>>
>>>> -----Original Message-----
>>>> From: Morten Brørup <mb@smartsharesystems.com>
>>>> Sent: 03 June 2026 17:26
>>>> To: Wathsala Vithanage <wathsala.vithanage@arm.com>; Hemant Agrawal
>>>> <hemant.agrawal@nxp.com>; Sachin Saxena (OSS)
>>>> <sachin.saxena@oss.nxp.com>
>>>> Cc: dev@dpdk.org; Maxime Leroy <maxime@leroys.fr>
>>>> Subject: ARM v8 rte_power_pause
>>>> Importance: High
>>>>
>>>> Hi Wathsala, Hemant and Sachin,
>>>>
>>>> Over at the Grout project, we are discussing power management in the
>>>> context of 100 Gbit/s latency deadlines [1].
>>>>
>>>> rte_power_pause() is not implemented for ARM v8 / Cortex-A72.
>>>> Syscalls such as nanosleep() have too much overhead, and cannot be used.
>>>>
>>>> Any suggestions for a power-reducing method to make a CPU core "sleep"
>> (i.e.
>>>> do nothing) for durations in the order of 1 microsecond?
>>>>
>>>> [1]:
>>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit
>>>>
>> hu%2F&data=05%7C02%7Chemant.agrawal%40nxp.com%7C06a651571db
>> 545d47d7a0
>> 8decc67908e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C639
>> 172942353
>> 967617%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYi
>> OiIwLjAuMD
>> AwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7
>> C%7C&s
>> data=7NCh3%2BS3TAu1sRLYgqGNAaTwqdgwjqhAs2awPixIeEM%3D&reserve
>> d=0
>>>> b.com%2FDPDK%2Fgrout%2Fpull%2F624%23issuecomment-
>>>>
>> 4602036364&data=05%7C02%7Chemant.agrawal%40nxp.com%7Cdbff5f2e
>> 8db1406f0c4008dec1671791%7C686ea1d3bc2b4c6fa92cd99c5c301635%7
>> C0%7C0%7C639160845728472826%7CUnknown%7CTWFpbGZsb3d8eyJFb
>> XB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTW
>> FpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=DRpJWjm2yaF3Cnhk0b
>>>> bFFhmGbKRweOOiWdsWco2NbX0%3D&reserved=0
>>>>
>>>> -Morten
^ permalink raw reply
* RE: [PATCH] common/qat: add asym crypto disable option
From: Akhil Goyal @ 2026-06-20 18:02 UTC (permalink / raw)
To: Ji, Kai, Nicolau, Radu, dev@dpdk.org
In-Reply-To: <DS0PR11MB745842CEBFACEDBA05C1CE6181232@DS0PR11MB7458.namprd11.prod.outlook.com>
> Acked-by: Kai Ji <kai.ji@intel.com>
Applied to dpdk-next-crypto
^ permalink raw reply
* RE: [PATCH] test: sync soft expiry check in inline IPsec
From: Akhil Goyal @ 2026-06-20 18:08 UTC (permalink / raw)
To: Aarnav JP, dev@dpdk.org, Anoob Joseph, Vamsi Krishna Attunuru
Cc: Jerin Jacob, Nithin Kumar Dabilpuram, Rahul Bhansali, Aarnav JP,
stable@dpdk.org
In-Reply-To: <20260505104351.2678817-1-ajp@marvell.com>
> Subject: [PATCH] test: sync soft expiry check in inline IPsec
>
> Soft expiry events are delivered asynchronously via
> the err-ring polling thread. The test checked notify_event
> right after the RX loop, before the polling thread could
> process the err-ring entry — causing intermittent failures
> with fast algorithms where TX/RX completes faster than the
> polling thread's usleep() wake-up.
>
> Add a bounded poll loop after RX for soft expiry cases, using
> rte_io_rmb() to ensure cross-core visibility. Fix store ordering
> in the callback with rte_io_wmb() so that the event subtype is
> visible before notify_event is set.
>
> Fixes: 34e8a9d9b4f2 ("test/security: add inline IPsec SA soft expiry cases")
> Cc: stable@dpdk.org
>
> Signed-off-by: Aarnav JP <ajp@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
Thanks.
^ permalink raw reply
* RE: [PATCH 1/2] test/crypto: validate ML crypto keys
From: Akhil Goyal @ 2026-06-20 18:17 UTC (permalink / raw)
To: Gowrishankar Muthukrishnan, dev@dpdk.org, Fan Zhang,
Gowrishankar Muthukrishnan
Cc: stable@dpdk.org
In-Reply-To: <20260527085257.1933-1-gmuthukrishn@marvell.com>
> -----Original Message-----
> From: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
> Sent: Wednesday, May 27, 2026 2:23 PM
> To: dev@dpdk.org; Akhil Goyal <gakhil@marvell.com>; Fan Zhang
> <fanzhang.oss@gmail.com>; Gowrishankar Muthukrishnan
> <gmuthukrishn@marvell.com>
> Cc: stable@dpdk.org
> Subject: [PATCH 1/2] test/crypto: validate ML crypto keys
>
> Validate ML-KEM and ML-DSA keys.
>
> Fixes: 76a5877072c ("test/crypto: add ML-KEM and ML-DSA cases")
> Cc: stable@dpdk.org
>
> Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
Series Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
^ permalink raw reply
* RE: [EXTERNAL] [v2] crypto/openssl: update to OpenSSL 3.0 minimum version
From: Akhil Goyal @ 2026-06-20 18:28 UTC (permalink / raw)
To: Emma Finn, Kai Ji; +Cc: dev@dpdk.org
In-Reply-To: <20260528080320.650260-1-emma.finn@intel.com>
> Update the OpenSSL PMD to require OpenSSL 3.0.0 as the minimum
> supported version, removing all compatibility code for earlier
> versions (1.0.1, 1.1.0, 1.1.1).
>
> Signed-off-by: Emma Finn <emma.finn@intel.com>
> ---
> *v2: skip build if openssl v3.0 dependency is not met.
> ---
> doc/guides/cryptodevs/openssl.rst | 4 +-
> doc/guides/rel_notes/release_26_07.rst | 5 +
> drivers/crypto/openssl/compat.h | 203 ------
> drivers/crypto/openssl/meson.build | 4 +-
> drivers/crypto/openssl/openssl_pmd_private.h | 30 -
> drivers/crypto/openssl/rte_openssl_pmd.c | 648 +------------------
> drivers/crypto/openssl/rte_openssl_pmd_ops.c | 206 ------
> 7 files changed, 21 insertions(+), 1079 deletions(-)
>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Thanks for the cleanup. You missed to remove the deprecation notice.
Removed deprecation notice while applying.
Applied to dpdk-next-crypto
^ permalink raw reply
* RE: [EXTERNAL] [v2] crypto/qat: require IPsec MB for HMAC precomputes
From: Akhil Goyal @ 2026-06-20 18:37 UTC (permalink / raw)
To: Emma Finn, Kai Ji; +Cc: dev@dpdk.org
In-Reply-To: <20260619135330.1821985-1-emma.finn@intel.com>
> if (ret) {
> QAT_LOG(ERR, "(MD5)precompute failed");
> return -EFAULT;
> @@ -3197,6 +2828,11 @@ qat_security_session_create(void *dev,
> sess_private_data,
> SECURITY_GET_SESS_PRIV_IOVA(sess));
> if (ret != 0) {
> QAT_LOG(ERR, "Failed to configure session parameters");
> +#ifdef RTE_QAT_OPENSSL
> +#if (OPENSSL_VERSION_NUMBER >= 0x30000000L)
> + ossl_legacy_provider_unload();
> +#endif
> +#endif
Why is this openssl version check required now?
Version < 3.0 is not supported in dpdk.
^ permalink raw reply
* RE: [PATCH 1/2] crypto/ipsec_mb: allow aesni_mb and aesni_gcm vdevs on Arm
From: Akhil Goyal @ 2026-06-20 18:43 UTC (permalink / raw)
To: Hemant Agrawal, Wathsala Vithanage, Kai Ji, Pablo de Lara
Cc: dev@dpdk.org, nd@arm.com, Paul.Elliott@arm.com,
Dhruv.Tripathi@arm.com, Shebu.VargheseKuriakose@arm.com
In-Reply-To: <GV1PR04MB10750F42B67E6112BE4F0466789122@GV1PR04MB10750.eurprd04.prod.outlook.com>
>
>
> > -----Original Message-----
> > From: Wathsala Vithanage <wathsala.vithanage@arm.com>
> > Sent: 30 May 2026 02:25
> > To: Kai Ji <kai.ji@intel.com>; Pablo de Lara <pablo.de.lara.guarch@intel.com>
> > Cc: dev@dpdk.org; nd@arm.com; Paul.Elliott@arm.com;
> > Dhruv.Tripathi@arm.com; Shebu.VargheseKuriakose@arm.com; Wathsala
> > Vithanage <wathsala.vithanage@arm.com>
> > Subject: [PATCH 1/2] crypto/ipsec_mb: allow aesni_mb and aesni_gcm vdevs
> > on Arm
> >
> > Extend Arm PMD gating in ipsec_mb_create() to permit
> > IPSEC_MB_PMD_TYPE_AESNI_MB and IPSEC_MB_PMD_TYPE_AESNI_GCM in
> > addition to existing SNOW3G and ZUC.
> >
> > This removes -ENOTSUP rejection for crypto_aesni_mb and crypto_aesni_gcm
> > on Arm, enabling these vdevs to probe and run when backed by a compatible
> > ipsec-mb library.
> >
> > Signed-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
> > ---
> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Series applied to dpdk-next-crypto
^ permalink raw reply
* RE: [PATCH] examples/ipsec-secgw: drop packets in poll mode
From: Akhil Goyal @ 2026-06-20 18:57 UTC (permalink / raw)
To: Rakesh Kudurumalla, Radu Nicolau
Cc: dev@dpdk.org, Jerin Jacob, Nithin Kumar Dabilpuram,
Rakesh Kudurumalla, dpdk stable
In-Reply-To: <20260601042946.89719-1-rkudurumalla@marvell.com>
> Subject: [PATCH] examples/ipsec-secgw: drop packets in poll mode
>
> During antireplay test packets are forwarded despite
> errors in poll mode instead of dropping.This patch
> fixes the same.
>
> Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
> ---
Fixes: dcbf9ad5fdf4 ("examples/ipsec-secgw: move fast path helper functions")
Cc: stable@dpdk.org
Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
^ permalink raw reply
* RE: [EXTERNAL] [PATCH] security: harden telemetry parameter parsing
From: Akhil Goyal @ 2026-06-20 19:19 UTC (permalink / raw)
To: Stephen Hemminger, dev@dpdk.org
Cc: stable@dpdk.org, Anoob Joseph, Gowrishankar Muthukrishnan
In-Reply-To: <20260605174636.218232-1-stephen@networkplumber.org>
> The cryptodev security telemetry handlers parsed dev_id/capa_id with
> strtoul() and no overflow or range check, so an out-of-range dev_id
> (e.g. 256) silently truncated to a valid device in
> rte_cryptodev_is_valid_dev(). isdigit() was also called on a plain
> (signed) char, which is undefined for high-bit input.
> The parser was also using strtok() which is not thread safe.
>
> Use a validated parse helper and reject malformed input rather than
> logging and continuing. This also drops the thread-unsafe strtok() in
> the crypto_caps handler.
>
> Fixes: 259ca6d1617f ("security: add telemetry endpoint for capabilities")
> Cc: stable@dpdk.org
>
> Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
This patch seems to be already merged in main tree as part of other series.
Marking it as superseded.
^ permalink raw reply
* RE: [PATCH v2] crypto/openssl: fix use-after-free bug and cleanup
From: Akhil Goyal @ 2026-06-20 19:21 UTC (permalink / raw)
To: Pratik Senapati, dev@dpdk.org; +Cc: kai.ji@intel.com, stable@dpdk.org
In-Reply-To: <20260609055302.1539202-1-psenapati@marvell.com>
> -----Original Message-----
> From: Pratik Senapati <psenapati@marvell.com>
> Sent: Tuesday, June 9, 2026 11:23 AM
> To: dev@dpdk.org
> Cc: Akhil Goyal <gakhil@marvell.com>; kai.ji@intel.com; stable@dpdk.org
> Subject: [PATCH v2] crypto/openssl: fix use-after-free bug and cleanup
>
> params is freed before it is used by
> EVP_PKEY_decapsulate_init()
> causing a use-after-free issue.
>
> Pass NULL to EVP_PKEY_decapsulate_init()
> instead of params to avoid it.
>
> Add resource cleanup for all error paths in the
> ML-KEM decapsulate and encapsulate handlers.
>
> Consolidate cleanup into multiple goto labels;
> err_decap, err_pkey, err_params for decap and
> err_encap, err_pkey, err_params for encap.
>
> Fixes: 5f761d7b605e ("crypto/openssl: support ML-KEM and ML-DSA")
> Cc: stable@dpdk.org
>
> Signed-off-by: Pratik Senapati <psenapati@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
Thanks.
^ permalink raw reply
* RE: [PATCH 1/2] crypto/ipsec_mb: remove chacha-poly and kasumi drivers
From: Akhil Goyal @ 2026-06-20 19:22 UTC (permalink / raw)
To: De Lara Guarch, Pablo, Nicolau, Radu, dev@dpdk.org
Cc: paul.elliott@arm.com, Shebu.VargheseKuriakose@arm.com,
Kantecki, Tomasz, Islam.Ragimov@arm.com,
Gowtham.SureshKumar@arm.com, Finn, Emma, Cornu, Marcel D,
Mcnamara, John, Jonathan.Wright@arm.com, Dhruv.Tripathi@arm.com,
wathsala.vithanage@arm.com, Thomas Monjalon, Fan Zhang, Ji, Kai
In-Reply-To: <BL1PR11MB552766F74EA3CD53AA04AFBF84E32@BL1PR11MB5527.namprd11.prod.outlook.com>
>
> > -----Original Message-----
> > From: Nicolau, Radu <radu.nicolau@intel.com>
> > Sent: Wednesday, June 3, 2026 10:28 AM
> > To: dev@dpdk.org
> > Cc: paul.elliott@arm.com; Shebu.VargheseKuriakose@arm.com; Kantecki,
> > Tomasz <tomasz.kantecki@intel.com>; Islam.Ragimov@arm.com;
> > Gowtham.SureshKumar@arm.com; Finn, Emma <emma.finn@intel.com>;
> > Cornu, Marcel D <marcel.d.cornu@intel.com>; gakhil@marvell.com;
> > Mcnamara, John <john.mcnamara@intel.com>; Jonathan.Wright@arm.com;
> > Dhruv.Tripathi@arm.com; wathsala.vithanage@arm.com; Nicolau, Radu
> > <radu.nicolau@intel.com>; Thomas Monjalon <thomas@monjalon.net>;
> > Fan Zhang <fanzhang.oss@gmail.com>; Ji, Kai <kai.ji@intel.com>; De Lara
> > Guarch, Pablo <pablo.de.lara.guarch@intel.com>
> > Subject: [PATCH 1/2] crypto/ipsec_mb: remove chacha-poly and kasumi
> > drivers
> >
> > The Chacha20-poly1305 and KASUMI drivers were just wrappers around
> > the main AESNI_MB driver, hence redundant and removed.
> >
> > Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
> > ---
> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Series Applied to dpdk-next-crypto
^ permalink raw reply
* RE: [PATCH] test/security: increase wait time for reassebmly test
From: Akhil Goyal @ 2026-06-20 19:28 UTC (permalink / raw)
To: Rahul Bhansali, dev@dpdk.org, Anoob Joseph; +Cc: Rahul Bhansali
In-Reply-To: <20260611061851.3099305-1-rbhansali@marvell.com>
> -----Original Message-----
> From: Rahul Bhansali <rbhansali@marvell.com>
> Sent: Thursday, June 11, 2026 11:49 AM
> To: dev@dpdk.org; Akhil Goyal <gakhil@marvell.com>; Anoob Joseph
> <anoobj@marvell.com>
> Cc: Rahul Bhansali <rbhansali@marvell.com>
> Subject: [PATCH] test/security: increase wait time for reassebmly test
>
> In case of multi segment inline IPsec reassembly burst test
> of 4 fragment per packet where each fragment is multi
> segmented ~11k bytes and sometimes few of reassembly fails
> out of 33 such burst.
>
> Delay of 1ms after burst Tx is not sufficient in this case,
> hence need to increase to 10ms to avoid random reassembly
> failures in functional tests.
>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> ---
Acked-by: Akhil Goyal <gakhil@marvell.com>
Applied to dpdk-next-crypto
^ permalink raw reply
* Re: ARM v8 rte_power_pause
From: saeed bishara @ 2026-06-20 20:23 UTC (permalink / raw)
To: Wathsala Vithanage
Cc: Hemant Agrawal, Morten Brørup, dev@dpdk.org, Maxime Leroy,
Gagandeep Singh
In-Reply-To: <1eb241f5-3cef-4814-ab3c-13246a452513@arm.com>
note that Event Stream periodically generates wakeup event for WFE,
linux kernel enables it and configures it to 100Hz (10us).
https://developer.arm.com/documentation/102379/0104/The-processor-timers/Event-stream
saeed
On Sat, Jun 20, 2026 at 8:46 PM Wathsala Vithanage
<wathsala.vithanage@arm.com> wrote:
>
>
> On 6/18/26 01:17, Hemant Agrawal wrote:
> > Hi Watshala,
> > I think WFET is not available on A72 core.
> > Can you update your answer w.r.t Cortex-A72/Arm v8.0 architecture?
>
> WFET is not available on A72. We enabled it in DPDK selectively for this
> reason.
>
> >
> > Regards
> > Hemant
> >
> >
> >> -----Original Message-----
> >> From: Wathsala Vithanage <wathsala.vithanage@arm.com>
> >> Sent: 17 June 2026 17:27
> >> To: Hemant Agrawal <hemant.agrawal@nxp.com>; Morten Brørup
> >> <mb@smartsharesystems.com>
> >> Cc: dev@dpdk.org; Maxime Leroy <maxime@leroys.fr>; Gagandeep Singh
> >> <G.Singh@nxp.com>
> >> Subject: Re: ARM v8 rte_power_pause
> >> Importance: High
> >>
> >> Hi Morten and Hemant,
> >>
> >> YIELD is a NOP on non-SMT CPUs, such as Neoverse.
> >>
> >> WFE is universally available on AArch64, but it comes with a caveat: the CPU
> >> can remain in a low-power state indefinitely unless an event is triggered. That
> >> event can be generated explicitly via SEV/SEVL by a different CPU, or implicitly
> >> through address monitoring (LDAXR).
> >>
> >> WFET is the safer variant because it includes a timeout, so explicit or implicit
> >> event-register manipulation is not required.
> >>
> >> --wathsala
> >>
> >> On 6/12/26 01:11, Hemant Agrawal wrote:
> >>> Hi Morten,
> >>> On Cortex‑A72 (ARMv8), the only architectural primitives available are
> >> YIELD, WFE, and WFI:
> >>> YIELD is the only deterministic, low-overhead option (pure CPU relax,
> >> no entry into low-power state)
> >>> WFE can be used as a low-power idle hint, but it is event-driven and
> >> not time-based (it may return immediately)
> >>> WFI depends on interrupt wakeup and is therefore not suitable for
> >>> tight latency loops
> >>>
> >>> For ~1 µs latency targets, the practical approach is a hybrid strategy:
> >>>
> >>> Short waits → spin using YIELD
> >>> Slightly longer waits → opportunistically use WFE for power reduction
> >>>
> >>> A simple implementation could look like (not tested):
> >>>
> >>> static inline void rte_armv8_pause(unsigned int iters) {
> >>> if (iters < 64) {
> >>> for (unsigned int i = 0; i < iters; i++)
> >>> asm volatile("yield");
> >>> } else {
> >>> asm volatile("sevl");
> >>> asm volatile("wfe");
> >>> }
> >>> }
> >>>
> >>> @Wathsala Vithanage — would appreciate your thoughts, especially if there
> >> are any micro-architectural nuances we should consider.
> >>> Regards,
> >>> Hemant
> >>>
> >>>> -----Original Message-----
> >>>> From: Morten Brørup <mb@smartsharesystems.com>
> >>>> Sent: 03 June 2026 17:26
> >>>> To: Wathsala Vithanage <wathsala.vithanage@arm.com>; Hemant Agrawal
> >>>> <hemant.agrawal@nxp.com>; Sachin Saxena (OSS)
> >>>> <sachin.saxena@oss.nxp.com>
> >>>> Cc: dev@dpdk.org; Maxime Leroy <maxime@leroys.fr>
> >>>> Subject: ARM v8 rte_power_pause
> >>>> Importance: High
> >>>>
> >>>> Hi Wathsala, Hemant and Sachin,
> >>>>
> >>>> Over at the Grout project, we are discussing power management in the
> >>>> context of 100 Gbit/s latency deadlines [1].
> >>>>
> >>>> rte_power_pause() is not implemented for ARM v8 / Cortex-A72.
> >>>> Syscalls such as nanosleep() have too much overhead, and cannot be used.
> >>>>
> >>>> Any suggestions for a power-reducing method to make a CPU core "sleep"
> >> (i.e.
> >>>> do nothing) for durations in the order of 1 microsecond?
> >>>>
> >>>> [1]:
> >>>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit
> >>>>
> >> hu%2F&data=05%7C02%7Chemant.agrawal%40nxp.com%7C06a651571db
> >> 545d47d7a0
> >> 8decc67908e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C639
> >> 172942353
> >> 967617%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYi
> >> OiIwLjAuMD
> >> AwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7
> >> C%7C&s
> >> data=7NCh3%2BS3TAu1sRLYgqGNAaTwqdgwjqhAs2awPixIeEM%3D&reserve
> >> d=0
> >>>> b.com%2FDPDK%2Fgrout%2Fpull%2F624%23issuecomment-
> >>>>
> >> 4602036364&data=05%7C02%7Chemant.agrawal%40nxp.com%7Cdbff5f2e
> >> 8db1406f0c4008dec1671791%7C686ea1d3bc2b4c6fa92cd99c5c301635%7
> >> C0%7C0%7C639160845728472826%7CUnknown%7CTWFpbGZsb3d8eyJFb
> >> XB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTW
> >> FpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=DRpJWjm2yaF3Cnhk0b
> >>>> bFFhmGbKRweOOiWdsWco2NbX0%3D&reserved=0
> >>>>
> >>>> -Morten
^ permalink raw reply
* Re: [PATCH v5 00/24] deprecate rte_atomic functions
From: Hemant Agrawal @ 2026-06-21 4:27 UTC (permalink / raw)
To: Stephen Hemminger, dev
In-Reply-To: <20260620023134.42877-1-stephen@networkplumber.org>
On 20-06-2026 07:58, Stephen Hemminger wrote:
> The rte_atomicNN_* family was flagged for deprecation in 2021 by
> commit 3ec965b6de12 ("doc: update atomic operation deprecation")
> but enforcement never landed and in-tree usage continued to grow.
>
> This series finishes converting every remaining in-tree caller to
> the C11-style rte_atomic_*_explicit() / RTE_ATOMIC() API, then
> marks the legacy functions __rte_deprecated so future in-tree and
> out-of-tree uses are caught at compile time.
>
> The goal of this series is to get driver writers to review and
> test each change.
>
> v5 - rebase now that ring changes are merged.
> - drop the barrier (rte_smp_mb) patch not required.
>
>
> Stephen Hemminger (24):
> bpf: use C11 atomics in BPF_ST_ATOMIC_REG
> net/bonding: use stdatomic
> net/nbl: remove unused rte_atomic16 field
> net/ena: replace use of rte_atomicNN
> net/failsafe: convert to stdatomic
> net/enic: do not use deprecated rte_atomic64
> net/pfe: use ethdev linkstatus helpers
> net/sfc: replace rte_atomic with stdatomic
> crypto/ccp: replace use of rte_atomic64 with stdatomic
> bus/dpaa: replace rte_atomic16 with stdatomic
> drivers: replace rte_atomic16 with stdatomic
> net/netvsc: replace rte_atomic32 with stdatomic
> event/sw: convert from rte_atomic32 to stdatomic
> bus/vmbus: convert from rte_atomic to stdatomic
> common/dpaax: use stdatomic instead of rte_atomic
> net/bnx2x: convert from rte_atomic32 to stdatomic
> bus/fslmc: replace rte_atomic32 with stdatomic
> drivers/event: replace rte_atomic32 in selftests
> net/hinic: replace rte_atomic32 with stdatomic
> net/txgbe: replace rte_atomic32 with stdatomic
> net/vhost: use stdatomic instead of rte_atomic32
> vdpa/ifc: replace rte_atomic32 with stdatomic
> test/atomic: suppress deprecation warnings for legacy APIs
> eal: deprecate rte_atomicNN functions
>
for dpaax/fslmc patches:
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
^ permalink raw reply
* Re: [PATCH v2 0/6] net/dpaa2: NAPI-style Rx queue interrupts
From: Hemant Agrawal @ 2026-06-21 4:33 UTC (permalink / raw)
To: Maxime Leroy, dev
In-Reply-To: <20260616102727.708948-1-maxime@leroys.fr>
Hi Maxime,
On 16-06-2026 15:57, Maxime Leroy wrote:
> This series lets a dpaa2 worker sleep on a queue's data-availability
> notification instead of busy-polling, exposed through the generic
> rte_eth_dev_rx_intr_* API (NAPI-style: poll while frames keep coming,
> arm the interrupt and sleep when the queue runs dry).
>
We need to try out few things on it. I am afraid that it will take
some time and our review for this patch will be late.
Regards
Hemant
^ permalink raw reply
* [v2] crypto/cnxk: add ML crypto support
From: Gowrishankar Muthukrishnan @ 2026-06-21 7:56 UTC (permalink / raw)
To: dev, Akhil Goyal, Nithin Dabilpuram, Kiran Kumar K,
Sunil Kumar Kori, Satha Rao, Harman Kalra, Ankur Dwivedi,
Anoob Joseph, Tejasree Kondoj
Cc: Stephen Hemminger, Gowrishankar Muthukrishnan
In-Reply-To: <20260529091330.6308-1-gmuthukrishn@marvell.com>
Add ML-KEM and ML-DSA support.
Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
---
v2:
- Addressed comments from v1.
---
doc/guides/cryptodevs/features/cn20k.ini | 3 +
doc/guides/cryptodevs/features/default.ini | 1 +
doc/guides/rel_notes/release_26_07.rst | 3 +
drivers/common/cnxk/hw/cpt.h | 1 +
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_cpt.c | 4 +
drivers/common/cnxk/roc_platform.h | 5 +
.../common/cnxk/roc_platform_base_symbols.c | 2 +
drivers/common/cnxk/roc_re.h | 31 ++
drivers/common/cnxk/roc_re_ml_tables.c | 248 +++++++++++
drivers/common/cnxk/roc_re_ml_tables.h | 19 +
drivers/crypto/cnxk/cnxk_ae.h | 399 +++++++++++++++++-
drivers/crypto/cnxk/cnxk_cryptodev.c | 11 +
drivers/crypto/cnxk/cnxk_cryptodev.h | 4 +-
.../crypto/cnxk/cnxk_cryptodev_capabilities.c | 62 ++-
drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 45 +-
16 files changed, 817 insertions(+), 22 deletions(-)
create mode 100644 drivers/common/cnxk/roc_re.h
create mode 100644 drivers/common/cnxk/roc_re_ml_tables.c
create mode 100644 drivers/common/cnxk/roc_re_ml_tables.h
diff --git a/doc/guides/cryptodevs/features/cn20k.ini b/doc/guides/cryptodevs/features/cn20k.ini
index d4c52082c6..8180128744 100644
--- a/doc/guides/cryptodevs/features/cn20k.ini
+++ b/doc/guides/cryptodevs/features/cn20k.ini
@@ -21,6 +21,7 @@ Asymmetric sessionless = Y
Sym raw data path API = Y
Inner checksum = Y
Rx inject = Y
+ML-DSA sign prehash = Y
;
; Supported crypto algorithms of 'cn20k' crypto driver.
@@ -110,6 +111,8 @@ ECDSA = Y
ECPM = Y
SM2 = Y
EdDSA = Y
+ML-DSA = Y
+ML-KEM = Y
;
; Supported Operating systems of the 'cn20k' crypto driver.
diff --git a/doc/guides/cryptodevs/features/default.ini b/doc/guides/cryptodevs/features/default.ini
index d8026c3750..be4ee777fb 100644
--- a/doc/guides/cryptodevs/features/default.ini
+++ b/doc/guides/cryptodevs/features/default.ini
@@ -35,6 +35,7 @@ Cipher multiple data units =
Cipher wrapped key =
Inner checksum =
Rx inject =
+ML-DSA sign prehash =
;
; Supported crypto algorithms of a default crypto driver.
diff --git a/doc/guides/rel_notes/release_26_07.rst b/doc/guides/rel_notes/release_26_07.rst
index 5d7aa8d1bf..13ffc487b1 100644
--- a/doc/guides/rel_notes/release_26_07.rst
+++ b/doc/guides/rel_notes/release_26_07.rst
@@ -155,6 +155,9 @@ New Features
Added AGENTS.md file for AI review
and supporting scripts to review patches and documentation.
+* **Updated Marvell cnxk crypto driver.**
+
+ * Added support for ML-KEM and ML-DSA on CN20K platform.
Removed Items
-------------
diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
index eb795f61ac..12aeb4d054 100644
--- a/drivers/common/cnxk/hw/cpt.h
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -58,6 +58,7 @@ enum cpt_eng_type {
CPT_ENG_TYPE_AE = 1,
CPT_ENG_TYPE_SE = 2,
CPT_ENG_TYPE_IE = 3,
+ CPT_ENG_TYPE_RE = 4,
CPT_MAX_ENG_TYPES,
};
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 9db77a9702..3303ad9354 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -65,6 +65,7 @@ sources = files(
'roc_npc_utils.c',
'roc_platform.c',
'roc_platform_base_symbols.c',
+ 'roc_re_ml_tables.c',
'roc_se.c',
'roc_sso.c',
'roc_sso_debug.c',
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 21d5e7f2ba..686c9eae7e 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -632,6 +632,9 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf, bool rxc_ena, uint16_t
eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
(1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]);
+ if (roc_model_is_cn20k())
+ eng_grpmsk |= (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_RE]);
+
if (roc_errata_cpt_has_ctx_fetch_issue()) {
ctx_ilen_valid = true;
/* Inbound SA size is max context size */
@@ -1097,6 +1100,7 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)
case CPT_ENG_TYPE_AE:
case CPT_ENG_TYPE_SE:
case CPT_ENG_TYPE_IE:
+ case CPT_ENG_TYPE_RE:
break;
default:
ret = -EINVAL;
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 73cc12e567..ac4f76473f 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -41,6 +41,7 @@
".arch_extension lse\n"
#endif
+#define PLT_ATOMIC RTE_ATOMIC
#define PLT_ASSERT RTE_ASSERT
#define PLT_VERIFY RTE_VERIFY
#define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE
@@ -218,6 +219,10 @@ plt_thread_is_valid(plt_thread_t thr)
#define plt_memory_order_release rte_memory_order_release
#define plt_memory_order_acquire rte_memory_order_acquire
#define plt_memory_order_relaxed rte_memory_order_relaxed
+#define plt_memory_order_seq_cst rte_memory_order_seq_cst
+
+#define plt_atomic_fetch_add_explicit rte_atomic_fetch_add_explicit
+#define plt_atomic_fetch_sub_explicit rte_atomic_fetch_sub_explicit
#define plt_bit_relaxed_get32 rte_bit_relaxed_get32
#define plt_bit_relaxed_set32 rte_bit_relaxed_set32
diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c
index ed34d4b05b..ece28d3885 100644
--- a/drivers/common/cnxk/roc_platform_base_symbols.c
+++ b/drivers/common/cnxk/roc_platform_base_symbols.c
@@ -500,6 +500,8 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_aged_flow_ctx_get)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_defrag_mcam_banks)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_get_key_type)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_mcam_dump)
+RTE_EXPORT_INTERNAL_SYMBOL(roc_re_ml_zeta_get)
+RTE_EXPORT_INTERNAL_SYMBOL(roc_re_ml_zeta_put)
RTE_EXPORT_INTERNAL_SYMBOL(roc_ree_queues_attach)
RTE_EXPORT_INTERNAL_SYMBOL(roc_ree_queues_detach)
RTE_EXPORT_INTERNAL_SYMBOL(roc_ree_msix_offsets_get)
diff --git a/drivers/common/cnxk/roc_re.h b/drivers/common/cnxk/roc_re.h
new file mode 100644
index 0000000000..a8cbda41c0
--- /dev/null
+++ b/drivers/common/cnxk/roc_re.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2026 Marvell.
+ */
+
+#ifndef __ROC_RE_H__
+#define __ROC_RE_H__
+
+/* RE ML opcodes */
+#define ROC_RE_MAJOR_OP_MLKEM 0x1A
+#define ROC_RE_MAJOR_OP_MLDSA 0x1B
+#define ROC_RE_MINOR_OP_MLKEM_KEYGEN 0x00
+#define ROC_RE_MINOR_OP_MLKEM_ENCAP 0x01
+#define ROC_RE_MINOR_OP_MLKEM_DECAP 0x02
+#define ROC_RE_MINOR_OP_MLDSA_KEYGEN 0x00
+#define ROC_RE_MINOR_OP_MLDSA_SIGN 0x01
+#define ROC_RE_MINOR_OP_MLDSA_VERIFY 0x02
+
+/* ML-KEM param2 fields */
+#define ROC_RE_ML_KEM_PARAM2_INMSG_BIT 4
+#define ROC_RE_ML_KEM_PARAM2_INSEED_BIT 5
+
+/* ML-DSA param2 fields */
+#define ROC_RE_ML_DSA_PARAM2_SIGN_BIT 4
+#define ROC_RE_ML_DSA_PARAM2_SEED_BIT 5
+#define ROC_RE_ML_DSA_PARAM2_CTXN_BIT 8
+
+/* ML-DSA minor op fields */
+#define ROC_RE_ML_DSA_MINOR_SIGN_TYPE_BIT 2
+#define ROC_RE_ML_DSA_MINOR_MSG_TYPE_BIT 4
+
+#endif /* __ROC_RE_H__ */
diff --git a/drivers/common/cnxk/roc_re_ml_tables.c b/drivers/common/cnxk/roc_re_ml_tables.c
new file mode 100644
index 0000000000..621807a555
--- /dev/null
+++ b/drivers/common/cnxk/roc_re_ml_tables.c
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2026 Marvell.
+ */
+
+#include "roc_re_ml_tables.h"
+
+#define RE_ML_TBL_NAME "re_ml_tbl"
+#define RE_MLKEM_ZETA_LEN 256
+#define RE_MLDSA_ZETA_LEN 1024
+
+/* ML table address and length */
+struct re_ml_entry {
+ const uint8_t *data;
+ size_t len;
+};
+
+struct re_ml_tbl {
+ PLT_ATOMIC(uint64_t) refcount;
+ uint8_t ml_tbl[];
+};
+
+static const uint8_t re_mlkem_zeta_tbl[RE_MLKEM_ZETA_LEN] = {
+ 0x01, 0x00, 0xc1, 0x06, 0x14, 0x0a, 0xd9, 0x0c,
+ 0x52, 0x0a, 0x76, 0x02, 0x69, 0x07, 0x50, 0x03,
+ 0x26, 0x04, 0x7f, 0x07, 0xc1, 0x00, 0x1d, 0x03,
+ 0xe2, 0x0a, 0xbc, 0x0c, 0x39, 0x02, 0xd2, 0x06,
+ 0x28, 0x01, 0x8f, 0x09, 0x3b, 0x05, 0xc4, 0x05,
+ 0xe6, 0x0b, 0x38, 0x00, 0xc0, 0x08, 0x35, 0x05,
+ 0x92, 0x05, 0x2e, 0x08, 0x17, 0x02, 0x42, 0x0b,
+ 0x59, 0x09, 0x3f, 0x0b, 0xb6, 0x07, 0x35, 0x03,
+ 0x21, 0x01, 0x4b, 0x01, 0xb5, 0x0c, 0xdc, 0x06,
+ 0xad, 0x04, 0x00, 0x09, 0xe5, 0x08, 0x07, 0x08,
+ 0x8a, 0x02, 0xb9, 0x07, 0xd1, 0x09, 0x78, 0x02,
+ 0x31, 0x0b, 0x21, 0x00, 0x28, 0x05, 0x7b, 0x07,
+ 0x0f, 0x09, 0x9b, 0x05, 0x27, 0x03, 0xc4, 0x01,
+ 0x9e, 0x05, 0x34, 0x0b, 0xfe, 0x05, 0x62, 0x09,
+ 0x57, 0x0a, 0x39, 0x0a, 0xc9, 0x05, 0x88, 0x02,
+ 0xaa, 0x09, 0x26, 0x0c, 0xcb, 0x04, 0x8e, 0x03,
+ 0x11, 0x00, 0xc9, 0x0a, 0x47, 0x02, 0x59, 0x0a,
+ 0x65, 0x06, 0xd3, 0x02, 0xf0, 0x08, 0x4c, 0x04,
+ 0x81, 0x05, 0x66, 0x0a, 0xd1, 0x0c, 0xe9, 0x00,
+ 0xf4, 0x02, 0x6c, 0x08, 0xc7, 0x0b, 0xea, 0x0b,
+ 0xa7, 0x06, 0x73, 0x06, 0xe5, 0x0a, 0xfd, 0x06,
+ 0x37, 0x07, 0xb8, 0x03, 0xb5, 0x05, 0x7f, 0x0a,
+ 0xab, 0x03, 0x04, 0x09, 0x85, 0x09, 0x54, 0x09,
+ 0xdd, 0x02, 0x21, 0x09, 0x0c, 0x01, 0x81, 0x02,
+ 0x30, 0x06, 0xfa, 0x08, 0xf5, 0x07, 0x94, 0x0c,
+ 0x77, 0x01, 0xf5, 0x09, 0x2a, 0x08, 0x6d, 0x06,
+ 0x27, 0x04, 0x3f, 0x01, 0xd5, 0x0a, 0xf5, 0x02,
+ 0x33, 0x08, 0x31, 0x02, 0xa2, 0x09, 0x22, 0x0a,
+ 0xf4, 0x0a, 0x44, 0x04, 0x93, 0x01, 0x02, 0x04,
+ 0x77, 0x04, 0x66, 0x08, 0xd7, 0x0a, 0x76, 0x03,
+ 0xba, 0x06, 0xbc, 0x04, 0x52, 0x07, 0x05, 0x04,
+ 0x3e, 0x08, 0x77, 0x0b, 0x75, 0x03, 0x6a, 0x08,
+};
+
+static const uint8_t re_mldsa_zeta_tbl[RE_MLDSA_ZETA_LEN] = {
+ 0x01, 0x00, 0x00, 0x00, 0x02, 0x5e, 0x49, 0x00,
+ 0x67, 0x75, 0x39, 0x00, 0x69, 0x65, 0x39, 0x00,
+ 0x2b, 0x06, 0x4f, 0x00, 0x73, 0xdf, 0x53, 0x00,
+ 0x33, 0xe0, 0x4f, 0x00, 0x6b, 0x06, 0x4f, 0x00,
+ 0xae, 0xb1, 0x76, 0x00, 0xd5, 0x0d, 0x36, 0x00,
+ 0xb0, 0xed, 0x28, 0x00, 0xe4, 0x7f, 0x20, 0x00,
+ 0x83, 0x72, 0x39, 0x00, 0x4a, 0x89, 0x70, 0x00,
+ 0x92, 0x81, 0x08, 0x00, 0xc8, 0x3d, 0x6d, 0x00,
+ 0x94, 0x72, 0x4c, 0x00, 0xb4, 0xe0, 0x41, 0x00,
+ 0xd2, 0xa3, 0x28, 0x00, 0x8a, 0x52, 0x66, 0x00,
+ 0xa7, 0x18, 0x4a, 0x00, 0x34, 0x40, 0x79, 0x00,
+ 0xee, 0x52, 0x0a, 0x00, 0x81, 0x7d, 0x6b, 0x00,
+ 0x1d, 0x9f, 0x4e, 0x00, 0x77, 0x28, 0x1a, 0x00,
+ 0xdf, 0x71, 0x25, 0x00, 0xee, 0x49, 0x16, 0x00,
+ 0xbd, 0x11, 0x76, 0x00, 0xb7, 0x2b, 0x49, 0x00,
+ 0x97, 0xf6, 0x2a, 0x00, 0xd5, 0xd8, 0x22, 0x00,
+ 0x2a, 0xf7, 0x36, 0x00, 0x1e, 0x91, 0x30, 0x00,
+ 0x3f, 0xd1, 0x29, 0x00, 0x73, 0x26, 0x49, 0x00,
+ 0x5f, 0x68, 0x50, 0x00, 0xa2, 0x10, 0x20, 0x00,
+ 0xf7, 0x87, 0x38, 0x00, 0xc3, 0xb2, 0x11, 0x00,
+ 0xa4, 0x03, 0x06, 0x00, 0xed, 0x2b, 0x0e, 0x00,
+ 0x2c, 0xb7, 0x10, 0x00, 0x35, 0x5f, 0x4a, 0x00,
+ 0x15, 0x9d, 0x1f, 0x00, 0xd4, 0x8c, 0x42, 0x00,
+ 0xf4, 0x77, 0x31, 0x00, 0x12, 0xe6, 0x20, 0x00,
+ 0x1d, 0x1c, 0x34, 0x00, 0x73, 0xd8, 0x1a, 0x00,
+ 0x81, 0x66, 0x73, 0x00, 0x3f, 0x55, 0x49, 0x00,
+ 0xf6, 0x52, 0x39, 0x00, 0x4a, 0x56, 0x62, 0x00,
+ 0x05, 0xad, 0x65, 0x00, 0x1c, 0x9a, 0x43, 0x00,
+ 0x5f, 0xaa, 0x53, 0x00, 0x22, 0xb6, 0x30, 0x00,
+ 0x38, 0x7f, 0x08, 0x00, 0x6d, 0x0e, 0x3b, 0x00,
+ 0xda, 0x83, 0x2c, 0x00, 0x6e, 0x49, 0x1c, 0x00,
+ 0x2b, 0x0e, 0x33, 0x00, 0x70, 0x5b, 0x1c, 0x00,
+ 0xf1, 0xe3, 0x2e, 0x00, 0xb9, 0x7e, 0x13, 0x00,
+ 0x30, 0xa9, 0x57, 0x00, 0xef, 0xc6, 0x3a, 0x00,
+ 0x4c, 0xd5, 0x3f, 0x00, 0xea, 0xb2, 0x4e, 0x00,
+ 0xe1, 0x3e, 0x50, 0x00, 0x75, 0xb1, 0x7b, 0x00,
+ 0xb4, 0x48, 0x26, 0x00, 0x56, 0xf2, 0x1e, 0x00,
+ 0xa2, 0x90, 0x1d, 0x00, 0xd4, 0xa6, 0x45, 0x00,
+ 0x9b, 0xe5, 0x2a, 0x00, 0x9c, 0x58, 0x52, 0x00,
+ 0xf5, 0xf1, 0x6e, 0x00, 0x88, 0x72, 0x3f, 0x00,
+ 0x02, 0x51, 0x17, 0x00, 0x59, 0x5d, 0x07, 0x00,
+ 0xba, 0x87, 0x11, 0x00, 0xa9, 0xac, 0x52, 0x00,
+ 0x9e, 0x3e, 0x77, 0x00, 0xd8, 0x96, 0x02, 0x00,
+ 0xec, 0x92, 0x25, 0x00, 0x12, 0xff, 0x4c, 0x00,
+ 0xe8, 0x4c, 0x40, 0x00, 0x82, 0xa5, 0x4a, 0x00,
+ 0xe6, 0x54, 0x1e, 0x00, 0xc1, 0x16, 0x4f, 0x00,
+ 0x79, 0x7e, 0x1a, 0x00, 0x8f, 0x97, 0x03, 0x00,
+ 0x17, 0x48, 0x4e, 0x00, 0x59, 0xb8, 0x31, 0x00,
+ 0xcc, 0x84, 0x58, 0x00, 0x27, 0x48, 0x1b, 0x00,
+ 0xd0, 0x63, 0x5b, 0x00, 0x7a, 0x78, 0x5d, 0x00,
+ 0x5e, 0x22, 0x35, 0x00, 0x7e, 0x0c, 0x40, 0x00,
+ 0xd1, 0x09, 0x6c, 0x00, 0x32, 0xd5, 0x5b, 0x00,
+ 0xd3, 0xc4, 0x6b, 0x00, 0xcb, 0x8e, 0x25, 0x00,
+ 0x4c, 0x53, 0x2e, 0x00, 0x6c, 0x7a, 0x09, 0x00,
+ 0x20, 0x88, 0x3b, 0x00, 0x5c, 0x28, 0x6d, 0x00,
+ 0xf8, 0xa4, 0x2c, 0x00, 0xaa, 0x7c, 0x33, 0x00,
+ 0xa0, 0xb2, 0x14, 0x00, 0x36, 0x85, 0x55, 0x00,
+ 0x86, 0xf1, 0x28, 0x00, 0x5d, 0x79, 0x55, 0x00,
+ 0x70, 0xf6, 0x4a, 0x00, 0x86, 0x4a, 0x23, 0x00,
+ 0x26, 0xe8, 0x75, 0x00, 0x66, 0xde, 0x78, 0x00,
+ 0x8c, 0x52, 0x05, 0x00, 0x59, 0xdf, 0x7a, 0x00,
+ 0x17, 0x6e, 0x0f, 0x00, 0xda, 0xf3, 0x5b, 0x00,
+ 0x7e, 0x9b, 0x45, 0x00, 0x34, 0x8b, 0x62, 0x00,
+ 0xcb, 0xbe, 0x5d, 0x00, 0x7b, 0x9e, 0x1a, 0x00,
+ 0xd9, 0x06, 0x00, 0x00, 0xc5, 0x57, 0x62, 0x00,
+ 0x3c, 0x4b, 0x57, 0x00, 0xef, 0xa8, 0x69, 0x00,
+ 0x38, 0x98, 0x28, 0x00, 0xfe, 0xb5, 0x64, 0x00,
+ 0xf5, 0xf8, 0x7e, 0x00, 0x78, 0x4e, 0x2a, 0x00,
+ 0x23, 0x0a, 0x12, 0x00, 0xa8, 0x54, 0x01, 0x00,
+ 0xff, 0xb7, 0x09, 0x00, 0x87, 0x5e, 0x43, 0x00,
+ 0xf8, 0x7f, 0x43, 0x00, 0xb4, 0xd5, 0x5c, 0x00,
+ 0x4e, 0xc0, 0x4d, 0x00, 0xaf, 0x28, 0x47, 0x00,
+ 0x5d, 0x73, 0x7f, 0x00, 0x0d, 0x8d, 0x0c, 0x00,
+ 0xd5, 0x66, 0x0f, 0x00, 0x80, 0x6d, 0x5a, 0x00,
+ 0x98, 0xab, 0x61, 0x00, 0x96, 0x5d, 0x18, 0x00,
+ 0x31, 0x7f, 0x43, 0x00, 0x98, 0x82, 0x46, 0x00,
+ 0x60, 0x29, 0x66, 0x00, 0x79, 0xd5, 0x4b, 0x00,
+ 0x06, 0xde, 0x28, 0x00, 0x8d, 0x5d, 0x46, 0x00,
+ 0xe3, 0xb0, 0x49, 0x00, 0x34, 0xb4, 0x09, 0x00,
+ 0xb3, 0x0d, 0x7c, 0x00, 0xb0, 0x68, 0x5a, 0x00,
+ 0xa9, 0x9b, 0x40, 0x00, 0xd5, 0xd3, 0x64, 0x00,
+ 0x2a, 0x76, 0x21, 0x00, 0x91, 0x85, 0x65, 0x00,
+ 0x39, 0x6e, 0x24, 0x00, 0x9b, 0xc3, 0x48, 0x00,
+ 0x59, 0xc7, 0x7b, 0x00, 0x59, 0x58, 0x4f, 0x00,
+ 0xb2, 0x2d, 0x39, 0x00, 0x23, 0x09, 0x23, 0x00,
+ 0x67, 0xeb, 0x12, 0x00, 0xf2, 0x4d, 0x45, 0x00,
+ 0x1c, 0xc3, 0x30, 0x00, 0x24, 0x54, 0x28, 0x00,
+ 0x2e, 0x23, 0x13, 0x00, 0x80, 0xaf, 0x7f, 0x00,
+ 0xcb, 0xbf, 0x2d, 0x00, 0x0b, 0x2a, 0x02, 0x00,
+ 0x2c, 0x83, 0x7e, 0x00, 0x7a, 0x58, 0x26, 0x00,
+ 0x75, 0x33, 0x6b, 0x00, 0x76, 0x5b, 0x09, 0x00,
+ 0xcc, 0xe1, 0x6b, 0x00, 0x1e, 0x06, 0x5e, 0x00,
+ 0x0d, 0xe0, 0x78, 0x00, 0x37, 0x8c, 0x62, 0x00,
+ 0x04, 0xa6, 0x3d, 0x00, 0x3c, 0xe5, 0x4a, 0x00,
+ 0x68, 0x1d, 0x1f, 0x00, 0xbb, 0x30, 0x63, 0x00,
+ 0xb8, 0x61, 0x73, 0x00, 0x6c, 0xa0, 0x5e, 0x00,
+ 0xc7, 0x1a, 0x67, 0x00, 0xc6, 0x1f, 0x20, 0x00,
+ 0xff, 0xa4, 0x5b, 0x00, 0x72, 0xd7, 0x60, 0x00,
+ 0x01, 0xf2, 0x08, 0x00, 0x24, 0xe0, 0x6d, 0x00,
+ 0x6d, 0x0e, 0x08, 0x00, 0x8e, 0x03, 0x56, 0x00,
+ 0x88, 0x56, 0x69, 0x00, 0x3e, 0x6d, 0x1e, 0x00,
+ 0xbd, 0x03, 0x26, 0x00, 0xfa, 0x9d, 0x6a, 0x00,
+ 0x17, 0xc0, 0x07, 0x00, 0xd4, 0xbf, 0x6d, 0x00,
+ 0xbd, 0xd0, 0x74, 0x00, 0xe3, 0xe1, 0x63, 0x00,
+ 0x73, 0x95, 0x51, 0x00, 0x0d, 0xb6, 0x7a, 0x00,
+ 0xba, 0x67, 0x28, 0x00, 0xd4, 0xec, 0x2d, 0x00,
+ 0x8c, 0x01, 0x58, 0x00, 0xf5, 0x4c, 0x3f, 0x00,
+ 0x09, 0x70, 0x0b, 0x00, 0x23, 0x7e, 0x42, 0x00,
+ 0x37, 0xbd, 0x3c, 0x00, 0x33, 0x33, 0x27, 0x00,
+ 0x57, 0x39, 0x67, 0x00, 0x5d, 0x4b, 0x1a, 0x00,
+ 0x26, 0x69, 0x19, 0x00, 0x06, 0xf2, 0x1e, 0x00,
+ 0x4e, 0xc1, 0x11, 0x00, 0xc8, 0x76, 0x4c, 0x00,
+ 0x2f, 0xf4, 0x3c, 0x00, 0x9a, 0xb1, 0x7f, 0x00,
+ 0x6c, 0xf6, 0x6a, 0x00, 0x69, 0x16, 0x2e, 0x00,
+ 0xd6, 0x52, 0x33, 0x00, 0x60, 0x47, 0x03, 0x00,
+ 0x60, 0x52, 0x08, 0x00, 0x78, 0x1e, 0x74, 0x00,
+ 0x16, 0x63, 0x2f, 0x00, 0x11, 0x0a, 0x6f, 0x00,
+ 0xf1, 0xc0, 0x07, 0x00, 0x0b, 0x6d, 0x77, 0x00,
+ 0xf0, 0x1f, 0x0d, 0x00, 0x24, 0x58, 0x34, 0x00,
+ 0xd4, 0x23, 0x02, 0x00, 0x59, 0xc5, 0x68, 0x00,
+ 0x85, 0x88, 0x5e, 0x00, 0x32, 0xaa, 0x2f, 0x00,
+ 0x65, 0xfc, 0x23, 0x00, 0x42, 0x69, 0x5e, 0x00,
+ 0xed, 0xe0, 0x51, 0x00, 0xb3, 0xad, 0x65, 0x00,
+ 0xe6, 0xa5, 0x2c, 0x00, 0xfe, 0xe1, 0x79, 0x00,
+ 0x64, 0x40, 0x7b, 0x00, 0xdd, 0xe1, 0x35, 0x00,
+ 0xac, 0x3a, 0x43, 0x00, 0xde, 0x4a, 0x46, 0x00,
+ 0x14, 0xfe, 0x1c, 0x00, 0xce, 0xf1, 0x73, 0x00,
+ 0x0e, 0x17, 0x10, 0x00, 0xd7, 0xb6, 0x74, 0x00,
+};
+
+static const struct re_ml_entry re_ml_zeta_tbl[2] = {
+ {
+ .data = re_mlkem_zeta_tbl,
+ .len = sizeof(re_mlkem_zeta_tbl)
+ },
+ {
+ .data = re_mldsa_zeta_tbl,
+ .len = sizeof(re_mldsa_zeta_tbl)
+ }
+};
+
+int
+roc_re_ml_zeta_get(uint64_t *tbl)
+{
+ int len = RE_MLKEM_ZETA_LEN + RE_MLDSA_ZETA_LEN;
+ const char name[] = RE_ML_TBL_NAME;
+ const struct plt_memzone *mz;
+ struct re_ml_tbl *ml;
+ uint8_t *data;
+
+ if (tbl == NULL)
+ return -EINVAL;
+
+ mz = plt_memzone_lookup(name);
+ if (mz == NULL) {
+ /* Create memzone first time */
+ mz = plt_memzone_reserve_cache_align(name, sizeof(struct re_ml_tbl) + len);
+ if (mz == NULL)
+ return -ENOMEM;
+ }
+
+ ml = mz->addr;
+ if (plt_atomic_fetch_add_explicit(&ml->refcount, 1, plt_memory_order_seq_cst) != 0)
+ return 0;
+
+ data = PLT_PTR_ADD(mz->addr, sizeof(uint64_t));
+ memcpy(data, re_ml_zeta_tbl[0].data, re_ml_zeta_tbl[0].len);
+ tbl[0] = plt_cpu_to_be_64((uintptr_t)data);
+
+ data = PLT_PTR_ADD(data, re_ml_zeta_tbl[0].len);
+ memcpy(data, re_ml_zeta_tbl[1].data, re_ml_zeta_tbl[1].len);
+ tbl[1] = plt_cpu_to_be_64((uintptr_t)data);
+
+ return 0;
+}
+
+void
+roc_re_ml_zeta_put(void)
+{
+ const char name[] = RE_ML_TBL_NAME;
+ const struct plt_memzone *mz;
+ struct re_ml_tbl *ml;
+
+ mz = plt_memzone_lookup(name);
+ if (mz == NULL)
+ return;
+
+ ml = mz->addr;
+ if (plt_atomic_fetch_sub_explicit(&ml->refcount, 1, plt_memory_order_seq_cst) == 1)
+ plt_memzone_free(mz);
+}
diff --git a/drivers/common/cnxk/roc_re_ml_tables.h b/drivers/common/cnxk/roc_re_ml_tables.h
new file mode 100644
index 0000000000..0a425f711d
--- /dev/null
+++ b/drivers/common/cnxk/roc_re_ml_tables.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2026 Marvell.
+ */
+
+#ifndef _ROC_RE_ML_TABLES_H_
+#define _ROC_RE_ML_TABLES_H_
+
+#include "roc_platform.h"
+
+enum roc_re_ml_zeta_idx {
+ ROC_RE_ML_ZETA_IDX_KEM = 0,
+ ROC_RE_ML_ZETA_IDX_DSA,
+ ROC_RE_ML_ZETA_IDX_MAX
+};
+
+int __roc_api roc_re_ml_zeta_get(uint64_t *tbl);
+void __roc_api roc_re_ml_zeta_put(void);
+
+#endif /* _ROC_RE_ML_TABLES_H_ */
diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h
index 21a0c8068a..691f9bfce5 100644
--- a/drivers/crypto/cnxk/cnxk_ae.h
+++ b/drivers/crypto/cnxk/cnxk_ae.h
@@ -10,6 +10,7 @@
#include <rte_malloc.h>
#include "roc_ae.h"
+#include "roc_re.h"
#include "cnxk_cryptodev_ops.h"
@@ -24,8 +25,11 @@ struct cnxk_ae_sess {
struct rte_crypto_rsa_xform rsa_ctx;
struct rte_crypto_modex_xform mod_ctx;
struct roc_ae_ec_ctx ec_ctx;
+ struct rte_crypto_ml_kem_xform ml_kem_ctx;
+ struct rte_crypto_ml_dsa_xform ml_dsa_ctx;
};
uint64_t *cnxk_fpm_iova;
+ uint64_t *cnxk_ml_iova;
struct roc_ae_ec_group **ec_grp;
uint64_t cpt_inst_w4;
uint64_t cpt_inst_w7;
@@ -52,6 +56,15 @@ struct cnxk_ae_sess {
} hw_ctx __plt_aligned(ROC_ALIGN);
};
+static const uint8_t mldsa_hash_algo[] = {
+ [RTE_CRYPTO_AUTH_SHA3_224] = 0xA,
+ [RTE_CRYPTO_AUTH_SHA3_256] = 0xB,
+ [RTE_CRYPTO_AUTH_SHA3_384] = 0xC,
+ [RTE_CRYPTO_AUTH_SHA3_512] = 0xD,
+ [RTE_CRYPTO_AUTH_SHAKE_128] = 0xE,
+ [RTE_CRYPTO_AUTH_SHAKE_256] = 0xF,
+};
+
static __rte_always_inline void
cnxk_ae_modex_param_normalize(uint8_t **data, size_t *len, size_t max)
{
@@ -259,6 +272,32 @@ cnxk_ae_fill_ec_params(struct cnxk_ae_sess *sess, struct rte_crypto_asym_xform *
return 0;
}
+static __rte_always_inline int
+cnxk_ae_fill_ml_kem_params(struct cnxk_ae_sess *sess,
+ struct rte_crypto_asym_xform *xform)
+{
+ struct rte_crypto_ml_kem_xform *ml_kem = &sess->ml_kem_ctx;
+ if (xform->mlkem.type == RTE_CRYPTO_ML_KEM_NONE)
+ return -EINVAL;
+
+ ml_kem->type = xform->mlkem.type;
+ return 0;
+}
+
+static __rte_always_inline int
+cnxk_ae_fill_ml_dsa_params(struct cnxk_ae_sess *sess,
+ struct rte_crypto_asym_xform *xform)
+{
+ struct rte_crypto_ml_dsa_xform *ml_dsa = &sess->ml_dsa_ctx;
+ if (xform->mldsa.type == RTE_CRYPTO_ML_DSA_NONE)
+ return -EINVAL;
+
+ ml_dsa->type = xform->mldsa.type;
+ ml_dsa->sign_deterministic = xform->mldsa.sign_deterministic;
+ ml_dsa->sign_prehash = xform->mldsa.sign_prehash;
+ return 0;
+}
+
static __rte_always_inline int
cnxk_ae_fill_session_parameters(struct cnxk_ae_sess *sess,
struct rte_crypto_asym_xform *xform)
@@ -284,6 +323,12 @@ cnxk_ae_fill_session_parameters(struct cnxk_ae_sess *sess,
case RTE_CRYPTO_ASYM_XFORM_EDDSA:
ret = cnxk_ae_fill_ec_params(sess, xform);
break;
+ case RTE_CRYPTO_ASYM_XFORM_ML_KEM:
+ ret = cnxk_ae_fill_ml_kem_params(sess, xform);
+ break;
+ case RTE_CRYPTO_ASYM_XFORM_ML_DSA:
+ ret = cnxk_ae_fill_ml_dsa_params(sess, xform);
+ break;
default:
return -ENOTSUP;
}
@@ -563,6 +608,280 @@ cnxk_ae_enqueue_rsa_op(struct rte_crypto_op *op, struct roc_ae_buf_ptr *meta_buf
return 0;
}
+static __rte_always_inline int __rte_hot
+cnxk_ae_enqueue_ml_kem_op(struct rte_crypto_op *op, struct roc_ae_buf_ptr *meta_buf,
+ struct cnxk_ae_sess *sess, struct cpt_inst_s *inst)
+{
+ size_t metabuf_len = cnxk_cpt_asym_get_mlen(), reqbuf_len;
+ struct rte_crypto_ml_kem_op *mlkem = &op->asym->mlkem;
+ union cpt_inst_w4 w4;
+ uint32_t dlen = 0;
+ uint16_t param2;
+ uint8_t *dptr;
+
+ /* Input buffer */
+ dptr = meta_buf->vaddr;
+ inst->dptr = (uintptr_t)dptr;
+
+ switch (mlkem->op) {
+ case RTE_CRYPTO_ML_KEM_OP_KEYGEN:
+ reqbuf_len = mlkem->keygen.d.length + mlkem->keygen.z.length;
+ if (reqbuf_len > (metabuf_len - dlen)) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -ENOMEM;
+ }
+
+ memcpy(dptr, mlkem->keygen.d.data, mlkem->keygen.d.length);
+ dptr += mlkem->keygen.d.length;
+ memcpy(dptr, mlkem->keygen.z.data, mlkem->keygen.z.length);
+ dptr += mlkem->keygen.z.length;
+
+ dlen = mlkem->keygen.d.length + mlkem->keygen.z.length;
+ w4.s.opcode_major = ROC_RE_MAJOR_OP_MLKEM;
+ w4.s.opcode_minor = ROC_RE_MINOR_OP_MLKEM_KEYGEN;
+ param2 = sess->ml_kem_ctx.type;
+ param2 |= (!!dlen << ROC_RE_ML_KEM_PARAM2_INSEED_BIT);
+ break;
+ case RTE_CRYPTO_ML_KEM_OP_ENCAP:
+ reqbuf_len = mlkem->encap.message.length + mlkem->encap.ek.length;
+ if (reqbuf_len > (metabuf_len - dlen)) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -ENOMEM;
+ }
+
+ memcpy(dptr, mlkem->encap.message.data, mlkem->encap.message.length);
+ dptr += mlkem->encap.message.length;
+ memcpy(dptr, mlkem->encap.ek.data, mlkem->encap.ek.length);
+ dptr += mlkem->encap.ek.length;
+
+ dlen = mlkem->encap.message.length + mlkem->encap.ek.length;
+ w4.s.opcode_major = ROC_RE_MAJOR_OP_MLKEM;
+ w4.s.opcode_minor = ROC_RE_MINOR_OP_MLKEM_ENCAP;
+ param2 = sess->ml_kem_ctx.type;
+ param2 |= (!!mlkem->encap.message.length << ROC_RE_ML_KEM_PARAM2_INMSG_BIT);
+ break;
+ case RTE_CRYPTO_ML_KEM_OP_DECAP:
+ reqbuf_len = mlkem->decap.dk.length + mlkem->decap.cipher.length;
+ if (reqbuf_len > (metabuf_len - dlen)) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -ENOMEM;
+ }
+
+ memcpy(dptr, mlkem->decap.dk.data, mlkem->decap.dk.length);
+ dptr += mlkem->decap.dk.length;
+ memcpy(dptr, mlkem->decap.cipher.data, mlkem->decap.cipher.length);
+ dptr += mlkem->decap.cipher.length;
+
+ dlen = mlkem->decap.cipher.length + mlkem->decap.dk.length;
+ w4.s.opcode_major = ROC_RE_MAJOR_OP_MLKEM;
+ w4.s.opcode_minor = ROC_RE_MINOR_OP_MLKEM_DECAP;
+ param2 = sess->ml_kem_ctx.type;
+ break;
+ default:
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -EINVAL;
+ }
+
+ w4.s.param1 = 0;
+ w4.s.param2 = param2;
+ w4.s.dlen = dlen;
+
+ inst->w4.u64 = w4.u64;
+
+ /* Reuse entire space of meta buffer as output is large in PQC */
+ inst->rptr = (uintptr_t)meta_buf->vaddr;
+
+ return 0;
+}
+
+static __rte_always_inline int __rte_hot
+cnxk_ae_enqueue_ml_dsa_op(struct rte_crypto_op *op, struct roc_ae_buf_ptr *meta_buf,
+ struct cnxk_ae_sess *sess, struct cpt_inst_s *inst)
+{
+ size_t metabuf_len = cnxk_cpt_asym_get_mlen(), reqbuf_len;
+ struct rte_crypto_ml_dsa_op *mldsa = &op->asym->mldsa;
+ enum rte_crypto_auth_algorithm hash;
+ bool sign_deterministic;
+ union cpt_inst_w4 w4;
+ uint16_t param1 = 0;
+ uint32_t dlen = 0;
+ uint16_t param2;
+ uint8_t *dptr;
+ uint8_t minor;
+
+ /* Input buffer */
+ dptr = meta_buf->vaddr;
+ inst->dptr = (uintptr_t)dptr;
+
+ switch (mldsa->op) {
+ case RTE_CRYPTO_ML_DSA_OP_KEYGEN:
+ reqbuf_len = mldsa->keygen.seed.length;
+ if (reqbuf_len > (metabuf_len - dlen)) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -ENOMEM;
+ }
+
+ param2 = sess->ml_dsa_ctx.type;
+
+ memcpy(dptr, mldsa->keygen.seed.data, mldsa->keygen.seed.length);
+ dptr += mldsa->keygen.seed.length;
+ param2 |= (!!mldsa->keygen.seed.length << ROC_RE_ML_DSA_PARAM2_SEED_BIT);
+
+ dlen += mldsa->keygen.seed.length;
+ w4.s.opcode_major = ROC_RE_MAJOR_OP_MLDSA;
+ w4.s.opcode_minor = ROC_RE_MINOR_OP_MLDSA_KEYGEN;
+ break;
+ case RTE_CRYPTO_ML_DSA_OP_SIGN:
+ reqbuf_len = mldsa->siggen.message.length + mldsa->siggen.privkey.length +
+ mldsa->siggen.ctx.length + mldsa->siggen.mu.length +
+ mldsa->siggen.seed.length;
+
+ if (reqbuf_len > (metabuf_len - dlen)) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -ENOMEM;
+ }
+
+ sign_deterministic = sess->ml_dsa_ctx.sign_deterministic;
+ hash = op->asym->mldsa.siggen.hash;
+ minor = ROC_RE_MINOR_OP_MLDSA_SIGN;
+
+ param1 = mldsa->siggen.message.length;
+ param2 = sess->ml_dsa_ctx.type;
+ if (hash == 0) {
+ minor |= (0 << ROC_RE_ML_DSA_MINOR_MSG_TYPE_BIT);
+ } else if (mldsa->siggen.mu.length != 0) {
+ minor |= (3 << ROC_RE_ML_DSA_MINOR_MSG_TYPE_BIT);
+ } else {
+ if (!sess->ml_dsa_ctx.sign_prehash ||
+ hash >= RTE_DIM(mldsa_hash_algo) || mldsa_hash_algo[hash] == 0) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -EINVAL;
+ }
+
+ minor |= (1 << ROC_RE_ML_DSA_MINOR_MSG_TYPE_BIT);
+ param2 |= (mldsa_hash_algo[hash] << ROC_RE_ML_DSA_PARAM2_SIGN_BIT);
+ }
+
+ minor |= ((sign_deterministic ? 0 : 2) << ROC_RE_ML_DSA_MINOR_SIGN_TYPE_BIT);
+
+ if (!sign_deterministic) {
+ if (!mldsa->siggen.seed.length) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -EINVAL;
+ }
+
+ memcpy(dptr, mldsa->siggen.seed.data, mldsa->siggen.seed.length);
+ dptr += mldsa->siggen.seed.length;
+ dlen += mldsa->siggen.seed.length;
+ }
+
+ memcpy(dptr, mldsa->siggen.privkey.data, mldsa->siggen.privkey.length);
+ dptr += mldsa->siggen.privkey.length;
+ dlen += mldsa->siggen.privkey.length;
+
+ memcpy(dptr, mldsa->siggen.ctx.data, mldsa->siggen.ctx.length);
+ dptr += mldsa->siggen.ctx.length;
+ dlen += mldsa->siggen.ctx.length;
+ if (mldsa->siggen.ctx.length > (UINT16_MAX >> ROC_RE_ML_DSA_PARAM2_CTXN_BIT)) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -EINVAL;
+ }
+ param2 |= ((uint16_t)mldsa->siggen.ctx.length
+ << ROC_RE_ML_DSA_PARAM2_CTXN_BIT);
+
+ if (mldsa->siggen.mu.length != 0) {
+ memcpy(dptr, mldsa->siggen.mu.data, mldsa->siggen.mu.length);
+ dptr += mldsa->siggen.mu.length;
+ dlen += mldsa->siggen.mu.length;
+ param1 = mldsa->siggen.mu.length;
+ } else if (mldsa->siggen.message.length != 0) {
+ memcpy(dptr, mldsa->siggen.message.data, mldsa->siggen.message.length);
+ dptr += mldsa->siggen.message.length;
+ dlen += mldsa->siggen.message.length;
+ }
+
+ w4.s.opcode_major = ROC_RE_MAJOR_OP_MLDSA;
+ w4.s.opcode_minor = minor;
+ break;
+ case RTE_CRYPTO_ML_DSA_OP_VERIFY:
+ reqbuf_len = mldsa->sigver.message.length + mldsa->sigver.pubkey.length +
+ mldsa->sigver.ctx.length + mldsa->sigver.mu.length +
+ mldsa->sigver.sign.length;
+
+ if (reqbuf_len > (metabuf_len - dlen)) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -ENOMEM;
+ }
+
+ hash = op->asym->mldsa.sigver.hash;
+ minor = ROC_RE_MINOR_OP_MLDSA_VERIFY;
+
+ param1 = mldsa->sigver.message.length;
+ param2 = sess->ml_dsa_ctx.type;
+ if (hash == 0) {
+ minor |= (0 << ROC_RE_ML_DSA_MINOR_MSG_TYPE_BIT);
+ } else if (mldsa->sigver.mu.length != 0) {
+ minor |= (3 << ROC_RE_ML_DSA_MINOR_MSG_TYPE_BIT);
+ } else {
+ if (!sess->ml_dsa_ctx.sign_prehash ||
+ hash >= RTE_DIM(mldsa_hash_algo) || mldsa_hash_algo[hash] == 0) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -EINVAL;
+ }
+
+ minor |= (1 << ROC_RE_ML_DSA_MINOR_MSG_TYPE_BIT);
+ param2 |= (mldsa_hash_algo[hash] << ROC_RE_ML_DSA_PARAM2_SIGN_BIT);
+ }
+
+ memcpy(dptr, mldsa->sigver.pubkey.data, mldsa->sigver.pubkey.length);
+ dptr += mldsa->sigver.pubkey.length;
+ dlen += mldsa->sigver.pubkey.length;
+
+ memcpy(dptr, mldsa->sigver.ctx.data, mldsa->sigver.ctx.length);
+ dptr += mldsa->sigver.ctx.length;
+ dlen += mldsa->sigver.ctx.length;
+ if (mldsa->sigver.ctx.length > (UINT16_MAX >> ROC_RE_ML_DSA_PARAM2_CTXN_BIT)) {
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -EINVAL;
+ }
+ param2 |= ((uint16_t)mldsa->sigver.ctx.length
+ << ROC_RE_ML_DSA_PARAM2_CTXN_BIT);
+
+ if (mldsa->sigver.mu.length != 0) {
+ memcpy(dptr, mldsa->sigver.mu.data, mldsa->sigver.mu.length);
+ dptr += mldsa->sigver.mu.length;
+ dlen += mldsa->sigver.mu.length;
+ param1 = mldsa->sigver.mu.length;
+ } else if (mldsa->sigver.message.length != 0) {
+ memcpy(dptr, mldsa->sigver.message.data, mldsa->sigver.message.length);
+ dptr += mldsa->sigver.message.length;
+ dlen += mldsa->sigver.message.length;
+ }
+
+ memcpy(dptr, mldsa->sigver.sign.data, mldsa->sigver.sign.length);
+ dptr += mldsa->sigver.sign.length;
+ dlen += mldsa->sigver.sign.length;
+
+ w4.s.opcode_major = ROC_RE_MAJOR_OP_MLDSA;
+ w4.s.opcode_minor = minor;
+ break;
+ default:
+ op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
+ return -EINVAL;
+ }
+
+ w4.s.param1 = param1;
+ w4.s.param2 = param2;
+ w4.s.dlen = dlen;
+
+ inst->w4.u64 = w4.u64;
+
+ /* Reuse entire space of meta buffer as output is large in PQC */
+ inst->rptr = (uintptr_t)meta_buf->vaddr;
+
+ return 0;
+}
+
static __rte_always_inline void
cnxk_ae_ecdsa_sign_prep(struct rte_crypto_ecdsa_op_param *ecdsa,
struct roc_ae_buf_ptr *meta_buf,
@@ -1712,6 +2031,55 @@ cnxk_ae_dequeue_ecdh_op(struct rte_crypto_ecdh_op_param *ecdh, uint8_t *rptr,
}
}
+static __rte_always_inline void
+cnxk_ae_dequeue_mlkem_op(struct rte_crypto_ml_kem_op *mlkem, uint8_t *rptr,
+ enum rte_crypto_ml_kem_type type)
+{
+ switch (mlkem->op) {
+ case RTE_CRYPTO_ML_KEM_OP_KEYGEN:
+ mlkem->keygen.dk.length = rte_crypto_ml_kem_privkey_size[type];
+ memcpy(mlkem->keygen.dk.data, rptr, mlkem->keygen.dk.length);
+ mlkem->keygen.ek.length = rte_crypto_ml_kem_pubkey_size[type];
+ memcpy(mlkem->keygen.ek.data, rptr + 384 * (type + 1), mlkem->keygen.ek.length);
+ break;
+ case RTE_CRYPTO_ML_KEM_OP_ENCAP:
+ mlkem->encap.sk.length = 32;
+ memcpy(mlkem->encap.sk.data, rptr, mlkem->encap.sk.length);
+ mlkem->encap.cipher.length = rte_crypto_ml_kem_cipher_size[type];
+ memcpy(mlkem->encap.cipher.data, rptr + 32, mlkem->encap.cipher.length);
+ break;
+ case RTE_CRYPTO_ML_KEM_OP_DECAP:
+ mlkem->decap.sk.length = 32;
+ memcpy(mlkem->decap.sk.data, rptr, mlkem->decap.sk.length);
+ break;
+ default:
+ break;
+ }
+}
+
+static __rte_always_inline void
+cnxk_ae_dequeue_mldsa_op(struct rte_crypto_ml_dsa_op *mldsa, uint8_t *rptr,
+ enum rte_crypto_ml_dsa_type type)
+{
+ switch (mldsa->op) {
+ case RTE_CRYPTO_ML_DSA_OP_KEYGEN:
+ mldsa->keygen.pubkey.length = rte_crypto_ml_dsa_pubkey_size[type];
+ memcpy(mldsa->keygen.pubkey.data, rptr, mldsa->keygen.pubkey.length);
+ mldsa->keygen.privkey.length = rte_crypto_ml_dsa_privkey_size[type];
+ memcpy(mldsa->keygen.privkey.data, rptr + mldsa->keygen.pubkey.length,
+ mldsa->keygen.privkey.length);
+ break;
+ case RTE_CRYPTO_ML_DSA_OP_SIGN:
+ mldsa->siggen.sign.length = rte_crypto_ml_dsa_sign_size[type];
+ memcpy(mldsa->siggen.sign.data, rptr, mldsa->siggen.sign.length);
+ break;
+ case RTE_CRYPTO_ML_DSA_OP_VERIFY:
+ break;
+ default:
+ break;
+ }
+}
+
static __rte_always_inline void *
cnxk_ae_alloc_meta(struct roc_ae_buf_ptr *buf,
struct rte_mempool *cpt_meta_pool,
@@ -1752,56 +2120,46 @@ cnxk_ae_enqueue(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,
switch (sess->xfrm_type) {
case RTE_CRYPTO_ASYM_XFORM_MODEX:
ret = cnxk_ae_modex_prep(op, &meta_buf, &sess->mod_ctx, inst);
- if (unlikely(ret))
- goto req_fail;
break;
case RTE_CRYPTO_ASYM_XFORM_RSA:
ret = cnxk_ae_enqueue_rsa_op(op, &meta_buf, sess, inst);
- if (unlikely(ret))
- goto req_fail;
break;
case RTE_CRYPTO_ASYM_XFORM_ECDSA:
ret = cnxk_ae_enqueue_ecdsa_op(op, &meta_buf, sess,
sess->cnxk_fpm_iova,
sess->ec_grp, inst);
- if (unlikely(ret))
- goto req_fail;
break;
case RTE_CRYPTO_ASYM_XFORM_EDDSA:
ret = cnxk_ae_enqueue_eddsa_op(op, &meta_buf, sess,
sess->cnxk_fpm_iova,
sess->ec_grp, inst);
- if (unlikely(ret))
- goto req_fail;
break;
case RTE_CRYPTO_ASYM_XFORM_SM2:
ret = cnxk_ae_enqueue_sm2_op(op, &meta_buf, sess,
sess->cnxk_fpm_iova,
sess->ec_grp, inst);
- if (unlikely(ret))
- goto req_fail;
break;
case RTE_CRYPTO_ASYM_XFORM_ECPM:
ret = cnxk_ae_ecpm_prep(&asym_op->ecpm.scalar, &asym_op->ecpm.p, &meta_buf,
sess->ec_grp[sess->ec_ctx.curveid],
sess->ec_ctx.curveid, inst);
- if (unlikely(ret))
- goto req_fail;
break;
case RTE_CRYPTO_ASYM_XFORM_ECFPM:
ret = cnxk_ae_ecfpm_prep(&asym_op->ecpm.scalar, &meta_buf,
sess->cnxk_fpm_iova,
sess->ec_grp[sess->ec_ctx.curveid],
sess->ec_ctx.curveid, inst);
- if (unlikely(ret))
- goto req_fail;
break;
case RTE_CRYPTO_ASYM_XFORM_ECDH:
ret = cnxk_ae_enqueue_ecdh_op(op, &meta_buf, sess,
sess->cnxk_fpm_iova,
sess->ec_grp, inst);
- if (unlikely(ret))
- goto req_fail;
+ break;
+ case RTE_CRYPTO_ASYM_XFORM_ML_KEM:
+ ret = cnxk_ae_enqueue_ml_kem_op(op, &meta_buf, sess, inst);
+ break;
+ case RTE_CRYPTO_ASYM_XFORM_ML_DSA:
+ ret = cnxk_ae_enqueue_ml_dsa_op(op, &meta_buf, sess, inst);
break;
default:
op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
@@ -1809,6 +2167,9 @@ cnxk_ae_enqueue(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,
goto req_fail;
}
+ if (unlikely(ret))
+ goto req_fail;
+
mop = mdata;
mop[0] = inst->rptr;
return 0;
@@ -1852,6 +2213,12 @@ cnxk_ae_post_process(struct rte_crypto_op *cop, struct cnxk_ae_sess *sess,
cnxk_ae_dequeue_ecdh_op(&op->ecdh, rptr, &sess->ec_ctx,
sess->ec_grp, op->flags);
break;
+ case RTE_CRYPTO_ASYM_XFORM_ML_KEM:
+ cnxk_ae_dequeue_mlkem_op(&op->mlkem, rptr, sess->ml_kem_ctx.type);
+ break;
+ case RTE_CRYPTO_ASYM_XFORM_ML_DSA:
+ cnxk_ae_dequeue_mldsa_op(&op->mldsa, rptr, sess->ml_dsa_ctx.type);
+ break;
default:
cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
break;
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.c b/drivers/crypto/cnxk/cnxk_cryptodev.c
index 5828a502e4..de27c4a580 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev.c
@@ -28,6 +28,9 @@ cnxk_cpt_default_ff_get(void)
if (roc_model_is_cn10ka_b0() || roc_model_is_cn10kb() || roc_model_is_cn20k())
ff |= RTE_CRYPTODEV_FF_SECURITY_RX_INJECT;
+ if (roc_model_is_cn20k())
+ ff |= RTE_CRYPTODEV_FF_MLDSA_SIGN_PREHASH;
+
return ff;
}
@@ -56,6 +59,14 @@ cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt)
return -ENOTSUP;
}
+ if (roc_model_is_cn20k()) {
+ ret = roc_cpt_eng_grp_add(roc_cpt, CPT_ENG_TYPE_RE);
+ if (ret < 0) {
+ plt_err("Could not add CPT RE engines");
+ return ret;
+ }
+ }
+
return 0;
}
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h
index f88162ad3c..bdc5752905 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev.h
+++ b/drivers/crypto/cnxk/cnxk_cryptodev.h
@@ -10,8 +10,9 @@
#include "roc_ae.h"
#include "roc_cpt.h"
+#include "roc_re_ml_tables.h"
-#define CNXK_CPT_MAX_CAPS 60
+#define CNXK_CPT_MAX_CAPS 62
#define CNXK_SEC_IPSEC_CRYPTO_MAX_CAPS 16
#define CNXK_SEC_TLS_1_3_CRYPTO_MAX_CAPS 3
#define CNXK_SEC_TLS_1_2_CRYPTO_MAX_CAPS 7
@@ -33,6 +34,7 @@ struct cnxk_cpt_vf {
sec_dtls_1_2_crypto_caps[CNXK_SEC_TLS_1_2_CRYPTO_MAX_CAPS];
struct rte_security_capability sec_caps[CNXK_SEC_MAX_CAPS];
uint64_t cnxk_fpm_iova[ROC_AE_EC_ID_PMAX];
+ uint64_t cnxk_ml_iova[ROC_RE_ML_ZETA_IDX_MAX];
struct roc_ae_ec_group *ec_grp[ROC_AE_EC_ID_PMAX];
uint16_t max_qps_limit;
uint16_t rx_inject_qp;
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
index be6d383717..736d588bde 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
@@ -129,6 +129,63 @@ static const struct rte_cryptodev_capabilities caps_mul[] = {
},
};
+static const struct rte_cryptodev_capabilities caps_pqc[] = {
+ {
+ /* ML-KEM */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ .asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_ML_KEM,
+ .op_types =
+ ((1 << RTE_CRYPTO_ML_KEM_OP_KEYGEN) |
+ (1 << RTE_CRYPTO_ML_KEM_OP_ENCAP) |
+ (1 << RTE_CRYPTO_ML_KEM_OP_DECAP)),
+ .mlkem_capa = {
+ [RTE_CRYPTO_ML_KEM_OP_KEYGEN] =
+ (1 << RTE_CRYPTO_ML_KEM_512) |
+ (1 << RTE_CRYPTO_ML_KEM_768) |
+ (1 << RTE_CRYPTO_ML_KEM_1024),
+ [RTE_CRYPTO_ML_KEM_OP_ENCAP] =
+ (1 << RTE_CRYPTO_ML_KEM_512) |
+ (1 << RTE_CRYPTO_ML_KEM_768) |
+ (1 << RTE_CRYPTO_ML_KEM_1024),
+ [RTE_CRYPTO_ML_KEM_OP_DECAP] =
+ (1 << RTE_CRYPTO_ML_KEM_512) |
+ (1 << RTE_CRYPTO_ML_KEM_768) |
+ (1 << RTE_CRYPTO_ML_KEM_1024)
+ }
+ }
+ }
+ },
+ {
+ /* ML-DSA */
+ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,
+ .asym = {
+ .xform_capa = {
+ .xform_type = RTE_CRYPTO_ASYM_XFORM_ML_DSA,
+ .op_types =
+ ((1 << RTE_CRYPTO_ML_DSA_OP_SIGN) |
+ (1 << RTE_CRYPTO_ML_DSA_OP_KEYGEN) |
+ (1 << RTE_CRYPTO_ML_DSA_OP_VERIFY)),
+ .mldsa_capa = {
+ [RTE_CRYPTO_ML_DSA_OP_KEYGEN] =
+ (1 << RTE_CRYPTO_ML_DSA_44) |
+ (1 << RTE_CRYPTO_ML_DSA_65) |
+ (1 << RTE_CRYPTO_ML_DSA_87),
+ [RTE_CRYPTO_ML_DSA_OP_SIGN] =
+ (1 << RTE_CRYPTO_ML_DSA_44) |
+ (1 << RTE_CRYPTO_ML_DSA_65) |
+ (1 << RTE_CRYPTO_ML_DSA_87),
+ [RTE_CRYPTO_ML_DSA_OP_VERIFY] =
+ (1 << RTE_CRYPTO_ML_DSA_44) |
+ (1 << RTE_CRYPTO_ML_DSA_65) |
+ (1 << RTE_CRYPTO_ML_DSA_87)
+ }
+ }
+ }
+ },
+};
+
static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {
{ /* SHA1 */
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -2079,10 +2136,13 @@ crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[],
if (roc_model_is_cn10k() || roc_model_is_cn20k())
cn10k_20k_crypto_caps_add(cnxk_caps, hw_caps, &cur_pos);
- if (roc_model_is_cn20k())
+ if (roc_model_is_cn20k()) {
CPT_CAPS_ADD(cnxk_caps, &cur_pos, hw_caps, zuc256_snow5g);
+ cpt_caps_add(cnxk_caps, &cur_pos, caps_pqc, RTE_DIM(caps_pqc));
+ }
cpt_caps_add(cnxk_caps, &cur_pos, caps_null, RTE_DIM(caps_null));
+
cpt_caps_add(cnxk_caps, &cur_pos, caps_end, RTE_DIM(caps_end));
if (roc_model_is_cn10k() || roc_model_is_cn20k())
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index d3cf1ddd57..ab4115d4dd 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -23,6 +23,7 @@
#else
#include "roc_io_generic.h"
#endif
+#include "roc_re_ml_tables.h"
#include "cnxk_ae.h"
#include "cnxk_cryptodev.h"
@@ -41,6 +42,14 @@
#define CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS 5
#define CNXK_CPT_MAX_ASYM_OP_MOD_LEN 1024
+
+/*
+ * PQC requests currently use a shared metabuf region for concatenated input
+ * and output. ML-DSA-87 SIGN requires at least 9523 bytes for private key
+ * input plus signature output, along with additional space for message and
+ * context parameters, so set it for the possible max.
+ */
+#define CNXK_CPT_MAX_ASYM_OP_PQC_LEN 16384
#define CNXK_CPT_META_BUF_MAX_CACHE_SIZE 128
static_assert((uint16_t)RTE_PMD_CNXK_AE_EC_ID_P192 == (uint16_t)ROC_AE_EC_ID_P192,
@@ -107,7 +116,10 @@ cnxk_cpt_asym_get_mlen(void)
len = sizeof(uint64_t);
/* Get meta len for asymmetric operations */
- len += CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS * CNXK_CPT_MAX_ASYM_OP_MOD_LEN;
+ if (roc_model_is_cn20k())
+ len += CNXK_CPT_MAX_ASYM_OP_PQC_LEN;
+ else
+ len += CNXK_CPT_MAX_ASYM_OP_NUM_PARAMS * CNXK_CPT_MAX_ASYM_OP_MOD_LEN;
return len;
}
@@ -121,6 +133,8 @@ cnxk_cpt_dev_clear(struct rte_cryptodev *dev)
if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
roc_ae_fpm_put();
roc_ae_ec_grp_put();
+ if (roc_model_is_cn20k())
+ roc_re_ml_zeta_put();
}
ret = roc_cpt_int_misc_cb_unregister(cnxk_cpt_int_misc_cb, NULL);
@@ -182,8 +196,15 @@ cnxk_cpt_dev_config(struct rte_cryptodev *dev, struct rte_cryptodev_config *conf
ret = roc_ae_ec_grp_get(vf->ec_grp);
if (ret) {
plt_err("Could not get EC grp table");
- roc_ae_fpm_put();
- return ret;
+ goto fpm_put;
+ }
+
+ if (roc_model_is_cn20k()) {
+ ret = roc_re_ml_zeta_get(vf->cnxk_ml_iova);
+ if (ret) {
+ plt_err("Could not initialize RE ML lookup table");
+ goto ec_grp_put;
+ }
}
}
roc_cpt->opaque = dev;
@@ -191,6 +212,12 @@ cnxk_cpt_dev_config(struct rte_cryptodev *dev, struct rte_cryptodev_config *conf
roc_cpt_int_misc_cb_register(cnxk_cpt_int_misc_cb, NULL);
return 0;
+
+ec_grp_put:
+ roc_ae_ec_grp_put();
+fpm_put:
+ roc_ae_fpm_put();
+ return ret;
}
int
@@ -992,7 +1019,16 @@ cnxk_ae_session_cfg(struct rte_cryptodev *dev, struct rte_crypto_asym_xform *xfo
priv->lf = roc_cpt->lf[0];
w7.u64 = 0;
- w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_AE];
+ if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_ML_KEM) {
+ w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_RE];
+ w7.s.cptr = rte_cpu_to_be_64(vf->cnxk_ml_iova[ROC_RE_ML_ZETA_IDX_KEM]);
+ } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_ML_DSA) {
+ w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_RE];
+ w7.s.cptr = rte_cpu_to_be_64(vf->cnxk_ml_iova[ROC_RE_ML_ZETA_IDX_DSA]);
+ } else {
+ w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_AE];
+ w7.s.cptr = 0;
+ }
if (roc_errata_cpt_hang_on_mixed_ctx_val()) {
hwc = &priv->hw_ctx;
@@ -1007,6 +1043,7 @@ cnxk_ae_session_cfg(struct rte_cryptodev *dev, struct rte_crypto_asym_xform *xfo
priv->cpt_inst_w7 = w7.u64;
priv->cnxk_fpm_iova = vf->cnxk_fpm_iova;
+ priv->cnxk_ml_iova = vf->cnxk_ml_iova;
priv->ec_grp = vf->ec_grp;
return 0;
--
2.37.1
^ permalink raw reply related
* RE: [PATCH] crypto/cnxk: fix out of place AES GCM
From: Tejasree Kondoj @ 2026-06-21 8:46 UTC (permalink / raw)
To: Daphne Priscilla F, dev@dpdk.org
Cc: stable@dpdk.org, Akhil Goyal, Anoob Joseph, Daphne Priscilla F
In-Reply-To: <20260612062009.3587783-1-df@marvell.com>
Acked-by: Tejasree Kondoj <ktejasree@marvell.com>
> -----Original Message-----
> From: Daphne Priscilla <df@marvell.com>
> Sent: Friday, June 12, 2026 11:50 AM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Akhil Goyal <gakhil@marvell.com>; Tejasree Kondoj
> <ktejasree@marvell.com>; Anoob Joseph <anoobj@marvell.com>; Daphne
> Priscilla F <df@marvell.com>
> Subject: [PATCH] crypto/cnxk: fix out of place AES GCM
>
> For AES-GCM out of place, when AAD is present in inbuf before the data, it is
> treated as passthrough data. This results in AAD being present in outbuf
> header, but test expects outbuf header to remain zero. Passthrough data is
> now diverted to metabuf so outbuf header remains zero.
>
> Fixes: 7c19abdd0cf1 ("common/cnxk: support 103XX CPT")
> Cc: stable@dpdk.org
>
> Signed-off-by: Daphne Priscilla <df@marvell.com>
> ---
> .mailmap | 1 +
> drivers/common/cnxk/roc_se.h | 2 +-
> drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 3 +
> drivers/crypto/cnxk/cnxk_se.h | 96 ++++++++++++++++++++++--
> 4 files changed, 93 insertions(+), 9 deletions(-)
>
> diff --git a/.mailmap b/.mailmap
> index 118dfa0ff9..1191afbf0b 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -334,6 +334,7 @@ Danny Patel <dannyp@marvell.com> Danny Zhou
> <danny.zhou@intel.com> Danylo Vodopianov <dvo-plv@napatech.com>
> Dapeng Yu <dapengx.yu@intel.com>
> +Daphne Priscilla <df@marvell.com>
> Darek Stojaczyk <dariusz.stojaczyk@intel.com> Daria Kolistratova
> <daria.kolistratova@intel.com> Dariusz Chaberski
> <dariuszx.chaberski@intel.com> diff --git a/drivers/common/cnxk/roc_se.h
> b/drivers/common/cnxk/roc_se.h index 499e71ce85..d3ad61ca04 100644
> --- a/drivers/common/cnxk/roc_se.h
> +++ b/drivers/common/cnxk/roc_se.h
> @@ -26,7 +26,7 @@
> #define ROC_SE_MISC_MINOR_OP_DUMMY 0x04ULL
> #define ROC_SE_MISC_MINOR_OP_HW_SUPPORT 0x08ULL
>
> -#define ROC_SE_MAX_AAD_SIZE 64
> +#define ROC_SE_MAX_AAD_SIZE 1024
> #define ROC_SE_MAX_MAC_LEN 64
>
> #define ROC_SE_OFF_CTRL_LEN 8
> diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
> b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
> index 2f9eb322dc..5e59f1d7bd 100644
> --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
> +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
> @@ -82,6 +82,9 @@ cnxk_cpt_get_mlen(void)
> (RTE_ALIGN_CEIL(ROC_MAX_SG_IN_OUT_CNT, 4)
> >> 2) * ROC_SG_ENTRY_SIZE),
> 8);
>
> + /* Space for discarding AAD bytes from output stream in GCM OOP */
> + len += ROC_SE_MAX_AAD_SIZE;
> +
> return len;
> }
>
> diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h
> index 8dbf3e73c7..09d9d1e0e3 100644
> --- a/drivers/crypto/cnxk/cnxk_se.h
> +++ b/drivers/crypto/cnxk/cnxk_se.h
> @@ -407,8 +407,28 @@ sg_inst_prep(struct roc_se_fc_params *params,
> struct cpt_inst_s *inst, uint64_t
> if (unlikely(req_flags &
> ROC_SE_SINGLE_BUF_INPLACE)) {
> i =
> fill_sg_comp_from_buf_min(scatter_comp, i, params->bufs, &size);
> } else {
> - i = fill_sg_comp_from_iov(scatter_comp, i,
> params->dst_iov, 0,
> - &size, aad_buf,
> aad_offset);
> + uint32_t dst_offset = 0;
> +
> + if (passthrough_len) {
> + if (unlikely(passthrough_len >
> ROC_SE_MAX_AAD_SIZE)) {
> + plt_dp_err(
> + "Passthrough length
> %u exceeds reserved space %u",
> + passthrough_len,
> ROC_SE_MAX_AAD_SIZE);
> + return -1;
> + }
> + uint64_t meta_passthrough =
> + (uint64_t)params-
> >meta_buf.vaddr +
> + params->meta_buf.size -
> ROC_SE_MAX_AAD_SIZE;
> + i = fill_sg_comp(scatter_comp, i,
> meta_passthrough,
> + passthrough_len);
> + size -= passthrough_len;
> + dst_offset = passthrough_len;
> + aad_offset = 0;
> + }
> + if (size)
> + i =
> fill_sg_comp_from_iov(scatter_comp, i, params->dst_iov,
> + dst_offset,
> &size, aad_buf,
> + aad_offset);
> }
> if (unlikely(size)) {
> plt_dp_err("Insufficient buffer space,"
> @@ -430,8 +450,28 @@ sg_inst_prep(struct roc_se_fc_params *params,
> struct cpt_inst_s *inst, uint64_t
> if (unlikely(req_flags &
> ROC_SE_SINGLE_BUF_INPLACE)) {
> i =
> fill_sg_comp_from_buf_min(scatter_comp, i, params->bufs, &size);
> } else {
> - i = fill_sg_comp_from_iov(scatter_comp, i,
> params->dst_iov, 0,
> - &size, aad_buf,
> aad_offset);
> + uint32_t dst_offset = 0;
> +
> + if (passthrough_len) {
> + if (unlikely(passthrough_len >
> ROC_SE_MAX_AAD_SIZE)) {
> + plt_dp_err(
> + "Passthrough length
> %u exceeds reserved space %u",
> + passthrough_len,
> ROC_SE_MAX_AAD_SIZE);
> + return -1;
> + }
> + uint64_t meta_passthrough =
> + (uint64_t)params-
> >meta_buf.vaddr +
> + params->meta_buf.size -
> ROC_SE_MAX_AAD_SIZE;
> + i = fill_sg_comp(scatter_comp, i,
> meta_passthrough,
> + passthrough_len);
> + size -= passthrough_len;
> + dst_offset = passthrough_len;
> + aad_offset = 0;
> + }
> + if (size)
> + i =
> fill_sg_comp_from_iov(scatter_comp, i, params->dst_iov,
> + dst_offset,
> &size, aad_buf,
> + aad_offset);
> }
>
> if (unlikely(size)) {
> @@ -606,8 +646,28 @@ sg2_inst_prep(struct roc_se_fc_params *params,
> struct cpt_inst_s *inst, uint64_t
> i =
> fill_sg2_comp_from_buf_min(scatter_comp, i, params->bufs,
> &size);
> } else {
> - i = fill_sg2_comp_from_iov(scatter_comp, i,
> params->dst_iov, 0,
> - &size, aad_buf,
> aad_offset);
> + uint32_t dst_offset = 0;
> +
> + if (passthrough_len) {
> + if (unlikely(passthrough_len >
> ROC_SE_MAX_AAD_SIZE)) {
> + plt_dp_err(
> + "Passthrough length
> %u exceeds reserved space %u",
> + passthrough_len,
> ROC_SE_MAX_AAD_SIZE);
> + return -1;
> + }
> + uint64_t meta_passthrough =
> + (uint64_t)params-
> >meta_buf.vaddr +
> + params->meta_buf.size -
> ROC_SE_MAX_AAD_SIZE;
> + i = fill_sg2_comp(scatter_comp, i,
> meta_passthrough,
> + passthrough_len);
> + size -= passthrough_len;
> + dst_offset = passthrough_len;
> + aad_offset = 0;
> + }
> + if (size)
> + i =
> fill_sg2_comp_from_iov(scatter_comp, i, params->dst_iov,
> + dst_offset,
> &size, aad_buf,
> + aad_offset);
> }
> if (unlikely(size)) {
> plt_dp_err("Insufficient buffer space,"
> @@ -632,8 +692,28 @@ sg2_inst_prep(struct roc_se_fc_params *params,
> struct cpt_inst_s *inst, uint64_t
> i =
> fill_sg2_comp_from_buf_min(scatter_comp, i, params->bufs,
> &size);
> } else {
> - i = fill_sg2_comp_from_iov(scatter_comp, i,
> params->dst_iov, 0,
> - &size, aad_buf,
> aad_offset);
> + uint32_t dst_offset = 0;
> +
> + if (passthrough_len) {
> + if (unlikely(passthrough_len >
> ROC_SE_MAX_AAD_SIZE)) {
> + plt_dp_err(
> + "Passthrough length
> %u exceeds reserved space %u",
> + passthrough_len,
> ROC_SE_MAX_AAD_SIZE);
> + return -1;
> + }
> + uint64_t meta_passthrough =
> + (uint64_t)params-
> >meta_buf.vaddr +
> + params->meta_buf.size -
> ROC_SE_MAX_AAD_SIZE;
> + i = fill_sg2_comp(scatter_comp, i,
> meta_passthrough,
> + passthrough_len);
> + size -= passthrough_len;
> + dst_offset = passthrough_len;
> + aad_offset = 0;
> + }
> + if (size)
> + i =
> fill_sg2_comp_from_iov(scatter_comp, i, params->dst_iov,
> + dst_offset,
> &size, aad_buf,
> + aad_offset);
> }
>
> if (unlikely(size)) {
> --
> 2.43.0
^ permalink raw reply
* [PATCH v2 00/19] dpaa: bus, net, dma and mempool improvements
From: Hemant Agrawal @ 2026-06-21 10:16 UTC (permalink / raw)
To: stephen, david.marchand, dev
In-Reply-To: <20260619122922.3774666-1-hemant.agrawal@nxp.com>
v2: fix checkpatch error and apply it over main branch
This series collects correctness fixes, cleanups and feature additions
across the NXP DPAA bus, net, mempool and DMA drivers.
1. Bus/fman infrastructure cleanups (patches 01, 02, 13)
- Refine fman symbol naming and fix unintended global scope.
- Scan the maximum BPID count from the device tree rather than
using a compile-time constant.
- Improve the DPAA bus log macro and fix bus-detection logic.
2. BMI Tx statistics (patch 03)
- Extend fman_hw to read Tx BMI registers and expose the counters
through the xstats interface.
3. Process-type guards (patch 04)
- Add secondary-process checks in the net, DMA and crypto drivers
to prevent segfaults when operations valid only in the primary
process are called from a secondary.
4. FQ shutdown hardening (patches 05-11)
- Introduce helpers for qman channel and work-queue lookup so that
FQ teardown is driven by the FQ descriptor instead of ad-hoc
parameters.
- Add channel validation and CGR cleanup to the shutdown path.
- Clean up the Tx-confirmation FQ on device stop and remove a
redundant shutdown call from Rx queue setup.
5. net/dpaa improvements (patches 12, 14, 15)
- Optimise FM de-configuration to avoid redundant portal drains.
- Streamline FMC MAC-type parsing.
- Report an error when deferred-start mode is requested (not
supported by the driver).
6. mempool/dpaa (patches 16-17)
- Optimise multi-entry buffer-pool acquire/release operations.
- Release the BPID in the driver destructor to avoid resource leaks
across repeated bind/unbind cycles.
7. dma/dpaa (patch 18)
- Add SG-list data validation and a workaround for erratum
ERR050757.
8. net/dpaa ONIC support (patch 19)
- Add port-type checks for ONIC (Open Network Interface Card)
shared-Ethernet ports.
Gagandeep Singh (2):
bus/dpaa: enhance DPAA FQ shutdown
dma/dpaa: add SG data validation and ERR050757 fix
Hemant Agrawal (5):
net/dpaa: clean Tx confirmation FQ on device stop
net/dpaa: remove redundant FQ shutdown from Rx queue setup
net/dpaa: optimize FM deconfig
bus/dpaa: improve log macro and fix bus detection
net/dpaa: report error on using deferred start
Jun Yang (10):
bus/dpaa: refine fman naming and fix global scope
bus/dpaa: scan max BPID from DTS
drivers: add BMI Tx statistics
bus/dpaa: define helpers for qman channel and wq
drivers: shutdown DPAA FQ by fq descriptor
bus/dpaa: improve FQ shutdown with channel validation
drivers: add DPAA cgrid cleanup support
net/dpaa: optimize FMC MAC type parsing
drivers: optimize DPAA multi-entry buffer pool operations
drivers: release DPAA bpid on driver destructor
Prashant Gupta (1):
drivers: add process-type guards for secondary process
Vanshika Shukla (1):
net/dpaa: add ONIC port checks
drivers/bus/dpaa/base/fman/fman.c | 23 ++--
drivers/bus/dpaa/base/fman/fman_hw.c | 108 ++++++++---------
drivers/bus/dpaa/base/qbman/bman.c | 57 +++------
drivers/bus/dpaa/base/qbman/bman_driver.c | 48 +++++---
drivers/bus/dpaa/base/qbman/qman.c | 115 ++++++++++--------
drivers/bus/dpaa/base/qbman/qman.h | 23 +++-
drivers/bus/dpaa/base/qbman/qman_driver.c | 29 ++++-
drivers/bus/dpaa/dpaa_bus.c | 35 ++++--
drivers/bus/dpaa/dpaa_bus_base_symbols.c | 4 +
drivers/bus/dpaa/include/fman.h | 30 ++++-
drivers/bus/dpaa/include/fsl_bman.h | 49 ++++++--
drivers/bus/dpaa/include/fsl_qman.h | 22 +++-
drivers/crypto/dpaa_sec/dpaa_sec.c | 3 -
drivers/dma/dpaa/dpaa_qdma.c | 103 ++++++++++++----
drivers/mempool/dpaa/dpaa_mempool.c | 75 ++++++++++--
drivers/mempool/dpaa/dpaa_mempool.h | 3 +-
drivers/net/dpaa/dpaa_ethdev.c | 132 ++++++++++++++++-----
drivers/net/dpaa/dpaa_ethdev.h | 22 +++-
drivers/net/dpaa/dpaa_flow.c | 137 +++++++++++++---------
drivers/net/dpaa/dpaa_flow.h | 7 +-
drivers/net/dpaa/dpaa_fmc.c | 73 +++++++-----
21 files changed, 746 insertions(+), 352 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH v2 01/19] bus/dpaa: refine fman naming and fix global scope
From: Hemant Agrawal @ 2026-06-21 10:16 UTC (permalink / raw)
To: stephen, david.marchand, dev; +Cc: Jun Yang
In-Reply-To: <20260621101651.1081425-1-hemant.agrawal@nxp.com>
From: Jun Yang <jun.yang@nxp.com>
Rename ccsr_map to memac_map in __fman_if struct for clarity,
as it maps the MEMAC register space not generic CCSR.
Rename bmi_map to rx_bmi_map to distinguish from TX BMI.
Make fman_ccsr_map_fd static as it is only used within fman.c.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
drivers/bus/dpaa/base/fman/fman.c | 14 ++--
drivers/bus/dpaa/base/fman/fman_hw.c | 106 ++++++++++++++-------------
drivers/bus/dpaa/include/fman.h | 6 +-
3 files changed, 63 insertions(+), 63 deletions(-)
diff --git a/drivers/bus/dpaa/base/fman/fman.c b/drivers/bus/dpaa/base/fman/fman.c
index 55311235f5..55f466d751 100644
--- a/drivers/bus/dpaa/base/fman/fman.c
+++ b/drivers/bus/dpaa/base/fman/fman.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
*
* Copyright 2010-2016 Freescale Semiconductor Inc.
- * Copyright 2017-2024 NXP
+ * Copyright 2017-2026 NXP
*
*/
@@ -465,9 +465,9 @@ fman_if_init(const struct device_node *dpa_node, int fd)
mname, regs_addr);
goto err;
}
- __if->ccsr_map = mmap(NULL, __if->regs_size,
+ __if->memac_map = mmap(NULL, __if->regs_size,
PROT_READ | PROT_WRITE, MAP_SHARED, fd, phys_addr);
- if (__if->ccsr_map == MAP_FAILED) {
+ if (__if->memac_map == MAP_FAILED) {
FMAN_ERR(-errno, "mmap(0x%"PRIx64")", phys_addr);
goto err;
}
@@ -599,9 +599,9 @@ fman_if_init(const struct device_node *dpa_node, int fd)
goto err;
}
- __if->bmi_map = mmap(NULL, __if->regs_size,
+ __if->rx_bmi_map = mmap(NULL, __if->regs_size,
PROT_READ | PROT_WRITE, MAP_SHARED, fd, phys_addr);
- if (__if->bmi_map == MAP_FAILED) {
+ if (__if->rx_bmi_map == MAP_FAILED) {
FMAN_ERR(-errno, "mmap(0x%"PRIx64")", phys_addr);
goto err;
}
@@ -1167,13 +1167,13 @@ fman_finish(void)
}
/* disable Rx and Tx */
- regs = __if->ccsr_map;
+ regs = __if->memac_map;
cfg = in_be32(®s->command_config);
out_be32(®s->command_config,
cfg & (~(MEMAC_RX_ENABLE | MEMAC_TX_ENABLE)));
/* release the mapping */
- _errno = munmap(__if->ccsr_map, __if->regs_size);
+ _errno = munmap(__if->memac_map, __if->regs_size);
if (unlikely(_errno < 0))
FMAN_ERR(_errno, "munmap() = (%s)", strerror(errno));
DPAA_BUS_INFO("Tearing down %s", __if->node_path);
diff --git a/drivers/bus/dpaa/base/fman/fman_hw.c b/drivers/bus/dpaa/base/fman/fman_hw.c
index cbb0491d70..ce68581555 100644
--- a/drivers/bus/dpaa/base/fman/fman_hw.c
+++ b/drivers/bus/dpaa/base/fman/fman_hw.c
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright 2017,2020,2022-2023 NXP
+ * Copyright 2017,2020,2022-2023,2026 NXP
*
*/
@@ -16,6 +16,8 @@
#include <fsl_fman_crc64.h>
#include <fsl_bman.h>
+extern int fman_ccsr_map_fd;
+
#define FMAN_SP_SG_DISABLE 0x80000000
#define FMAN_SP_EXT_BUF_MARG_START_SHIFT 16
@@ -39,7 +41,7 @@ fman_if_set_mcast_filter_table(struct fman_if *p)
void *hashtable_ctrl;
uint32_t i;
- hashtable_ctrl = &((struct memac_regs *)__if->ccsr_map)->hashtable_ctrl;
+ hashtable_ctrl = &((struct memac_regs *)__if->memac_map)->hashtable_ctrl;
for (i = 0; i < 64; i++)
out_be32(hashtable_ctrl, i|HASH_CTRL_MCAST_EN);
}
@@ -51,7 +53,7 @@ fman_if_reset_mcast_filter_table(struct fman_if *p)
void *hashtable_ctrl;
uint32_t i;
- hashtable_ctrl = &((struct memac_regs *)__if->ccsr_map)->hashtable_ctrl;
+ hashtable_ctrl = &((struct memac_regs *)__if->memac_map)->hashtable_ctrl;
for (i = 0; i < 64; i++)
out_be32(hashtable_ctrl, i & ~HASH_CTRL_MCAST_EN);
}
@@ -101,7 +103,7 @@ fman_if_add_hash_mac_addr(struct fman_if *p, uint8_t *eth)
hash = get_mac_hash_code(eth_addr) & HASH_CTRL_ADDR_MASK;
hash = hash | HASH_CTRL_MCAST_EN;
- hashtable_ctrl = &((struct memac_regs *)__if->ccsr_map)->hashtable_ctrl;
+ hashtable_ctrl = &((struct memac_regs *)__if->memac_map)->hashtable_ctrl;
out_be32(hashtable_ctrl, hash);
return 0;
@@ -112,7 +114,7 @@ fman_if_get_primary_mac_addr(struct fman_if *p, uint8_t *eth)
{
struct __fman_if *__if = container_of(p, struct __fman_if, __if);
void *mac_reg =
- &((struct memac_regs *)__if->ccsr_map)->mac_addr0.mac_addr_l;
+ &((struct memac_regs *)__if->memac_map)->mac_addr0.mac_addr_l;
u32 val = in_be32(mac_reg);
int i;
@@ -130,7 +132,7 @@ fman_if_get_primary_mac_addr(struct fman_if *p, uint8_t *eth)
eth[2] = (val & 0x00ff0000) >> 16;
eth[3] = (val & 0xff000000) >> 24;
- mac_reg = &((struct memac_regs *)__if->ccsr_map)->mac_addr0.mac_addr_u;
+ mac_reg = &((struct memac_regs *)__if->memac_map)->mac_addr0.mac_addr_u;
val = in_be32(mac_reg);
eth[4] = (val & 0x000000ff) >> 0;
@@ -151,16 +153,16 @@ fman_if_clear_mac_addr(struct fman_if *p, uint8_t addr_num)
return;
if (addr_num) {
- reg = &((struct memac_regs *)m->ccsr_map)->
+ reg = &((struct memac_regs *)m->memac_map)->
mac_addr[addr_num-1].mac_addr_l;
out_be32(reg, 0x0);
- reg = &((struct memac_regs *)m->ccsr_map)->
+ reg = &((struct memac_regs *)m->memac_map)->
mac_addr[addr_num-1].mac_addr_u;
out_be32(reg, 0x0);
} else {
- reg = &((struct memac_regs *)m->ccsr_map)->mac_addr0.mac_addr_l;
+ reg = &((struct memac_regs *)m->memac_map)->mac_addr0.mac_addr_l;
out_be32(reg, 0x0);
- reg = &((struct memac_regs *)m->ccsr_map)->mac_addr0.mac_addr_u;
+ reg = &((struct memac_regs *)m->memac_map)->mac_addr0.mac_addr_u;
out_be32(reg, 0x0);
}
}
@@ -180,10 +182,10 @@ fman_if_add_mac_addr(struct fman_if *p, uint8_t *eth, uint8_t addr_num)
memcpy(&m->__if.mac_addr, eth, ETHER_ADDR_LEN);
if (addr_num)
- reg = &((struct memac_regs *)m->ccsr_map)->
+ reg = &((struct memac_regs *)m->memac_map)->
mac_addr[addr_num-1].mac_addr_l;
else
- reg = &((struct memac_regs *)m->ccsr_map)->mac_addr0.mac_addr_l;
+ reg = &((struct memac_regs *)m->memac_map)->mac_addr0.mac_addr_l;
val = (m->__if.mac_addr.addr_bytes[0] |
(m->__if.mac_addr.addr_bytes[1] << 8) |
@@ -192,10 +194,10 @@ fman_if_add_mac_addr(struct fman_if *p, uint8_t *eth, uint8_t addr_num)
out_be32(reg, val);
if (addr_num)
- reg = &((struct memac_regs *)m->ccsr_map)->
+ reg = &((struct memac_regs *)m->memac_map)->
mac_addr[addr_num-1].mac_addr_u;
else
- reg = &((struct memac_regs *)m->ccsr_map)->mac_addr0.mac_addr_u;
+ reg = &((struct memac_regs *)m->memac_map)->mac_addr0.mac_addr_u;
val = ((m->__if.mac_addr.addr_bytes[4] << 0) |
(m->__if.mac_addr.addr_bytes[5] << 8));
@@ -214,7 +216,7 @@ fman_if_set_rx_ignore_pause_frames(struct fman_if *p, bool enable)
assert(fman_ccsr_map_fd != -1);
/* Set Rx Ignore Pause Frames */
- cmdcfg = &((struct memac_regs *)__if->ccsr_map)->command_config;
+ cmdcfg = &((struct memac_regs *)__if->memac_map)->command_config;
if (enable)
value = in_be32(cmdcfg) | CMD_CFG_PAUSE_IGNORE;
else
@@ -232,7 +234,7 @@ fman_if_conf_max_frame_len(struct fman_if *p, unsigned int max_frame_len)
assert(fman_ccsr_map_fd != -1);
/* Set Max frame length */
- maxfrm = &((struct memac_regs *)__if->ccsr_map)->maxfrm;
+ maxfrm = &((struct memac_regs *)__if->memac_map)->maxfrm;
out_be32(maxfrm, (MAXFRM_RX_MASK & max_frame_len));
}
@@ -240,7 +242,7 @@ void
fman_if_stats_get(struct fman_if *p, struct rte_eth_stats *stats)
{
struct __fman_if *m = container_of(p, struct __fman_if, __if);
- struct memac_regs *regs = m->ccsr_map;
+ struct memac_regs *regs = m->memac_map;
/* read recved packet count */
stats->ipackets = (u64)in_be32(®s->rfrm_l) |
@@ -263,7 +265,7 @@ void
fman_if_stats_get_all(struct fman_if *p, uint64_t *value, int n)
{
struct __fman_if *m = container_of(p, struct __fman_if, __if);
- struct memac_regs *regs = m->ccsr_map;
+ struct memac_regs *regs = m->memac_map;
int i;
uint64_t base_offset = offsetof(struct memac_regs, reoct_l);
@@ -278,7 +280,7 @@ void
fman_if_stats_reset(struct fman_if *p)
{
struct __fman_if *m = container_of(p, struct __fman_if, __if);
- struct memac_regs *regs = m->ccsr_map;
+ struct memac_regs *regs = m->memac_map;
uint32_t tmp;
tmp = in_be32(®s->statn_config);
@@ -295,7 +297,7 @@ void
fman_if_bmi_stats_enable(struct fman_if *p)
{
struct __fman_if *m = container_of(p, struct __fman_if, __if);
- struct rx_bmi_regs *regs = (struct rx_bmi_regs *)m->bmi_map;
+ struct rx_bmi_regs *regs = (struct rx_bmi_regs *)m->rx_bmi_map;
uint32_t tmp;
tmp = in_be32(®s->fmbm_rstc);
@@ -309,7 +311,7 @@ void
fman_if_bmi_stats_disable(struct fman_if *p)
{
struct __fman_if *m = container_of(p, struct __fman_if, __if);
- struct rx_bmi_regs *regs = (struct rx_bmi_regs *)m->bmi_map;
+ struct rx_bmi_regs *regs = (struct rx_bmi_regs *)m->rx_bmi_map;
uint32_t tmp;
tmp = in_be32(®s->fmbm_rstc);
@@ -323,7 +325,7 @@ void
fman_if_bmi_stats_get_all(struct fman_if *p, uint64_t *value)
{
struct __fman_if *m = container_of(p, struct __fman_if, __if);
- struct rx_bmi_regs *regs = (struct rx_bmi_regs *)m->bmi_map;
+ struct rx_bmi_regs *regs = (struct rx_bmi_regs *)m->rx_bmi_map;
int i = 0;
value[i++] = (u32)in_be32(®s->fmbm_rfrc);
@@ -340,7 +342,7 @@ void
fman_if_bmi_stats_reset(struct fman_if *p)
{
struct __fman_if *m = container_of(p, struct __fman_if, __if);
- struct rx_bmi_regs *regs = (struct rx_bmi_regs *)m->bmi_map;
+ struct rx_bmi_regs *regs = (struct rx_bmi_regs *)m->rx_bmi_map;
out_be32(®s->fmbm_rfrc, 0);
out_be32(®s->fmbm_rfbc, 0);
@@ -361,7 +363,7 @@ fman_if_promiscuous_enable(struct fman_if *p)
assert(fman_ccsr_map_fd != -1);
/* Enable Rx promiscuous mode */
- cmdcfg = &((struct memac_regs *)__if->ccsr_map)->command_config;
+ cmdcfg = &((struct memac_regs *)__if->memac_map)->command_config;
out_be32(cmdcfg, in_be32(cmdcfg) | CMD_CFG_PROMIS_EN);
}
@@ -374,7 +376,7 @@ fman_if_promiscuous_disable(struct fman_if *p)
assert(fman_ccsr_map_fd != -1);
/* Disable Rx promiscuous mode */
- cmdcfg = &((struct memac_regs *)__if->ccsr_map)->command_config;
+ cmdcfg = &((struct memac_regs *)__if->memac_map)->command_config;
out_be32(cmdcfg, in_be32(cmdcfg) & (~CMD_CFG_PROMIS_EN));
}
@@ -386,7 +388,7 @@ fman_if_enable_rx(struct fman_if *p)
assert(fman_ccsr_map_fd != -1);
/* enable Rx and Tx */
- out_be32(__if->ccsr_map + 8, in_be32(__if->ccsr_map + 8) | 3);
+ out_be32(__if->memac_map + 8, in_be32(__if->memac_map + 8) | 3);
}
void
@@ -397,7 +399,7 @@ fman_if_disable_rx(struct fman_if *p)
assert(fman_ccsr_map_fd != -1);
/* only disable Rx, not Tx */
- out_be32(__if->ccsr_map + 8, in_be32(__if->ccsr_map + 8) & ~(u32)2);
+ out_be32(__if->memac_map + 8, in_be32(__if->memac_map + 8) & ~(u32)2);
}
int
@@ -408,7 +410,7 @@ fman_if_get_rx_status(struct fman_if *p)
assert(fman_ccsr_map_fd != -1);
/* return true if RX bit is set */
- return !!(in_be32(__if->ccsr_map + 8) & (u32)2);
+ return !!(in_be32(__if->memac_map + 8) & (u32)2);
}
void
@@ -421,11 +423,11 @@ fman_if_loopback_enable(struct fman_if *p)
/* Enable loopback mode */
if ((__if->__if.is_memac) && (__if->__if.is_rgmii)) {
unsigned int *ifmode =
- &((struct memac_regs *)__if->ccsr_map)->if_mode;
+ &((struct memac_regs *)__if->memac_map)->if_mode;
out_be32(ifmode, in_be32(ifmode) | IF_MODE_RLP);
} else{
unsigned int *cmdcfg =
- &((struct memac_regs *)__if->ccsr_map)->command_config;
+ &((struct memac_regs *)__if->memac_map)->command_config;
out_be32(cmdcfg, in_be32(cmdcfg) | CMD_CFG_LOOPBACK_EN);
}
}
@@ -439,11 +441,11 @@ fman_if_loopback_disable(struct fman_if *p)
/* Disable loopback mode */
if ((__if->__if.is_memac) && (__if->__if.is_rgmii)) {
unsigned int *ifmode =
- &((struct memac_regs *)__if->ccsr_map)->if_mode;
+ &((struct memac_regs *)__if->memac_map)->if_mode;
out_be32(ifmode, in_be32(ifmode) & ~IF_MODE_RLP);
} else {
unsigned int *cmdcfg =
- &((struct memac_regs *)__if->ccsr_map)->command_config;
+ &((struct memac_regs *)__if->memac_map)->command_config;
out_be32(cmdcfg, in_be32(cmdcfg) & ~CMD_CFG_LOOPBACK_EN);
}
}
@@ -461,11 +463,11 @@ fman_if_set_bp(struct fman_if *fm_if, unsigned num __always_unused,
assert(fman_ccsr_map_fd != -1);
fmbm_ebmpi =
- in_be32(&((struct rx_bmi_regs *)__if->bmi_map)->fmbm_ebmpi[0]);
+ in_be32(&((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_ebmpi[0]);
fmbm_ebmpi = ebmpi_val_ace | (fmbm_ebmpi & ebmpi_mask) | (bpid << 16) |
(bufsize);
- out_be32(&((struct rx_bmi_regs *)__if->bmi_map)->fmbm_ebmpi[0],
+ out_be32(&((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_ebmpi[0],
fmbm_ebmpi);
}
@@ -477,7 +479,7 @@ fman_if_get_fc_threshold(struct fman_if *fm_if)
assert(fman_ccsr_map_fd != -1);
- fmbm_mpd = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_mpd;
+ fmbm_mpd = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_mpd;
return in_be32(fmbm_mpd);
}
@@ -490,7 +492,7 @@ fman_if_set_fc_threshold(struct fman_if *fm_if, u32 high_water,
assert(fman_ccsr_map_fd != -1);
- fmbm_mpd = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_mpd;
+ fmbm_mpd = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_mpd;
out_be32(fmbm_mpd, FMAN_ENABLE_BPOOL_DEPLETION);
return bm_pool_set_hw_threshold(bpid, low_water, high_water);
@@ -503,7 +505,7 @@ fman_if_get_fc_quanta(struct fman_if *fm_if)
assert(fman_ccsr_map_fd != -1);
- return in_be32(&((struct memac_regs *)__if->ccsr_map)->pause_quanta[0]);
+ return in_be32(&((struct memac_regs *)__if->memac_map)->pause_quanta[0]);
}
int
@@ -513,7 +515,7 @@ fman_if_set_fc_quanta(struct fman_if *fm_if, u16 pause_quanta)
assert(fman_ccsr_map_fd != -1);
- out_be32(&((struct memac_regs *)__if->ccsr_map)->pause_quanta[0],
+ out_be32(&((struct memac_regs *)__if->memac_map)->pause_quanta[0],
pause_quanta);
return 0;
}
@@ -528,7 +530,7 @@ fman_if_get_fdoff(struct fman_if *fm_if)
assert(fman_ccsr_map_fd != -1);
- fmbm_rebm = in_be32(&((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rebm);
+ fmbm_rebm = in_be32(&((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rebm);
fdoff = (fmbm_rebm >> FMAN_SP_EXT_BUF_MARG_START_SHIFT) & 0x1ff;
@@ -543,7 +545,7 @@ fman_if_set_err_fqid(struct fman_if *fm_if, uint32_t err_fqid)
assert(fman_ccsr_map_fd != -1);
unsigned int *fmbm_refqid =
- &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_refqid;
+ &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_refqid;
out_be32(fmbm_refqid, err_fqid);
}
@@ -559,7 +561,7 @@ fman_if_get_ic_params(struct fman_if *fm_if, struct fman_if_ic_params *icp)
assert(fman_ccsr_map_fd != -1);
unsigned int *fmbm_ricp =
- &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_ricp;
+ &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_ricp;
val = in_be32(fmbm_ricp);
icp->iceof = (val & iceof_mask) >> 12;
@@ -586,7 +588,7 @@ fman_if_set_ic_params(struct fman_if *fm_if,
val |= (icp->icsz >> 4) & icsz_mask;
unsigned int *fmbm_ricp =
- &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_ricp;
+ &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_ricp;
out_be32(fmbm_ricp, val);
unsigned int *fmbm_ticp =
@@ -608,7 +610,7 @@ fman_if_set_fdoff(struct fman_if *fm_if, uint32_t fd_offset)
assert(fman_ccsr_map_fd != -1);
- fmbm_rebm = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rebm;
+ fmbm_rebm = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rebm;
out_be32(fmbm_rebm, (in_be32(fmbm_rebm) & ~fmbm_mask) | val);
}
@@ -621,7 +623,7 @@ fman_if_set_maxfrm(struct fman_if *fm_if, uint16_t max_frm)
assert(fman_ccsr_map_fd != -1);
- reg_maxfrm = &((struct memac_regs *)__if->ccsr_map)->maxfrm;
+ reg_maxfrm = &((struct memac_regs *)__if->memac_map)->maxfrm;
out_be32(reg_maxfrm, (in_be32(reg_maxfrm) & 0xFFFF0000) | max_frm);
}
@@ -634,7 +636,7 @@ fman_if_get_maxfrm(struct fman_if *fm_if)
assert(fman_ccsr_map_fd != -1);
- reg_maxfrm = &((struct memac_regs *)__if->ccsr_map)->maxfrm;
+ reg_maxfrm = &((struct memac_regs *)__if->memac_map)->maxfrm;
return (in_be32(reg_maxfrm) | 0x0000FFFF);
}
@@ -655,7 +657,7 @@ fman_if_get_sg_enable(struct fman_if *fm_if)
assert(fman_ccsr_map_fd != -1);
- fmbm_rebm = in_be32(&((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rebm);
+ fmbm_rebm = in_be32(&((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rebm);
return (fmbm_rebm & FMAN_SP_SG_DISABLE) ? 0 : 1;
}
@@ -675,7 +677,7 @@ fman_if_set_sg(struct fman_if *fm_if, int enable)
assert(fman_ccsr_map_fd != -1);
- fmbm_rebm = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rebm;
+ fmbm_rebm = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rebm;
out_be32(fmbm_rebm, (in_be32(fmbm_rebm) & ~fmbm_mask) | val);
}
@@ -699,14 +701,14 @@ fman_if_discard_rx_errors(struct fman_if *fm_if)
struct __fman_if *__if = container_of(fm_if, struct __fman_if, __if);
unsigned int *fmbm_rfsdm, *fmbm_rfsem;
- fmbm_rfsem = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rfsem;
+ fmbm_rfsem = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rfsem;
out_be32(fmbm_rfsem, 0);
/* Configure the discard mask to discard the error packets which have
* DMA errors, Frame size error, Header error etc. The mask 0x010EE3F0
* is to configured discard all the errors which come in the FD[STATUS]
*/
- fmbm_rfsdm = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rfsdm;
+ fmbm_rfsdm = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rfsdm;
out_be32(fmbm_rfsdm, 0x010EE3F0);
}
@@ -718,9 +720,9 @@ fman_if_receive_rx_errors(struct fman_if *fm_if,
unsigned int *fmbm_rcfg, *fmbm_rfsdm, *fmbm_rfsem;
unsigned int val;
- fmbm_rcfg = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rcfg;
- fmbm_rfsdm = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rfsdm;
- fmbm_rfsem = &((struct rx_bmi_regs *)__if->bmi_map)->fmbm_rfsem;
+ fmbm_rcfg = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rcfg;
+ fmbm_rfsdm = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rfsdm;
+ fmbm_rfsem = &((struct rx_bmi_regs *)__if->rx_bmi_map)->fmbm_rfsem;
val = in_be32(fmbm_rcfg);
out_be32(fmbm_rcfg, val | BMI_PORT_CFG_FDOVR);
diff --git a/drivers/bus/dpaa/include/fman.h b/drivers/bus/dpaa/include/fman.h
index c33fe81516..a248edf4d8 100644
--- a/drivers/bus/dpaa/include/fman.h
+++ b/drivers/bus/dpaa/include/fman.h
@@ -462,8 +462,8 @@ struct __fman_if {
char node_name[IF_NAME_MAX_LEN];
char node_path[PATH_MAX];
uint64_t regs_size;
- void *ccsr_map;
- void *bmi_map;
+ void *memac_map;
+ void *rx_bmi_map;
void *tx_bmi_map;
void *qmi_map;
};
@@ -473,8 +473,6 @@ struct __fman_if {
*/
extern const struct list_head *fman_if_list;
-extern int fman_ccsr_map_fd;
-
/* To iterate the "bpool_list" for an interface. Eg;
* struct fman_if *p = get_ptr_to_some_interface();
* struct fman_if_bpool *bp;
--
2.25.1
^ permalink raw reply related
* [PATCH v2 02/19] bus/dpaa: scan max BPID from DTS
From: Hemant Agrawal @ 2026-06-21 10:16 UTC (permalink / raw)
To: stephen, david.marchand, dev; +Cc: Jun Yang
In-Reply-To: <20260621101651.1081425-1-hemant.agrawal@nxp.com>
From: Jun Yang <jun.yang@nxp.com>
Calculate the maximum BPID dynamically from the device tree
configuration instead of using a hardcoded value. This ensures
correct operation across different DPAA hardware configurations.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
drivers/bus/dpaa/base/qbman/bman_driver.c | 48 ++++++++++++++++-------
1 file changed, 33 insertions(+), 15 deletions(-)
diff --git a/drivers/bus/dpaa/base/qbman/bman_driver.c b/drivers/bus/dpaa/base/qbman/bman_driver.c
index 23e44ac10b..85575192bf 100644
--- a/drivers/bus/dpaa/base/qbman/bman_driver.c
+++ b/drivers/bus/dpaa/base/qbman/bman_driver.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
*
* Copyright 2008-2016 Freescale Semiconductor Inc.
- * Copyright 2017 NXP
+ * Copyright 2017,2026 NXP
*
*/
@@ -182,7 +182,12 @@ int bman_init_ccsr(const struct device_node *node)
int bman_global_init(void)
{
const struct device_node *dt_node;
+ const rte_be32_t *range;
+ uint32_t start, count;
+ int ret;
static int done;
+#define BPID_RANGE_START_INDEX 0
+#define BPID_RANGE_COUNT_INDEX 1
if (done)
return -EBUSY;
@@ -197,36 +202,49 @@ int bman_global_init(void)
if (of_device_is_compatible(dt_node, "fsl,bman-portal-1.0") ||
of_device_is_compatible(dt_node, "fsl,bman-portal-1.0.0")) {
bman_ip_rev = BMAN_REV10;
- bman_pool_max = 64;
} else if (of_device_is_compatible(dt_node, "fsl,bman-portal-2.0") ||
of_device_is_compatible(dt_node, "fsl,bman-portal-2.0.8")) {
bman_ip_rev = BMAN_REV20;
- bman_pool_max = 8;
} else if (of_device_is_compatible(dt_node, "fsl,bman-portal-2.1.0") ||
of_device_is_compatible(dt_node, "fsl,bman-portal-2.1.1") ||
of_device_is_compatible(dt_node, "fsl,bman-portal-2.1.2") ||
of_device_is_compatible(dt_node, "fsl,bman-portal-2.1.3")) {
bman_ip_rev = BMAN_REV21;
- bman_pool_max = 64;
} else {
- pr_warn("unknown BMan version in portal node,default "
- "to rev1.0");
+ pr_warn("unknown BMan version in portal node, default to rev1.0");
bman_ip_rev = BMAN_REV10;
- bman_pool_max = 64;
}
if (!bman_ip_rev) {
pr_err("Unknown bman portal version\n");
return -ENODEV;
}
- {
- const struct device_node *dn = of_find_compatible_node(NULL,
- NULL, "fsl,bman");
- if (!dn)
- pr_err("No bman device node available");
-
- if (bman_init_ccsr(dn))
- pr_err("BMan CCSR map failed.");
+
+ for_each_compatible_node(dt_node, NULL, "fsl,bpid-range") {
+ range = of_get_property(dt_node, "fsl,bpid-range", NULL);
+ if (!range)
+ continue;
+ start = rte_be_to_cpu_32(range[BPID_RANGE_START_INDEX]);
+ count = rte_be_to_cpu_32(range[BPID_RANGE_COUNT_INDEX]);
+ bman_pool_max = start + count;
+ pr_info("Max BPID: %d, fixed BPID < %d", bman_pool_max, start);
+ break;
+ }
+ if (!bman_pool_max) {
+ pr_err("No BPID range found");
+ return -ENODEV;
+ }
+
+ dt_node = of_find_compatible_node(NULL, NULL, "fsl,bman");
+ if (!dt_node) {
+ pr_err("No bman device node available");
+ return -ENODEV;
+ }
+
+ ret = bman_init_ccsr(dt_node);
+ if (ret) {
+ pr_err("Failed(%d) to init bman ccsr", ret);
+ return ret;
}
done = 1;
--
2.25.1
^ permalink raw reply related
* [PATCH v2 03/19] drivers: add BMI Tx statistics
From: Hemant Agrawal @ 2026-06-21 10:16 UTC (permalink / raw)
To: stephen, david.marchand, dev; +Cc: Jun Yang
In-Reply-To: <20260621101651.1081425-1-hemant.agrawal@nxp.com>
From: Jun Yang <jun.yang@nxp.com>
Add support for BMI (Buffer Manager Interface) Tx statistics
counters. Extend fman_hw to read Tx BMI registers and expose
them through the xstats interface.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
drivers/bus/dpaa/base/fman/fman_hw.c | 2 --
drivers/bus/dpaa/include/fman.h | 24 ++++++++++++++++++++++++
drivers/net/dpaa/dpaa_ethdev.c | 10 +++++++++-
drivers/net/dpaa/dpaa_ethdev.h | 11 +++++++++--
4 files changed, 42 insertions(+), 5 deletions(-)
diff --git a/drivers/bus/dpaa/base/fman/fman_hw.c b/drivers/bus/dpaa/base/fman/fman_hw.c
index ce68581555..aab04bf76a 100644
--- a/drivers/bus/dpaa/base/fman/fman_hw.c
+++ b/drivers/bus/dpaa/base/fman/fman_hw.c
@@ -301,7 +301,6 @@ fman_if_bmi_stats_enable(struct fman_if *p)
uint32_t tmp;
tmp = in_be32(®s->fmbm_rstc);
-
tmp |= FMAN_BMI_COUNTERS_EN;
out_be32(®s->fmbm_rstc, tmp);
@@ -315,7 +314,6 @@ fman_if_bmi_stats_disable(struct fman_if *p)
uint32_t tmp;
tmp = in_be32(®s->fmbm_rstc);
-
tmp &= ~FMAN_BMI_COUNTERS_EN;
out_be32(®s->fmbm_rstc, tmp);
diff --git a/drivers/bus/dpaa/include/fman.h b/drivers/bus/dpaa/include/fman.h
index a248edf4d8..2bddf489b8 100644
--- a/drivers/bus/dpaa/include/fman.h
+++ b/drivers/bus/dpaa/include/fman.h
@@ -306,6 +306,21 @@ struct tx_bmi_regs {
uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine*/
uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale*/
uint32_t fmbm_trlmt; /**< Tx Rate Limiter*/
+ uint32_t reserved0034[0x73];/**< (0x0034 0x01FF) */
+ uint32_t fmbm_tstc; /**< Tx Statistics Counters*/
+ uint32_t fmbm_tfrc; /**< Tx Frame Counter*/
+ uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter*/
+ uint32_t fmbm_tfledc; /**< Tx Frames Length Error Discard*/
+ uint32_t fmbm_tfufdc; /**< Tx Frames Unsupported Format*/
+ uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */
+ uint32_t reserved0218[0x1a];/**< (0x0218 0x027F) */
+ uint32_t fmbm_tpc; /**< Tx Performance Counters*/
+ uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters */
+ uint32_t fmbm_tccn; /**< Tx Cycle Counter*/
+ uint32_t fmbm_ttuc; /**< Tx Tasks Utilization Counter */
+ uint32_t fmbm_ttcquc; /**< Tx Transmit Confirm Queue Utilization Counter*/
+ uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter */
+ uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter */
};
/* Description FM RTC timer alarm */
@@ -468,6 +483,15 @@ struct __fman_if {
void *qmi_map;
};
+#define MEMMAC_REG_OFFSET(reg) offsetof(struct memac_regs, reg)
+#define BMI_RX_REG_OFFSET(reg) offsetof(struct rx_bmi_regs, reg)
+#define BMI_TX_REG_OFFSET(reg) offsetof(struct tx_bmi_regs, reg)
+
+#define FMAN_IF_BMI_RX_STAT_OFFSET_START BMI_RX_REG_OFFSET(fmbm_rfrc)
+#define FMAN_IF_BMI_RX_STAT_OFFSET_END BMI_RX_REG_OFFSET(fmbm_rbdc)
+#define FMAN_IF_BMI_TX_STAT_OFFSET_START BMI_TX_REG_OFFSET(fmbm_tfrc)
+#define FMAN_IF_BMI_TX_STAT_OFFSET_END BMI_TX_REG_OFFSET(fmbm_tbdc)
+
/* And this is the base list node that the interfaces are added to. (See
* fman_if_enable_all_rx() below for an example of its use.)
*/
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 9f976d179b..8fb2e33e0a 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2017-2020,2022-2025 NXP
+ * Copyright 2017-2020,2022-2026 NXP
*
*/
/* System headers */
@@ -143,6 +143,14 @@ static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rodc)},
{"rx_buf_diallocate",
offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rbdc)},
+ {"tx_bad_frames_count",
+ offsetof(struct dpaa_if_tx_bmi_stats, fmbm_tfdc)},
+ {"tx_frame_length_discard",
+ offsetof(struct dpaa_if_tx_bmi_stats, fmbm_tfledc)},
+ {"tx_frames_unsupported_format",
+ offsetof(struct dpaa_if_tx_bmi_stats, fmbm_tfufdc)},
+ {"tx_buf_diallocate",
+ offsetof(struct dpaa_if_tx_bmi_stats, fmbm_tbdc)},
};
static struct rte_dpaa_driver rte_dpaa_pmd;
diff --git a/drivers/net/dpaa/dpaa_ethdev.h b/drivers/net/dpaa/dpaa_ethdev.h
index f400030a5c..d342d98f23 100644
--- a/drivers/net/dpaa/dpaa_ethdev.h
+++ b/drivers/net/dpaa/dpaa_ethdev.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
- * Copyright 2017-2024 NXP
+ * Copyright 2017-2026 NXP
*
*/
#ifndef __DPAA_ETHDEV_H__
@@ -234,7 +234,6 @@ dpaa_rx_cb_atomic(void *event,
void **bufs);
struct dpaa_if_rx_bmi_stats {
- uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/
@@ -245,6 +244,14 @@ struct dpaa_if_rx_bmi_stats {
uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/
};
+struct dpaa_if_tx_bmi_stats {
+ uint32_t fmbm_tfrc; /**< Tx Frame Counter*/
+ uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter*/
+ uint32_t fmbm_tfledc; /**< Tx Frames Length Error Discard*/
+ uint32_t fmbm_tfufdc; /**< Tx Frames Unsupported Format*/
+ uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */
+};
+
int
dpaa_tx_conf_queue_init(struct qman_fq *fq);
--
2.25.1
^ permalink raw reply related
* [PATCH v2 04/19] drivers: add process-type guards for secondary process
From: Hemant Agrawal @ 2026-06-21 10:16 UTC (permalink / raw)
To: stephen, david.marchand, dev; +Cc: Prashant Gupta
In-Reply-To: <20260621101651.1081425-1-hemant.agrawal@nxp.com>
From: Prashant Gupta <prashant.gupta_3@nxp.com>
Add RTE_PROC_PRIMARY checks in device initialization paths for
net/dpaa, crypto/dpaa_sec and dma/dpaa drivers. Secondary
processes should skip hardware initialization to prevent
segfaults when accessing hardware registers that are only
mapped in the primary process.
Signed-off-by: Prashant Gupta <prashant.gupta_3@nxp.com>
---
drivers/crypto/dpaa_sec/dpaa_sec.c | 3 ---
drivers/dma/dpaa/dpaa_qdma.c | 4 ++++
drivers/net/dpaa/dpaa_ethdev.c | 3 +++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c
index 65bbd38b17..36f5819b0e 100644
--- a/drivers/crypto/dpaa_sec/dpaa_sec.c
+++ b/drivers/crypto/dpaa_sec/dpaa_sec.c
@@ -3783,9 +3783,6 @@ cryptodev_dpaa_sec_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
RTE_DPAA_MAX_NB_SEC_QPS,
};
- if (rte_eal_process_type() != RTE_PROC_PRIMARY)
- return 0;
-
snprintf(cryptodev_name, sizeof(cryptodev_name), "%s", dpaa_dev->name);
cryptodev = rte_cryptodev_pmd_create(cryptodev_name, &dpaa_dev->device, &init_params);
diff --git a/drivers/dma/dpaa/dpaa_qdma.c b/drivers/dma/dpaa/dpaa_qdma.c
index 74e23d2ee5..0ede9ee8b5 100644
--- a/drivers/dma/dpaa/dpaa_qdma.c
+++ b/drivers/dma/dpaa/dpaa_qdma.c
@@ -1329,6 +1329,10 @@ dpaa_qdma_init(struct rte_dma_dev *dmadev)
int regs_size;
int ret;
uint32_t i, j, k;
+ char *penv;
+
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return -ENOTSUP;
if (dpaa_get_devargs(dmadev->device->devargs, DPAA_DMA_ERROR_CHECK)) {
s_hw_err_check = true;
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 8fb2e33e0a..42ab9679d1 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -2686,6 +2686,9 @@ rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
PMD_INIT_FUNC_TRACE();
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
eth_dev = dpaa_dev->eth_dev;
dpaa_eth_dev_close(eth_dev);
ret = rte_eth_dev_release_port(eth_dev);
--
2.25.1
^ permalink raw reply related
* [PATCH v2 05/19] bus/dpaa: define helpers for qman channel and wq
From: Hemant Agrawal @ 2026-06-21 10:16 UTC (permalink / raw)
To: stephen, david.marchand, dev; +Cc: Jun Yang
In-Reply-To: <20260621101651.1081425-1-hemant.agrawal@nxp.com>
From: Jun Yang <jun.yang@nxp.com>
Add inline helper functions to extract channel and work queue
from a frame queue descriptor, replacing open-coded bit
manipulation throughout the driver.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
---
drivers/bus/dpaa/base/qbman/qman.c | 14 ++------------
drivers/bus/dpaa/base/qbman/qman.h | 23 ++++++++++++++++++++++-
2 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/bus/dpaa/base/qbman/qman.c b/drivers/bus/dpaa/base/qbman/qman.c
index 5534e1846c..c9a8ec34a5 100644
--- a/drivers/bus/dpaa/base/qbman/qman.c
+++ b/drivers/bus/dpaa/base/qbman/qman.c
@@ -2704,14 +2704,6 @@ int qman_delete_cgr(struct qman_cgr *cgr)
return ret;
}
-#define GENMASK(h, l) \
- (((~0U) >> (sizeof(unsigned int) * 8 - ((h) - (l) + 1))) << (l))
-
-/* 'fqid' is a 24-bit field in every h/w descriptor */
-#define QM_FQID_MASK GENMASK(23, 0)
-#define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK))
-#define qm_fqid_get(p) (be32_to_cpu((p)->fqid) & QM_FQID_MASK)
-
static int
_qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
{
@@ -2798,7 +2790,6 @@ qman_shutdown_fq(u32 fqid)
u32 res;
u8 state;
u32 channel, wq;
- u16 dest_wq;
DPAA_BUS_DEBUG("In shutdown for queue = %x", fqid);
p = get_affine_portal();
@@ -2828,9 +2819,8 @@ qman_shutdown_fq(u32 fqid)
}
/* Need to store these since the MCR gets reused */
- dest_wq = be16_to_cpu(mcr->queryfq.fqd.dest_wq);
- channel = dest_wq & 0x7;
- wq = dest_wq >> 3;
+ channel = qm_fqd_get_chan(&mcr->queryfq.fqd);
+ wq = qm_fqd_get_wq(&mcr->queryfq.fqd);
switch (state) {
case QM_MCR_NP_STATE_TEN_SCHED:
diff --git a/drivers/bus/dpaa/base/qbman/qman.h b/drivers/bus/dpaa/base/qbman/qman.h
index 43a16d1e3b..bd97689a91 100644
--- a/drivers/bus/dpaa/base/qbman/qman.h
+++ b/drivers/bus/dpaa/base/qbman/qman.h
@@ -1,12 +1,15 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
*
* Copyright 2008-2016 Freescale Semiconductor Inc.
- * Copyright 2017 NXP
+ * Copyright 2017,2026 NXP
*
*/
#include "qman_priv.h"
+#define GENMASK(h, l) \
+ (((~0U) >> (sizeof(u32) * 8 - ((h) - (l) + 1))) << (l))
+
/***************************/
/* Portal register assists */
/***************************/
@@ -42,6 +45,14 @@
#define QM_CL_RR0 0x3900
#define QM_CL_RR1 0x3940
+#define QM_FQD_CHAN_OFF 3
+#define QM_FQD_WQ_MASK GENMASK(2, 0)
+/* 'fqid' is a 24-bit field in every h/w descriptor */
+#define QM_FQID_MASK GENMASK(23, 0)
+
+#define qm_fqid_set(p, v) ((p)->fqid = cpu_to_be32((v) & QM_FQID_MASK))
+#define qm_fqid_get(p) (be32_to_cpu((p)->fqid) & QM_FQID_MASK)
+
/* BTW, the drivers (and h/w programming model) already obtain the required
* synchronisation for portal accesses via lwsync(), hwsync(), and
* data-dependencies. Use of barrier()s or other order-preserving primitives
@@ -911,3 +922,13 @@ static inline void __qm_isr_write(struct qm_portal *portal, enum qm_isr_reg n,
__qm_out(&portal->addr, QM_REG_ISR + (n << 2), val);
#endif
}
+
+static inline int qm_fqd_get_chan(const struct qm_fqd *fqd)
+{
+ return be16_to_cpu(fqd->dest_wq) >> QM_FQD_CHAN_OFF;
+}
+
+static inline int qm_fqd_get_wq(const struct qm_fqd *fqd)
+{
+ return be16_to_cpu(fqd->dest_wq) & QM_FQD_WQ_MASK;
+}
--
2.25.1
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