From: Thomas Monjalon <thomas@monjalon.net>
To: Yonghao Li <cruselee1@live.cn>
Cc: dev@dpdk.org, konstantin.ananyev@huawei.com, stable@dpdk.org,
Bruce Richardson <bruce.richardson@intel.com>
Subject: Re: [PATCH] eal/x86: fix LZCNT CPU feature bit
Date: Wed, 23 Sep 2026 18:48:33 +0200 [thread overview]
Message-ID: <vdxtIy_6RCmB6PVFi6O4VA@monjalon.net> (raw)
In-Reply-To: <apU1JV-ays2oJDgZ@bricha3-mobl1.ger.corp.intel.com>
31/08/2026 10:02, Bruce Richardson:
> On Fri, Aug 28, 2026 at 09:32:52PM +0100, Yonghao Li wrote:
> > --- a/lib/eal/x86/rte_cpuflags.c
> > +++ b/lib/eal/x86/rte_cpuflags.c
> > @@ -137,7 +137,7 @@ struct feature_entry rte_cpu_feature_table[] = {
> > FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
> >
> > FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0)
> > - FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)
> > + FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 5)
> > FEAT_DEF(MONITORX, 0x80000001, 0, RTE_REG_ECX, 29)
> >
>
> Confirmed by checking Table 21-90 in the Intel SDM Vol 1 docs. Thanks for
> catching this.
>
> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Applied, thanks.
prev parent reply other threads:[~2026-09-23 16:48 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 20:32 [PATCH] eal/x86: fix LZCNT CPU feature bit Yonghao Li
2026-08-31 7:51 ` David Marchand
2026-08-31 8:02 ` Bruce Richardson
2026-09-23 16:48 ` Thomas Monjalon [this message]
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