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Wed, 22 Mar 2023 21:03:23 +0000 Received: from DM4PR11MB5488.namprd11.prod.outlook.com ([fe80::3e9f:e67a:40c:d2da]) by DM4PR11MB5488.namprd11.prod.outlook.com ([fe80::3e9f:e67a:40c:d2da%8]) with mapi id 15.20.6178.037; Wed, 22 Mar 2023 21:03:23 +0000 Message-ID: <0296ba17-6e91-76f2-4866-179feb94074b@intel.com> Date: Wed, 22 Mar 2023 14:03:20 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH 1/2] drm/i915: limit double GT reset to pre-MTL Content-Language: en-US To: John Harrison , References: <20230320211039.1513368-1-daniele.ceraolospurio@intel.com> <382f0058-2b4f-4ef2-8031-27a2f75715df@intel.com> From: "Ceraolo Spurio, Daniele" In-Reply-To: <382f0058-2b4f-4ef2-8031-27a2f75715df@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: BY3PR10CA0028.namprd10.prod.outlook.com (2603:10b6:a03:255::33) To DM4PR11MB5488.namprd11.prod.outlook.com (2603:10b6:5:39d::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5488:EE_|SA0PR11MB4671:EE_ X-MS-Office365-Filtering-Correlation-Id: caa4ca38-7400-444b-5a5b-08db2b18df7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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And there is no w/a number associated with it. > It all feels extremely suspect and warrants a great big FIXME tag as a > minimum. I agree that the whole thing is unclear and we could add a FIXME, but IMO that is outside the scope of this patch as I'm not adding the code in question. This should be discussed with the original author/reviewers. Daniele > > John. > > >> >> This is a problem on MTL, due to the fact that we have to apply a time >> consuming WA (coming in the next patch) every time we hit the GDRST >> register in a way that can include the GSC engine. Even post MTL, the >> expectation is that we'll have some work to do before and after hitting >> the GDRST if the GSC is involved. >> >> Since the issue requiring the double reset seems to be limited to older >> platforms, instead of trying to handle the double-reset on MTL and >> future platforms it is just easier to turn it off. The default on MTL is >> also for GuC to own engine reset, with i915 only covering full-GT reset. >> >> Signed-off-by: Daniele Ceraolo Spurio >> Cc: Chris Wilson >> Cc: Andi Shyti >> Cc: Mika Kuoppala >> Cc: Gwan-gyeong Mun >> Cc: John Harrison >> --- >>   drivers/gpu/drm/i915/gt/intel_reset.c | 35 +++++++++++++++------------ >>   1 file changed, 20 insertions(+), 15 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c >> b/drivers/gpu/drm/i915/gt/intel_reset.c >> index 0bb9094fdacd..2c3463f77e5c 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_reset.c >> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c >> @@ -268,9 +268,27 @@ static int ilk_do_reset(struct intel_gt *gt, >> intel_engine_mask_t engine_mask, >>   static int gen6_hw_domain_reset(struct intel_gt *gt, u32 >> hw_domain_mask) >>   { >>       struct intel_uncore *uncore = gt->uncore; >> -    int loops = 2; >> +    int loops; >>       int err; >>   +    /* >> +     * On some platforms, e.g. Jasperlake, we see that the engine >> register >> +     * state is not cleared until shortly after GDRST reports >> completion, >> +     * causing a failure as we try to immediately resume while the >> internal >> +     * state is still in flux. If we immediately repeat the reset, the >> +     * second reset appears to serialise with the first, and since >> it is a >> +     * no-op, the registers should retain their reset value. >> However, there >> +     * is still a concern that upon leaving the second reset, the >> internal >> +     * engine state is still in flux and not ready for resuming. >> +     * >> +     * Starting on MTL, there are some prep steps that we need to do >> when >> +     * resetting some engines that need to be applied every time we >> write to >> +     * GEN6_GDRST. As those are time consuming (tens of ms), we >> don't want >> +     * to perform that twice, so, since the Jasperlake issue hasn't >> been >> +     * observed on MTL, we avoid repeating the reset on newer >> platforms. >> +     */ >> +    loops = GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70) ? 2 : 1; >> + >>       /* >>        * GEN6_GDRST is not in the gt power well, no need to check >>        * for fifo space for the write or forcewake the chip for >> @@ -279,20 +297,7 @@ static int gen6_hw_domain_reset(struct intel_gt >> *gt, u32 hw_domain_mask) >>       do { >>           intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask); >>   -        /* >> -         * Wait for the device to ack the reset requests. >> -         * >> -         * On some platforms, e.g. Jasperlake, we see that the >> -         * engine register state is not cleared until shortly after >> -         * GDRST reports completion, causing a failure as we try >> -         * to immediately resume while the internal state is still >> -         * in flux. If we immediately repeat the reset, the second >> -         * reset appears to serialise with the first, and since >> -         * it is a no-op, the registers should retain their reset >> -         * value. However, there is still a concern that upon >> -         * leaving the second reset, the internal engine state >> -         * is still in flux and not ready for resuming. >> -         */ >> +        /* Wait for the device to ack the reset requests. */ >>           err = __intel_wait_for_register_fw(uncore, GEN6_GDRST, >>                              hw_domain_mask, 0, >>                              2000, 0, >