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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aec6c795282sm1025387166b.6.2025.07.23.03.19.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Jul 2025 03:19:13 -0700 (PDT) Message-ID: <0a2188e7-3919-48f7-b5c1-8f779f617f28@oss.qualcomm.com> Date: Wed, 23 Jul 2025 12:19:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/17] drm/msm/a6xx: Switch to GMU AO counter To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-9-9347aa5bcbd6@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250720-ifpc-support-v1-9-9347aa5bcbd6@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=BJ6zrEQG c=1 sm=1 tr=0 ts=6880b724 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=oovjfIWShZiszQ5o9iAA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: JRCZfIbPxoE3S9xeoNyfs3CKm7KYSihp X-Proofpoint-ORIG-GUID: JRCZfIbPxoE3S9xeoNyfs3CKm7KYSihp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDA4NyBTYWx0ZWRfX24LgzU80T4Xx wAATIYYHiDA8gW4SjcXJpWVMdVQAkwFzl4cVfpwC2oucp0LjODjZaKcpO7hMUkm2uxB02a6vP2N mGqzy338XcIxgzo1+J3w7Bu8LHT7nvQ/ldB/OntUSB9dIAcEY0LbCChBFVoMOIMFntb371lZrkx fCr0UGwfYljbpR80qeD3KCwmNJL/Tujs/JazTLB0RXOPt3v8JFhzQHYuDoG8+tirU3gkvx6bC0F SZeYgZLohPqTAplVXwl2FNyQLpY0j7M6spzMCa8+hkH01X1DJhyl/2+fliXCqiEsA+NrJeHwyOD D4anR40n8Ju8vX3lziB2uNObRcHulc641tib07fZ6dqyP6VaPI8T54S+xEM4o7scwefRSexxP4d HZbjjJUrlssDdNqc+hlqHVR46y0S+6a5CPWLfc4e9oAzaFQs9HCMoZNDVOfgeNe5lWzi6aGn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_02,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230087 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 7/20/25 2:16 PM, Akhil P Oommen wrote: > CP_ALWAYS_ON counter falls under GX domain which is collapsed during > IFPC. So switch to GMU_ALWAYS_ON counter for any CPU reads since it is > not impacted by IFPC. Both counters are clocked by same xo clock source. > > Signed-off-by: Akhil P Oommen > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 30 ++++++++++++++++-------------- > 1 file changed, 16 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 6770f0363e7284e4596b1188637a4615d2c0779b..f000915a4c2698a85b45bd3c92e590f14999d10d 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -16,6 +16,19 @@ > > #define GPU_PAS_ID 13 > > +static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu) > +{ > + u64 count_hi, count_lo, temp; > + > + do { > + count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); > + count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); > + temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); > + } while (count_hi != temp); The original logic is as follows: static u64 gen7_read_alwayson(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); u32 lo = 0, hi = 0, tmp = 0; /* Always use the GMU AO counter when doing a AHB read */ gmu_core_regread(device, GEN7_GMU_ALWAYS_ON_COUNTER_H, &hi); gmu_core_regread(device, GEN7_GMU_ALWAYS_ON_COUNTER_L, &lo); /* Check for overflow */ gmu_core_regread(device, GEN7_GMU_ALWAYS_ON_COUNTER_H, &tmp); if (hi != tmp) { gmu_core_regread(device, GEN7_GMU_ALWAYS_ON_COUNTER_L, &lo); hi = tmp; } return (((u64) hi) << 32) | lo; } Doing this in a while-loop almost looks like you want a lot of time to pass - REG_WIDTH(u32?)/19.2 MHz Konrad