From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2EB3DCCA470 for ; Wed, 1 Oct 2025 07:47:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8BE9A10E690; Wed, 1 Oct 2025 07:47:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Fwy/laVP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id E281D10E690 for ; Wed, 1 Oct 2025 07:47:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1759304865; x=1790840865; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=/QaWQpWbEUgMj7y0djuC4uNPi0m/wC8mRT9s62rgIx0=; b=Fwy/laVPl8JArJo0wMNWT7VqnO1JMgRDdr/ZprtLpcSiwogdYw0BPsz5 4S9zdwU4spEHchRE9ut8A9ADYoy7iBdijweTKxL5ymJDcPEj38W4rxNSK 6Jk1TQmvIvUv0LM+Aj1hVEGFnr3yD2pRwC8RppMzy3TiGIOmtfG0Wq3qx d9s+Va9A5Ub0YPB7k+RrzoZdOWiiJpfN6U4dLGzZk+m/rpY0LYNMWUjcv 30YoJVR3i/JOaK2ynsjg3RCHldHIRbwDzeW1U/6yxxdRUxeImyhScGhgy /5PG/xVioY6kTlwxzHP7LOhrm75aWwB1wTtLlYKhpl+4EY1YeVdSYWOOI w==; X-CSE-ConnectionGUID: 3g2nURbpQQehLnrQm4yMqQ== X-CSE-MsgGUID: I4kfGvNUTQ+RhaACHZFdRw== X-IronPort-AV: E=McAfee;i="6800,10657,11569"; a="87018961" X-IronPort-AV: E=Sophos;i="6.18,306,1751266800"; d="scan'208";a="87018961" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2025 00:47:44 -0700 X-CSE-ConnectionGUID: S/VcsHf0Th2eRWA2/5ZFXw== X-CSE-MsgGUID: LVlQsvt4QO69izQH++l1ag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,306,1751266800"; d="scan'208";a="183009635" Received: from unknown (HELO [10.102.88.152]) ([10.102.88.152]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2025 00:47:43 -0700 Message-ID: <0afdf845-0ce0-45f2-85f3-5633987db268@linux.intel.com> Date: Wed, 1 Oct 2025 09:47:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] accel/ivpu: Enable MCA ECC signalling based on MSR To: Maciej Falkowski , dri-devel@lists.freedesktop.org Cc: oded.gabbay@gmail.com, jeff.hugo@oss.qualcomm.com, lizhi.hou@amd.com, Tomasz Rusinowicz References: <20250925145020.1446208-1-maciej.falkowski@linux.intel.com> Content-Language: en-US From: Karol Wachowski Organization: Intel Technology Poland sp. z o.o. - ul. Slowackiego 173, 80-298 Gdansk - KRS 101882 - NIP 957-07-52-316 In-Reply-To: <20250925145020.1446208-1-maciej.falkowski@linux.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Reviewed-by: Karol Wachowski On 9/25/2025 4:50 PM, Maciej Falkowski wrote: > From: Tomasz Rusinowicz > > Add new boot parameter for NPU5+ that enables > ECC signalling for on-chip memory based on the value > of MSR_INTEGRITY_CAPS register. > > Signed-off-by: Tomasz Rusinowicz > Signed-off-by: Maciej Falkowski > --- > drivers/accel/ivpu/ivpu_fw.c | 4 ++++ > drivers/accel/ivpu/ivpu_hw.c | 23 +++++++++++++++++++++++ > drivers/accel/ivpu/ivpu_hw.h | 1 + > 3 files changed, 28 insertions(+) > > diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c > index b81bd143a285..be1290be77fd 100644 > --- a/drivers/accel/ivpu/ivpu_fw.c > +++ b/drivers/accel/ivpu/ivpu_fw.c > @@ -606,6 +606,8 @@ static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_ > boot_params->system_time_us); > ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = 0x%x\n", > boot_params->power_profile); > + ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_uses_ecc_mca_signal = 0x%x\n", > + boot_params->vpu_uses_ecc_mca_signal); > } > > void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) > @@ -708,6 +710,8 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params > boot_params->d0i3_entry_vpu_ts = 0; > if (IVPU_WA(disable_d0i2)) > boot_params->power_profile |= BIT(1); > + boot_params->vpu_uses_ecc_mca_signal = > + ivpu_hw_uses_ecc_mca_signal(vdev) ? VPU_BOOT_MCA_ECC_BOTH : 0; > > boot_params->system_time_us = ktime_to_us(ktime_get_real()); > wmb(); /* Flush WC buffers after writing bootparams */ > diff --git a/drivers/accel/ivpu/ivpu_hw.c b/drivers/accel/ivpu/ivpu_hw.c > index 8dbf8780920a..d69cd0d93569 100644 > --- a/drivers/accel/ivpu/ivpu_hw.c > +++ b/drivers/accel/ivpu/ivpu_hw.c > @@ -8,6 +8,8 @@ > #include "ivpu_hw_btrs.h" > #include "ivpu_hw_ip.h" > > +#include > +#include > #include > #include > #include > @@ -22,6 +24,8 @@ MODULE_PARM_DESC(fail_hw, ",,,"); > > #define FW_SHARED_MEM_ALIGNMENT SZ_512K /* VPU MTRR limitation */ > > +#define ECC_MCA_SIGNAL_ENABLE_MASK 0xff > + > static char *platform_to_str(u32 platform) > { > switch (platform) { > @@ -395,3 +399,22 @@ irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr) > pm_runtime_mark_last_busy(vdev->drm.dev); > return IRQ_HANDLED; > } > + > +bool ivpu_hw_uses_ecc_mca_signal(struct ivpu_device *vdev) > +{ > + unsigned long long msr_integrity_caps; > + int ret; > + > + if (ivpu_hw_ip_gen(vdev) < IVPU_HW_IP_50XX) > + return false; > + > + ret = rdmsrq_safe(MSR_INTEGRITY_CAPS, &msr_integrity_caps); > + if (ret) { > + ivpu_warn(vdev, "Error reading MSR_INTEGRITY_CAPS: %d", ret); > + return false; > + } > + > + ivpu_dbg(vdev, MISC, "MSR_INTEGRITY_CAPS: 0x%llx\n", msr_integrity_caps); > + > + return msr_integrity_caps & ECC_MCA_SIGNAL_ENABLE_MASK; > +} > diff --git a/drivers/accel/ivpu/ivpu_hw.h b/drivers/accel/ivpu/ivpu_hw.h > index 511a1a29f7f6..b6d0f0d0dccc 100644 > --- a/drivers/accel/ivpu/ivpu_hw.h > +++ b/drivers/accel/ivpu/ivpu_hw.h > @@ -63,6 +63,7 @@ void ivpu_irq_handlers_init(struct ivpu_device *vdev); > void ivpu_hw_irq_enable(struct ivpu_device *vdev); > void ivpu_hw_irq_disable(struct ivpu_device *vdev); > irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr); > +bool ivpu_hw_uses_ecc_mca_signal(struct ivpu_device *vdev); > > static inline u32 ivpu_hw_btrs_irq_handler(struct ivpu_device *vdev, int irq) > {