From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kenneth Graunke Subject: Re: [PATCH 6/6] [v4] drm/i915: Add support for CCS modifiers Date: Tue, 01 Aug 2017 15:52:38 -0700 Message-ID: <10882811.hqQZZsOt1U@kirito> References: <20170801165817.7063-1-ben@bwidawsk.net> <1530601.zh7oHHzDPt@kirito> <20170801224753.GA2441@mail.bwidawsk.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1226875047==" Return-path: In-Reply-To: <20170801224753.GA2441@mail.bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Ben Widawsky , Daniel Stone , DRI Development List-Id: dri-devel@lists.freedesktop.org --===============1226875047== Content-Type: multipart/signed; boundary="nextPart9689371.yLskAc1yW3"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPart9689371.yLskAc1yW3 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" On Tuesday, August 1, 2017 3:47:53 PM PDT Ben Widawsky wrote: > On 17-08-01 15:43:50, Kenneth Graunke wrote: > >On Tuesday, August 1, 2017 9:58:17 AM PDT Ben Widawsky wrote: > >> v2: > >> - Support sprite plane. > >> - Support pipe C/D limitation on GEN9. > >> > >> v3: > >> - Rename structure (Ville) > >> - Handle GLK (Ville) > >> > >> v4: > >> - Fix PIPE_C check, introduced in v2 (Daniel) > >> - Whitespace fix (Daniel) > >> > >> Cc: Daniel Stone > >> Cc: Kristian H=F8gsberg > >> Signed-off-by: Ben Widawsky > >> --- > >> drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++++++= =2D-- > >> drivers/gpu/drm/i915/intel_sprite.c | 28 +++++++++++++++++++++++++++- > >> 2 files changed, 54 insertions(+), 4 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i9= 15/intel_display.c > >> index ad49b99ef25f..0dc9f40edc7e 100644 > >> --- a/drivers/gpu/drm/i915/intel_display.c > >> +++ b/drivers/gpu/drm/i915/intel_display.c > >> @@ -93,7 +93,17 @@ static const uint32_t skl_primary_formats[] =3D { > >> DRM_FORMAT_VYUY, > >> }; > >> > >> -static const uint64_t skl_format_modifiers[] =3D { > >> +static const uint64_t skl_format_modifiers_noccs[] =3D { > >> + I915_FORMAT_MOD_Yf_TILED, > >> + I915_FORMAT_MOD_Y_TILED, > >> + I915_FORMAT_MOD_X_TILED, > >> + DRM_FORMAT_MOD_LINEAR, > >> + DRM_FORMAT_MOD_INVALID > >> +}; > >> + > >> +static const uint64_t skl_format_modifiers_ccs[] =3D { > >> + I915_FORMAT_MOD_Yf_TILED_CCS, > >> + I915_FORMAT_MOD_Y_TILED_CCS, > >> I915_FORMAT_MOD_Yf_TILED, > >> I915_FORMAT_MOD_Y_TILED, > >> I915_FORMAT_MOD_X_TILED, > >> @@ -13853,6 +13863,10 @@ static bool skl_mod_supported(uint32_t format= , uint64_t modifier) > >> case DRM_FORMAT_XBGR8888: > >> case DRM_FORMAT_ARGB8888: > >> case DRM_FORMAT_ABGR8888: > >> + if (modifier =3D=3D I915_FORMAT_MOD_Yf_TILED_CCS || > >> + modifier =3D=3D I915_FORMAT_MOD_Y_TILED_CCS) > >> + return true; > >> + /* fall through */ > >> case DRM_FORMAT_RGB565: > >> case DRM_FORMAT_XRGB2101010: > >> case DRM_FORMAT_XBGR2101010: > >> @@ -14099,10 +14113,20 @@ intel_primary_plane_create(struct drm_i915_p= rivate *dev_priv, enum pipe pipe) > >> primary->frontbuffer_bit =3D INTEL_FRONTBUFFER_PRIMARY(pipe); > >> primary->check_plane =3D intel_check_primary_plane; > >> > >> - if (INTEL_GEN(dev_priv) >=3D 9) { > >> + if (INTEL_GEN(dev_priv) >=3D 10 || IS_GEMINILAKE(dev_priv)) { > >> + intel_primary_formats =3D skl_primary_formats; > >> + num_formats =3D ARRAY_SIZE(skl_primary_formats); > >> + modifiers =3D skl_format_modifiers_ccs; > >> + > >> + primary->update_plane =3D skylake_update_primary_plane; > >> + primary->disable_plane =3D skylake_disable_primary_plane; > >> + } else if (INTEL_GEN(dev_priv) >=3D 9) { > >> intel_primary_formats =3D skl_primary_formats; > >> num_formats =3D ARRAY_SIZE(skl_primary_formats); > >> - modifiers =3D skl_format_modifiers; > >> + if (pipe < PIPE_C) > >> + modifiers =3D skl_format_modifiers_ccs; > >> + else > >> + modifiers =3D skl_format_modifiers_noccs; > >> > >> primary->update_plane =3D skylake_update_primary_plane; > >> primary->disable_plane =3D skylake_disable_primary_plane; > >> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i91= 5/intel_sprite.c > >> index b1cc4835b963..5a2b3f3693a6 100644 > >> --- a/drivers/gpu/drm/i915/intel_sprite.c > >> +++ b/drivers/gpu/drm/i915/intel_sprite.c > >> @@ -1085,7 +1085,17 @@ static uint32_t skl_plane_formats[] =3D { > >> DRM_FORMAT_VYUY, > >> }; > >> > >> +static const uint64_t skl_plane_format_modifiers_noccs[] =3D { > >> + I915_FORMAT_MOD_Yf_TILED, > >> + I915_FORMAT_MOD_Y_TILED, > >> + I915_FORMAT_MOD_X_TILED, > >> + DRM_FORMAT_MOD_LINEAR, > >> + DRM_FORMAT_MOD_INVALID > >> +}; > >> + > >> static const uint64_t skl_plane_format_modifiers[] =3D { > >> + I915_FORMAT_MOD_Yf_TILED_CCS, > >> + I915_FORMAT_MOD_Y_TILED_CCS, > >> I915_FORMAT_MOD_Yf_TILED, > >> I915_FORMAT_MOD_Y_TILED, > >> I915_FORMAT_MOD_X_TILED, > >> @@ -1148,6 +1158,9 @@ static bool skl_sprite_plane_format_mod_supporte= d(struct drm_plane *plane, > >> case DRM_FORMAT_XBGR8888: > >> case DRM_FORMAT_ARGB8888: > >> case DRM_FORMAT_ABGR8888: > >> + if (modifier =3D=3D I915_FORMAT_MOD_Y_TILED_CCS || > >> + modifier =3D=3D I915_FORMAT_MOD_Yf_TILED_CCS) > >> + return true; > >> case DRM_FORMAT_RGB565: > >> case DRM_FORMAT_XRGB2101010: > >> case DRM_FORMAT_XBGR2101010: > >> @@ -1230,7 +1243,7 @@ intel_sprite_plane_create(struct drm_i915_privat= e *dev_priv, > >> } > >> intel_plane->base.state =3D &state->base; > >> > >> - if (INTEL_GEN(dev_priv) >=3D 9) { > >> + if (INTEL_GEN(dev_priv) >=3D 10) { > > > >I think this should be INTEL_GEN(dev_priv) >=3D 10 || IS_GEMINILAKE(dev_= priv). > > > >With that fixed, this patch would be: > >Reviewed-by: Kenneth Graunke > > > >for what it's worth (I'm not that familiar with display). > > >=20 > Thanks. Here is what I've changed locally which didn't match the primary > support: >=20 > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/i= ntel_sprite.c > index 5a2b3f3693a6..1c484195fd0f 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -1093,7 +1093,7 @@ static const uint64_t skl_plane_format_modifiers_no= ccs[] =3D { > DRM_FORMAT_MOD_INVALID > }; > =20 > -static const uint64_t skl_plane_format_modifiers[] =3D { > +static const uint64_t skl_plane_format_modifiers_ccs[] =3D { > I915_FORMAT_MOD_Yf_TILED_CCS, > I915_FORMAT_MOD_Y_TILED_CCS, > I915_FORMAT_MOD_Yf_TILED, > @@ -1243,7 +1243,7 @@ intel_sprite_plane_create(struct drm_i915_private *= dev_priv, > } > intel_plane->base.state =3D &state->base; > =20 > - if (INTEL_GEN(dev_priv) >=3D 10) { > + if (INTEL_GEN(dev_priv) >=3D 10 || IS_GEMINILAKE(dev_priv)) { > intel_plane->can_scale =3D true; > state->scaler_id =3D -1; > =20 > @@ -1252,7 +1252,7 @@ intel_sprite_plane_create(struct drm_i915_private *= dev_priv, > =20 > plane_formats =3D skl_plane_formats; > num_plane_formats =3D ARRAY_SIZE(skl_plane_formats); > - modifiers =3D skl_plane_format_modifiers; > + modifiers =3D skl_plane_format_modifiers_ccs; > } else if (INTEL_GEN(dev_priv) >=3D 9) { > intel_plane->can_scale =3D true; > state->scaler_id =3D -1; > @@ -1262,10 +1262,10 @@ intel_sprite_plane_create(struct drm_i915_private= *dev_priv, > =20 > plane_formats =3D skl_plane_formats; > num_plane_formats =3D ARRAY_SIZE(skl_plane_formats); > - if (pipe >=3D PIPE_C) > - modifiers =3D skl_plane_format_modifiers_noccs; > + if (pipe < PIPE_C) > + modifiers =3D skl_plane_format_modifiers_ccs; > else > - modifiers =3D skl_plane_format_modifiers; > + modifiers =3D skl_plane_format_modifiers_noccs; > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > intel_plane->can_scale =3D false; That looks good, with that squashed in, Reviewed-by: Kenneth Graunke --nextPart9689371.yLskAc1yW3 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. Content-Transfer-Encoding: 7Bit -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE6OtbNAgc4e6ibv4ZW1vaBx1JzDgFAlmBBjYACgkQW1vaBx1J zDjmPQ/+L21GKi/nA6bzRLdOsfzbXgTWs4/15simWjqNV3QS3bL8hccrj740kyfx HpBUYy63wxoYjk045KrQI2qwh2qGFbNoSDfArojK1LHnGi8XQ33cio3KyqAdkFVj NeU+xQX46j3tgsccgxlTTQ9Rqq5LhJrtrkEWimJUB9WtU+pimqJG2byVSujRU7ay vrFIw2T0hv/jXQkUj93UxEliLkEy/4r+ww1Z8nSI24/Ry+UsjFYRrhPJ/5rVcb2T fKhoiHhMGo5yVRy6zo1d5THcTKexQYq18EbUNZLRnBa6NFqtksHE5GfiUsWB7sg5 0DbyQypctobHXAAJdX6YyRcn6bJddG6s6wc125sxRmNG5OnVKvv/0feMVjlSj3wd TiyNJGVjh41EEsyJVXjSWv+XEQ7UGJAY0qSmHP65J5YQ3B3JA+G6VoX7XLKechJX kpZzHGPYFm3ZLv+U0WQyO+cuJ5R+EoICDNt6RqyIYyzuzqNuloOCTPKBiSCs1VmW IrMR85TxFqNarzi7lfoF2HlIQgDuATVqmbPoWGaIvFZLIJ9dBnJcdZ9j5drQ324v b+5QF65j+B90oYXnoJPKZc8CC3MJ0nC7mXArMuM7HGNdL8XZWc05FylbGGR63uWm sKWFmH02aWGSnv6eQ1BEOFtX8eE/aTX1AtfOa85ujA55GCxl3Vs= =OfnE -----END PGP SIGNATURE----- --nextPart9689371.yLskAc1yW3-- --===============1226875047== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============1226875047==--