Re: [PATCH v2 08/11] drm/i915/psr: Check if source supports sink specific SU granularity

["Souza, Jose" <jose.souza@intel.com>]

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On Mon, 2018-12-03 at 12:59 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > According to eDP spec, sink can required specific selective update
> > granularity that source must comply.
> > Here caching the value if required and checking if source supports
> > it.
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h  |  1 +
> >  drivers/gpu/drm/i915/intel_psr.c | 21 ++++++++++++++++++++-
> >  2 files changed, 21 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 43ac6873a2bb..0727d8051dd3 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -507,6 +507,7 @@ struct i915_psr {
> >  	ktime_t last_exit;
> >  	bool sink_not_reliable;
> >  	bool irq_aux_error;
> > +	u16 su_x_granularity;
> >  };
> >  
> >  enum intel_pch {
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 282ff1bc68a7..f9eccaac850a 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -261,6 +261,23 @@ static u8
> > intel_dp_get_sink_sync_latency(struct
> > intel_dp *intel_dp)
> >  	return val;
> >  }
> >  
> > +static u16 intel_dp_get_su_x_granulartiy(struct intel_dp
> > *intel_dp)
> > +{
> > +	u16 val;
> > +	ssize_t r;
> > +
> > +	if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
> > {
> > +		/* Returning the default X granularity */
> > +		return 4;
> > +	}
> nit: Braces not needed, you could move the comment a line above.
> 
> A value of 0 in this DPCD indicates there is no granularity
> requirement, why assume 4? 

Like you said bellow, 4 is the default granularity if this is not set.

> 
> > +
> > +	r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY,
> > &val, 2);
> > +	if (r != 2)
> > +		DRM_WARN("Unable to read DP_PSR2_SU_X_GRANULARITY\n");
> Please change this to the warning level that we use elsewhere for aux
> failures.

So changing to DRM_DEBUG_KMS()

> 
> If I'm reading the spec correctly, a value of 0 in this DPCD means
> the
> sink expects a granularity of 4, so returning 0 would be incorrect.
> 
> > +
> > +	return val;
> Assume the default value of 4 if aux read fails (after printing an
> error)
> 

Done


> > +}
> > +
> >  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> >  {
> >  	struct drm_i915_private *dev_priv =
> > @@ -315,6 +332,8 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> >  		if (dev_priv->psr.sink_psr2_support) {
> >  			dev_priv->psr.colorimetry_support =
> >  				intel_dp_get_colorimetry_status(intel_d
> > p);
> > +			dev_priv->psr.su_x_granularity =
> > +				intel_dp_get_su_x_granulartiy(intel_dp)
> > ;
> >  		}
> >  	}
> >  }
> > @@ -546,7 +565,7 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >  	 * at each 4 lines with height of 4 lines, what eDP states
> >  	 * that sink should support.
> >  	 */
> > -	if (crtc_hdisplay % 4) {
> > +	if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
> >  		DRM_DEBUG_KMS("PSR2 not enabled, default SU granularity
> > not match\n");
> >  		return false;
> >  	}

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