From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex Deucher Subject: [PATCH] drm/radeon/kms: the SS_Id field in the LCD table if for LVDS only Date: Fri, 20 May 2011 12:36:11 -0400 Message-ID: <1305909372-22095-1-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qw0-f49.google.com (mail-qw0-f49.google.com [209.85.216.49]) by gabe.freedesktop.org (Postfix) with ESMTP id B65419EEA4 for ; Fri, 20 May 2011 09:36:20 -0700 (PDT) Received: by qwi2 with SMTP id 2so2344013qwi.36 for ; Fri, 20 May 2011 09:36:20 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: airlied@gmail.com, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org For DP/eDP, always use the standard DP SS indices. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_crtc.c | 42 +++++++++---------------------- 1 files changed, 12 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index dab06fb..bbd6c59 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -940,42 +940,24 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode case ATOM_ENCODER_MODE_DP: /* DP/eDP */ dp_clock = dig_connector->dp_clock / 10; - if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { - if (ASIC_IS_DCE4(rdev)) { - /* first try ASIC_INTERNAL_SS_ON_DP */ + if (ASIC_IS_DCE4(rdev)) + ss_enabled = + radeon_atombios_get_asic_ss_info(rdev, &ss, + ASIC_INTERNAL_SS_ON_DP, + dp_clock); + else { + if (dp_clock == 16200) { ss_enabled = - radeon_atombios_get_asic_ss_info(rdev, &ss, - ASIC_INTERNAL_SS_ON_DP, - dp_clock); + radeon_atombios_get_ppll_ss_info(rdev, &ss, + ATOM_DP_SS_ID2); if (!ss_enabled) ss_enabled = - radeon_atombios_get_asic_ss_info(rdev, &ss, - dig->lcd_ss_id, - dp_clock); + radeon_atombios_get_ppll_ss_info(rdev, &ss, + ATOM_DP_SS_ID1); } else ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss, - dig->lcd_ss_id); - } else { - if (ASIC_IS_DCE4(rdev)) - ss_enabled = - radeon_atombios_get_asic_ss_info(rdev, &ss, - ASIC_INTERNAL_SS_ON_DP, - dp_clock); - else { - if (dp_clock == 16200) { - ss_enabled = - radeon_atombios_get_ppll_ss_info(rdev, &ss, - ATOM_DP_SS_ID2); - if (!ss_enabled) - ss_enabled = - radeon_atombios_get_ppll_ss_info(rdev, &ss, - ATOM_DP_SS_ID1); - } else - ss_enabled = - radeon_atombios_get_ppll_ss_info(rdev, &ss, - ATOM_DP_SS_ID1); - } + ATOM_DP_SS_ID1); } break; case ATOM_ENCODER_MODE_LVDS: -- 1.7.1.1