From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex Deucher Subject: [PATCH] drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices Date: Fri, 20 May 2011 12:36:12 -0400 Message-ID: <1305909372-22095-2-git-send-email-alexdeucher@gmail.com> References: <1305909372-22095-1-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qy0-f177.google.com (mail-qy0-f177.google.com [209.85.216.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 4530A9ED2D for ; Fri, 20 May 2011 09:36:21 -0700 (PDT) Received: by qyl38 with SMTP id 38so2505831qyl.15 for ; Fri, 20 May 2011 09:36:21 -0700 (PDT) In-Reply-To: <1305909372-22095-1-git-send-email-alexdeucher@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: airlied@gmail.com, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_crtc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index bbd6c59..48f5ff0 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -815,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, args.v3.ucPostDiv = post_div; args.v3.ucPpll = pll_id; args.v3.ucMiscInfo = (pll_id << 2); + if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) + args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; args.v3.ucTransmitterId = encoder_id; args.v3.ucEncoderMode = encoder_mode; break; -- 1.7.1.1