From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexdeucher@gmail.com Subject: [PATCH] drm/radeon/kms: make sure pci max read request size is valid on evergreen+ Date: Thu, 1 Sep 2011 13:05:15 -0400 Message-ID: <1314896715-7870-1-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qy0-f177.google.com (mail-qy0-f177.google.com [209.85.216.177]) by gabe.freedesktop.org (Postfix) with ESMTP id C22CC9EE99 for ; Thu, 1 Sep 2011 10:05:23 -0700 (PDT) Received: by qyk2 with SMTP id 2so1156905qyk.15 for ; Thu, 01 Sep 2011 10:05:23 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: airlied@gmail.com, dri-devel@lists.freedesktop.org Cc: Alex Deucher , stable@kernel.org List-Id: dri-devel@lists.freedesktop.org From: Alex Deucher If the bios or OS sets the pci max read request size to 0 or an invalid value (6,7), it can result in a hang or slowdown. Check and set it to something sane if it's invalid. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=42162 Signed-off-by: Alex Deucher Cc: stable@kernel.org --- drivers/gpu/drm/radeon/evergreen.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/radeon/ni.c | 3 +++ 2 files changed, 27 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index d8b725d..1e040f5 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -41,6 +41,28 @@ static void evergreen_gpu_init(struct radeon_device *rdev); void evergreen_fini(struct radeon_device *rdev); static void evergreen_pcie_gen2_enable(struct radeon_device *rdev); +#define PCI_DEVICE_CNTL 0x60 +#define PCI_MAX_READ_REQUEST_SIZE_SHIFT 12 +#define PCI_MAX_READ_REQUEST_SIZE_MASK (7 << 12) + +void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) +{ + u16 tmp; + + pci_read_config_word(rdev->pdev, PCI_DEVICE_CNTL, &tmp); + + /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it + * to avoid hangs or perfomance issues + */ + if ((((tmp & PCI_MAX_READ_REQUEST_SIZE_MASK) >> PCI_MAX_READ_REQUEST_SIZE_SHIFT) == 0) || + (((tmp & PCI_MAX_READ_REQUEST_SIZE_MASK) >> PCI_MAX_READ_REQUEST_SIZE_SHIFT) == 6) || + (((tmp & PCI_MAX_READ_REQUEST_SIZE_MASK) >> PCI_MAX_READ_REQUEST_SIZE_SHIFT) == 7)) { + tmp &= ~PCI_MAX_READ_REQUEST_SIZE_MASK; + tmp |= (2 << PCI_MAX_READ_REQUEST_SIZE_SHIFT); + pci_write_config_word(rdev->pdev, PCI_DEVICE_CNTL, tmp); + } +} + void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) { /* enable the pflip int */ @@ -1865,6 +1887,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + evergreen_fix_pci_max_read_req_size(rdev); + cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; cc_gc_shader_pipe_config |= diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index d916c82..d6cb534 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -39,6 +39,7 @@ extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); extern void evergreen_mc_program(struct radeon_device *rdev); extern void evergreen_irq_suspend(struct radeon_device *rdev); extern int evergreen_mc_init(struct radeon_device *rdev); +extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); #define EVERGREEN_PFP_UCODE_SIZE 1120 #define EVERGREEN_PM4_UCODE_SIZE 1376 @@ -724,6 +725,8 @@ static void cayman_gpu_init(struct radeon_device *rdev) WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); + evergreen_fix_pci_max_read_req_size(rdev); + mc_shared_chmap = RREG32(MC_SHARED_CHMAP); mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); -- 1.7.1.1