From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexdeucher@gmail.com Subject: [drm-next 13/14] drm/radeon/kms: reorganize surface callbacks Date: Thu, 23 Feb 2012 17:53:49 -0500 Message-ID: <1330037630-1895-14-git-send-email-alexdeucher@gmail.com> References: <1330037630-1895-1-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qy0-f177.google.com (mail-qy0-f177.google.com [209.85.216.177]) by gabe.freedesktop.org (Postfix) with ESMTP id F21619E82F for ; Thu, 23 Feb 2012 14:54:07 -0800 (PST) Received: by mail-qy0-f177.google.com with SMTP id u28so176901qcs.36 for ; Thu, 23 Feb 2012 14:54:07 -0800 (PST) In-Reply-To: <1330037630-1895-1-git-send-email-alexdeucher@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: airlied@gmail.com, dri-devel@lists.freedesktop.org Cc: Alex Deucher List-Id: dri-devel@lists.freedesktop.org From: Alex Deucher tidy up the radeon_asic struct. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h | 14 +++-- drivers/gpu/drm/radeon/radeon_asic.c | 103 ++++++++++++++++++++++------------ 2 files changed, 76 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 88dacc5..5077478 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1186,10 +1186,12 @@ struct radeon_asic { u32 copy_ring_index; } copy; - int (*set_surface_reg)(struct radeon_device *rdev, int reg, - uint32_t tiling_flags, uint32_t pitch, - uint32_t offset, uint32_t obj_size); - void (*clear_surface_reg)(struct radeon_device *rdev, int reg); + struct { + int (*set_reg)(struct radeon_device *rdev, int reg, + uint32_t tiling_flags, uint32_t pitch, + uint32_t offset, uint32_t obj_size); + void (*clear_reg)(struct radeon_device *rdev, int reg); + } surface; struct { void (*init)(struct radeon_device *rdev); @@ -1705,8 +1707,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) -#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) -#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) +#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) +#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 4eaa5f1..0a59f48 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -168,8 +168,10 @@ static struct radeon_asic r100_asic = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &r100_hpd_init, .fini = &r100_hpd_fini, @@ -240,8 +242,10 @@ static struct radeon_asic r200_asic = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &r100_hpd_init, .fini = &r100_hpd_fini, @@ -312,8 +316,10 @@ static struct radeon_asic r300_asic = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &r100_hpd_init, .fini = &r100_hpd_fini, @@ -384,8 +390,10 @@ static struct radeon_asic r300_asic_pcie = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &r100_hpd_init, .fini = &r100_hpd_fini, @@ -456,9 +464,10 @@ static struct radeon_asic r420_asic = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, - + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &r100_hpd_init, .fini = &r100_hpd_fini, @@ -529,8 +538,10 @@ static struct radeon_asic rs400_asic = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &r100_hpd_init, .fini = &r100_hpd_fini, @@ -601,8 +612,10 @@ static struct radeon_asic rs600_asic = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &rs600_hpd_init, .fini = &rs600_hpd_fini, @@ -673,8 +686,10 @@ static struct radeon_asic rs690_asic = { .copy = &r200_copy_dma, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &rs600_hpd_init, .fini = &rs600_hpd_fini, @@ -745,8 +760,10 @@ static struct radeon_asic rv515_asic = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &rs600_hpd_init, .fini = &rs600_hpd_fini, @@ -817,8 +834,10 @@ static struct radeon_asic r520_asic = { .copy = &r100_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r100_set_surface_reg, - .clear_surface_reg = r100_clear_surface_reg, + .surface = { + .set_reg = r100_set_surface_reg, + .clear_reg = r100_clear_surface_reg, + }, .hpd = { .init = &rs600_hpd_init, .fini = &rs600_hpd_fini, @@ -888,8 +907,10 @@ static struct radeon_asic r600_asic = { .copy = &r600_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r600_set_surface_reg, - .clear_surface_reg = r600_clear_surface_reg, + .surface = { + .set_reg = r600_set_surface_reg, + .clear_reg = r600_clear_surface_reg, + }, .hpd = { .init = &r600_hpd_init, .fini = &r600_hpd_fini, @@ -959,8 +980,10 @@ static struct radeon_asic rs780_asic = { .copy = &r600_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r600_set_surface_reg, - .clear_surface_reg = r600_clear_surface_reg, + .surface = { + .set_reg = r600_set_surface_reg, + .clear_reg = r600_clear_surface_reg, + }, .hpd = { .init = &r600_hpd_init, .fini = &r600_hpd_fini, @@ -1030,8 +1053,10 @@ static struct radeon_asic rv770_asic = { .copy = &r600_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r600_set_surface_reg, - .clear_surface_reg = r600_clear_surface_reg, + .surface = { + .set_reg = r600_set_surface_reg, + .clear_reg = r600_clear_surface_reg, + }, .hpd = { .init = &r600_hpd_init, .fini = &r600_hpd_fini, @@ -1101,8 +1126,10 @@ static struct radeon_asic evergreen_asic = { .copy = &r600_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r600_set_surface_reg, - .clear_surface_reg = r600_clear_surface_reg, + .surface = { + .set_reg = r600_set_surface_reg, + .clear_reg = r600_clear_surface_reg, + }, .hpd = { .init = &evergreen_hpd_init, .fini = &evergreen_hpd_fini, @@ -1172,8 +1199,10 @@ static struct radeon_asic sumo_asic = { .copy = &r600_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r600_set_surface_reg, - .clear_surface_reg = r600_clear_surface_reg, + .surface = { + .set_reg = r600_set_surface_reg, + .clear_reg = r600_clear_surface_reg, + }, .hpd = { .init = &evergreen_hpd_init, .fini = &evergreen_hpd_fini, @@ -1243,8 +1272,10 @@ static struct radeon_asic btc_asic = { .copy = &r600_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r600_set_surface_reg, - .clear_surface_reg = r600_clear_surface_reg, + .surface = { + .set_reg = r600_set_surface_reg, + .clear_reg = r600_clear_surface_reg, + }, .hpd = { .init = &evergreen_hpd_init, .fini = &evergreen_hpd_fini, @@ -1343,8 +1374,10 @@ static struct radeon_asic cayman_asic = { .copy = &r600_copy_blit, .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, }, - .set_surface_reg = r600_set_surface_reg, - .clear_surface_reg = r600_clear_surface_reg, + .surface = { + .set_reg = r600_set_surface_reg, + .clear_reg = r600_clear_surface_reg, + }, .hpd = { .init = &evergreen_hpd_init, .fini = &evergreen_hpd_fini, -- 1.7.7.5