From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/7 v6] drm/i915/intel_i2c: use double-buffered writes Date: Wed, 28 Mar 2012 19:41:21 +0100 Message-ID: <1332960093_131068@CP5-2952> References: <1332959199-32161-1-git-send-email-djkurtz@chromium.org> <1332959199-32161-3-git-send-email-djkurtz@chromium.org> Return-path: In-Reply-To: <1332959199-32161-3-git-send-email-djkurtz@chromium.org> Sender: linux-kernel-owner@vger.kernel.org To: Daniel Vetter , Keith Packard , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Benson Leung , Yufeng Shen , Daniel Kurtz List-Id: dri-devel@lists.freedesktop.org On Thu, 29 Mar 2012 02:26:34 +0800, Daniel Kurtz wrote: > The GMBUS controller GMBUS3 register is double-buffered. Take advantage > of this by writing two 4-byte words before the first wait for HW_RDY. > This helps keep the GMBUS controller from becoming idle during long writes. > > Signed-off-by: Daniel Kurtz "For byte counts that are greater than four bytes, this register will be written with subsequent data only after the HW_RDY status bit is set" Hmm, I had interpretted that as should only be. But if you take into account that the register is indeed double-buffered, it does make sense that the hardware itself is only updated after the HW_RDY signal. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre