From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions Date: Wed, 28 Mar 2012 19:52:16 +0100 Message-ID: <1332960747_131180@CP5-2952> References: <1332959199-32161-1-git-send-email-djkurtz@chromium.org> <1332959199-32161-6-git-send-email-djkurtz@chromium.org> Return-path: In-Reply-To: <1332959199-32161-6-git-send-email-djkurtz@chromium.org> Sender: linux-kernel-owner@vger.kernel.org To: Daniel Vetter , Keith Packard , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Benson Leung , Yufeng Shen , Daniel Kurtz List-Id: dri-devel@lists.freedesktop.org On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz wrote: > It is very common for an i2c device to require a small 1 or 2 byte write > followed by a read. For example, when reading from an i2c EEPROM it is > common to write and address, offset or index followed by a reading some > values. Hmm, I have "gmbus1, bits 8-15: 8-bit GMBUS slave register This field is redundant and should not be used." Scary. :) Otherwise, the code itself looks correct and quite neatly done now. -Chris -- Chris Wilson, Intel Open Source Technology Centre