* [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault
@ 2013-09-18 13:39 Michel Dänzer
2013-09-18 13:39 ` [PATCH 2/3] drm/radeon/cik: Fix encoding of number of banks in tiling configuration info Michel Dänzer
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Michel Dänzer @ 2013-09-18 13:39 UTC (permalink / raw)
To: dri-devel
From: Michel Dänzer <michel.daenzer@amd.com>
The string is encoded from the MSB to the LSB of the register.
Cc: stable@vger.kernel.org
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---
drivers/gpu/drm/radeon/cik.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index a77b593..4f1f419 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -4721,12 +4721,13 @@ static void cik_vm_decode_fault(struct radeon_device *rdev,
u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
- char *block = (char *)&mc_client;
+ char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
+ (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
- printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
+ printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
protections, vmid, addr,
(status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
- block, mc_id);
+ block, mc_client, mc_id);
}
/**
--
1.8.4.rc3
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/3] drm/radeon/cik: Fix encoding of number of banks in tiling configuration info 2013-09-18 13:39 [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault Michel Dänzer @ 2013-09-18 13:39 ` Michel Dänzer 2013-09-18 13:39 ` [PATCH 3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well Michel Dänzer 2013-09-18 15:44 ` [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault Alex Deucher 2 siblings, 0 replies; 7+ messages in thread From: Michel Dänzer @ 2013-09-18 13:39 UTC (permalink / raw) To: dri-devel From: Michel Dänzer <michel.daenzer@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> --- drivers/gpu/drm/radeon/cik.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 4f1f419..8feaf51 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -2835,10 +2835,8 @@ static void cik_gpu_init(struct radeon_device *rdev) rdev->config.cik.tile_config |= (3 << 0); break; } - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) - rdev->config.cik.tile_config |= 1 << 4; - else - rdev->config.cik.tile_config |= 0 << 4; + rdev->config.cik.tile_config |= + ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; rdev->config.cik.tile_config |= ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; rdev->config.cik.tile_config |= -- 1.8.4.rc3 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well 2013-09-18 13:39 [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault Michel Dänzer 2013-09-18 13:39 ` [PATCH 2/3] drm/radeon/cik: Fix encoding of number of banks in tiling configuration info Michel Dänzer @ 2013-09-18 13:39 ` Michel Dänzer 2013-09-18 13:56 ` Alex Deucher 2013-09-18 15:44 ` [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault Alex Deucher 2 siblings, 1 reply; 7+ messages in thread From: Michel Dänzer @ 2013-09-18 13:39 UTC (permalink / raw) To: dri-devel From: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> --- Not sure this is necessary, but AFAICT the pipe configuration applies to 1D tiling modes as well. drivers/gpu/drm/radeon/cik.c | 48 +++++++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 8feaf51..35d8247 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -1788,7 +1788,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 5: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); break; case 6: gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | @@ -1808,7 +1809,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 9: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); break; case 10: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -1830,7 +1832,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 13: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); break; case 14: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -1852,7 +1855,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 27: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); break; case 28: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -2007,7 +2011,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 5: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P4_16x16); break; case 6: gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | @@ -2027,7 +2032,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 9: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P4_16x16); break; case 10: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -2049,7 +2055,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 13: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P4_16x16); break; case 14: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -2071,7 +2078,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 27: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P4_16x16); break; case 28: gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | @@ -2133,7 +2141,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 5: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P4_8x16); break; case 6: gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | @@ -2153,7 +2162,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 9: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P4_8x16); break; case 10: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -2175,7 +2185,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 13: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P4_8x16); break; case 14: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -2197,7 +2208,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 27: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P4_8x16); break; case 28: gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | @@ -2352,7 +2364,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 5: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P2); break; case 6: gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | @@ -2371,7 +2384,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 9: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P2); break; case 10: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -2393,7 +2407,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 13: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P2); break; case 14: gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | @@ -2415,7 +2430,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) break; case 27: gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | + PIPE_CONFIG(ADDR_SURF_P2); break; case 28: gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | -- 1.8.4.rc3 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well 2013-09-18 13:39 ` [PATCH 3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well Michel Dänzer @ 2013-09-18 13:56 ` Alex Deucher 2013-09-18 15:55 ` Michel Dänzer 0 siblings, 1 reply; 7+ messages in thread From: Alex Deucher @ 2013-09-18 13:56 UTC (permalink / raw) To: Michel Dänzer; +Cc: Maling list - DRI developers On Wed, Sep 18, 2013 at 9:39 AM, Michel Dänzer <michel@daenzer.net> wrote: > From: Michel Dänzer <michel.daenzer@amd.com> > > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> > --- > > Not sure this is necessary, but AFAICT the pipe configuration applies to > 1D tiling modes as well. I don't think pipe config applies to 1D modes since they are fixed size across asics. > > drivers/gpu/drm/radeon/cik.c | 48 +++++++++++++++++++++++++++++--------------- > 1 file changed, 32 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index 8feaf51..35d8247 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -1788,7 +1788,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 5: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); > break; > case 6: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -1808,7 +1809,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 9: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); > break; > case 10: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -1830,7 +1832,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 13: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); > break; > case 14: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -1852,7 +1855,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 27: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16); > break; > case 28: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2007,7 +2011,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 5: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_16x16); > break; > case 6: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2027,7 +2032,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 9: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_16x16); > break; > case 10: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2049,7 +2055,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 13: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_16x16); > break; > case 14: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2071,7 +2078,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 27: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_16x16); > break; > case 28: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2133,7 +2141,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 5: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16); > break; > case 6: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2153,7 +2162,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 9: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16); > break; > case 10: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2175,7 +2185,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 13: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16); > break; > case 14: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2197,7 +2208,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 27: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16); > break; > case 28: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2352,7 +2364,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 5: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P2); > break; > case 6: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > @@ -2371,7 +2384,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 9: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P2); > break; > case 10: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2393,7 +2407,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 13: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P2); > break; > case 14: > gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > @@ -2415,7 +2430,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) > break; > case 27: > gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); > + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) | > + PIPE_CONFIG(ADDR_SURF_P2); > break; > case 28: > gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | > -- > 1.8.4.rc3 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well 2013-09-18 13:56 ` Alex Deucher @ 2013-09-18 15:55 ` Michel Dänzer 2013-09-18 16:00 ` Alex Deucher 0 siblings, 1 reply; 7+ messages in thread From: Michel Dänzer @ 2013-09-18 15:55 UTC (permalink / raw) To: Alex Deucher; +Cc: Maling list - DRI developers On Mit, 2013-09-18 at 09:56 -0400, Alex Deucher wrote: > On Wed, Sep 18, 2013 at 9:39 AM, Michel Dänzer <michel@daenzer.net> wrote: > > From: Michel Dänzer <michel.daenzer@amd.com> > > > > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> > > --- > > > > Not sure this is necessary, but AFAICT the pipe configuration applies to > > 1D tiling modes as well. > > I don't think pipe config applies to 1D modes since they are fixed > size across asics. Makes sense. I noticed that we're setting pipe config for 1D tiling modes on SI as well, and the documentation I saw didn't explicitly say that it only applies to 2D tiling. Maybe we should remove the setting of pipe config and friends for 1D tiling modes on SI instead? -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Debian, X and DRI developer _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well 2013-09-18 15:55 ` Michel Dänzer @ 2013-09-18 16:00 ` Alex Deucher 0 siblings, 0 replies; 7+ messages in thread From: Alex Deucher @ 2013-09-18 16:00 UTC (permalink / raw) To: Michel Dänzer; +Cc: Maling list - DRI developers On Wed, Sep 18, 2013 at 11:55 AM, Michel Dänzer <michel@daenzer.net> wrote: > On Mit, 2013-09-18 at 09:56 -0400, Alex Deucher wrote: >> On Wed, Sep 18, 2013 at 9:39 AM, Michel Dänzer <michel@daenzer.net> wrote: >> > From: Michel Dänzer <michel.daenzer@amd.com> >> > >> > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> >> > --- >> > >> > Not sure this is necessary, but AFAICT the pipe configuration applies to >> > 1D tiling modes as well. >> >> I don't think pipe config applies to 1D modes since they are fixed >> size across asics. > > Makes sense. I noticed that we're setting pipe config for 1D tiling > modes on SI as well, and the documentation I saw didn't explicitly say > that it only applies to 2D tiling. > > Maybe we should remove the setting of pipe config and friends for 1D > tiling modes on SI instead? > I suppose we should try and double check. The tiling settings spreadsheets sets the fields for SI, but no CIK, but I don't think the hw actually needs it. Alex > > -- > Earthling Michel Dänzer | http://www.amd.com > Libre software enthusiast | Debian, X and DRI developer > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault 2013-09-18 13:39 [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault Michel Dänzer 2013-09-18 13:39 ` [PATCH 2/3] drm/radeon/cik: Fix encoding of number of banks in tiling configuration info Michel Dänzer 2013-09-18 13:39 ` [PATCH 3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well Michel Dänzer @ 2013-09-18 15:44 ` Alex Deucher 2 siblings, 0 replies; 7+ messages in thread From: Alex Deucher @ 2013-09-18 15:44 UTC (permalink / raw) To: Michel Dänzer; +Cc: Maling list - DRI developers On Wed, Sep 18, 2013 at 9:39 AM, Michel Dänzer <michel@daenzer.net> wrote: > From: Michel Dänzer <michel.daenzer@amd.com> > > The string is encoded from the MSB to the LSB of the register. > > Cc: stable@vger.kernel.org > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Patches 1 and 2 applied. I don't think the 3rd one is necessary. Thanks! Alex > --- > drivers/gpu/drm/radeon/cik.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c > index a77b593..4f1f419 100644 > --- a/drivers/gpu/drm/radeon/cik.c > +++ b/drivers/gpu/drm/radeon/cik.c > @@ -4721,12 +4721,13 @@ static void cik_vm_decode_fault(struct radeon_device *rdev, > u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT; > u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT; > u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT; > - char *block = (char *)&mc_client; > + char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, > + (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; > > - printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", > + printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", > protections, vmid, addr, > (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read", > - block, mc_id); > + block, mc_client, mc_id); > } > > /** > -- > 1.8.4.rc3 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-09-18 16:00 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-09-18 13:39 [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault Michel Dänzer 2013-09-18 13:39 ` [PATCH 2/3] drm/radeon/cik: Fix encoding of number of banks in tiling configuration info Michel Dänzer 2013-09-18 13:39 ` [PATCH 3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well Michel Dänzer 2013-09-18 13:56 ` Alex Deucher 2013-09-18 15:55 ` Michel Dänzer 2013-09-18 16:00 ` Alex Deucher 2013-09-18 15:44 ` [PATCH 1/3] drm/radeon/cik: Fix printing of client name on VM protection fault Alex Deucher
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