* [PATCH 1/2] drm/radeon: fix render backend setup for SI and CIK
@ 2013-12-22 1:18 Marek Olšák
2013-12-22 1:18 ` [PATCH 2/2] drm/radeon: expose render backend mask to the userspace Marek Olšák
2013-12-23 15:02 ` [PATCH 1/2] drm/radeon: fix render backend setup for SI and CIK Alex Deucher
0 siblings, 2 replies; 3+ messages in thread
From: Marek Olšák @ 2013-12-22 1:18 UTC (permalink / raw)
To: dri-devel
From: Marek Olšák <marek.olsak@amd.com>
Only the render backends of the first shader engine were enabled. The others
were erroneously disabled. Enabling the other render backends improves
performance a lot.
Unigine Sanctuary on Bonaire:
Before: 15 fps
After: 90 fps
Judging from the fan noise, the GPU was also underclocked when the other
render backends were disabled, resulting in horrible performance. The fan is
a lot noisy under load now.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
drivers/gpu/drm/radeon/cik.c | 10 +++++-----
drivers/gpu/drm/radeon/si.c | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index b43a3a3..138a776 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3057,7 +3057,7 @@ static u32 cik_create_bitmask(u32 bit_width)
* Returns the disabled RB bitmask.
*/
static u32 cik_get_rb_disabled(struct radeon_device *rdev,
- u32 max_rb_num, u32 se_num,
+ u32 max_rb_num_per_se,
u32 sh_per_se)
{
u32 data, mask;
@@ -3071,7 +3071,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
data >>= BACKEND_DISABLE_SHIFT;
- mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se);
+ mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
return data & mask;
}
@@ -3088,7 +3088,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
*/
static void cik_setup_rb(struct radeon_device *rdev,
u32 se_num, u32 sh_per_se,
- u32 max_rb_num)
+ u32 max_rb_num_per_se)
{
int i, j;
u32 data, mask;
@@ -3098,7 +3098,7 @@ static void cik_setup_rb(struct radeon_device *rdev,
for (i = 0; i < se_num; i++) {
for (j = 0; j < sh_per_se; j++) {
cik_select_se_sh(rdev, i, j);
- data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
+ data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
if (rdev->family == CHIP_HAWAII)
disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
else
@@ -3108,7 +3108,7 @@ static void cik_setup_rb(struct radeon_device *rdev,
cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
mask = 1;
- for (i = 0; i < max_rb_num; i++) {
+ for (i = 0; i < max_rb_num_per_se * se_num; i++) {
if (!(disabled_rbs & mask))
enabled_rbs |= mask;
mask <<= 1;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index a36736d..3eed9a1 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2811,7 +2811,7 @@ static void si_setup_spi(struct radeon_device *rdev,
}
static u32 si_get_rb_disabled(struct radeon_device *rdev,
- u32 max_rb_num, u32 se_num,
+ u32 max_rb_num_per_se,
u32 sh_per_se)
{
u32 data, mask;
@@ -2825,14 +2825,14 @@ static u32 si_get_rb_disabled(struct radeon_device *rdev,
data >>= BACKEND_DISABLE_SHIFT;
- mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
+ mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
return data & mask;
}
static void si_setup_rb(struct radeon_device *rdev,
u32 se_num, u32 sh_per_se,
- u32 max_rb_num)
+ u32 max_rb_num_per_se)
{
int i, j;
u32 data, mask;
@@ -2842,14 +2842,14 @@ static void si_setup_rb(struct radeon_device *rdev,
for (i = 0; i < se_num; i++) {
for (j = 0; j < sh_per_se; j++) {
si_select_se_sh(rdev, i, j);
- data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
+ data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
}
}
si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
mask = 1;
- for (i = 0; i < max_rb_num; i++) {
+ for (i = 0; i < max_rb_num_per_se * se_num; i++) {
if (!(disabled_rbs & mask))
enabled_rbs |= mask;
mask <<= 1;
--
1.8.3.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/radeon: expose render backend mask to the userspace
2013-12-22 1:18 [PATCH 1/2] drm/radeon: fix render backend setup for SI and CIK Marek Olšák
@ 2013-12-22 1:18 ` Marek Olšák
2013-12-23 15:02 ` [PATCH 1/2] drm/radeon: fix render backend setup for SI and CIK Alex Deucher
1 sibling, 0 replies; 3+ messages in thread
From: Marek Olšák @ 2013-12-22 1:18 UTC (permalink / raw)
To: dri-devel
From: Marek Olšák <marek.olsak@amd.com>
This will allow userspace to correctly program the PA_SC_RASTER_CONFIG
register, so it can be considered a fix.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
drivers/gpu/drm/radeon/cik.c | 2 ++
drivers/gpu/drm/radeon/radeon.h | 4 ++--
drivers/gpu/drm/radeon/radeon_kms.c | 9 +++++++++
drivers/gpu/drm/radeon/si.c | 2 ++
include/uapi/drm/radeon_drm.h | 2 ++
5 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 138a776..e950fab 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3114,6 +3114,8 @@ static void cik_setup_rb(struct radeon_device *rdev,
mask <<= 1;
}
+ rdev->config.cik.backend_enable_mask = enabled_rbs;
+
for (i = 0; i < se_num; i++) {
cik_select_se_sh(rdev, i, 0xffffffff);
data = 0;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b1f990d..45e1f44 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1940,7 +1940,7 @@ struct si_asic {
unsigned sc_earlyz_tile_fifo_size;
unsigned num_tile_pipes;
- unsigned num_backends_per_se;
+ unsigned backend_enable_mask;
unsigned backend_disable_mask_per_asic;
unsigned backend_map;
unsigned num_texture_channel_caches;
@@ -1970,7 +1970,7 @@ struct cik_asic {
unsigned sc_earlyz_tile_fifo_size;
unsigned num_tile_pipes;
- unsigned num_backends_per_se;
+ unsigned backend_enable_mask;
unsigned backend_disable_mask_per_asic;
unsigned backend_map;
unsigned num_texture_channel_caches;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 55d0b47..21d593c 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -461,6 +461,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
case RADEON_INFO_SI_CP_DMA_COMPUTE:
*value = 1;
break;
+ case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
+ if (rdev->family >= CHIP_BONAIRE) {
+ *value = rdev->config.cik.backend_enable_mask;
+ } else if (rdev->family >= CHIP_TAHITI) {
+ *value = rdev->config.si.backend_enable_mask;
+ } else {
+ DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
+ }
+ break;
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 3eed9a1..85e1edf 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2855,6 +2855,8 @@ static void si_setup_rb(struct radeon_device *rdev,
mask <<= 1;
}
+ rdev->config.si.backend_enable_mask = enabled_rbs;
+
for (i = 0; i < se_num; i++) {
si_select_se_sh(rdev, i, 0xffffffff);
data = 0;
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 2f3f7ea..fe421e8 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -983,6 +983,8 @@ struct drm_radeon_cs {
#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
/* CIK macrotile mode array */
#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
+/* query the number of render backends */
+#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
struct drm_radeon_info {
--
1.8.3.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] drm/radeon: fix render backend setup for SI and CIK
2013-12-22 1:18 [PATCH 1/2] drm/radeon: fix render backend setup for SI and CIK Marek Olšák
2013-12-22 1:18 ` [PATCH 2/2] drm/radeon: expose render backend mask to the userspace Marek Olšák
@ 2013-12-23 15:02 ` Alex Deucher
1 sibling, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2013-12-23 15:02 UTC (permalink / raw)
To: Marek Olšák; +Cc: Maling list - DRI developers
On Sat, Dec 21, 2013 at 8:18 PM, Marek Olšák <maraeo@gmail.com> wrote:
> From: Marek Olšák <marek.olsak@amd.com>
>
> Only the render backends of the first shader engine were enabled. The others
> were erroneously disabled. Enabling the other render backends improves
> performance a lot.
>
> Unigine Sanctuary on Bonaire:
> Before: 15 fps
> After: 90 fps
>
> Judging from the fan noise, the GPU was also underclocked when the other
> render backends were disabled, resulting in horrible performance. The fan is
> a lot noisy under load now.
>
> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Applied the series to my -fixes tree. Thanks!
Alex
> ---
> drivers/gpu/drm/radeon/cik.c | 10 +++++-----
> drivers/gpu/drm/radeon/si.c | 10 +++++-----
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index b43a3a3..138a776 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -3057,7 +3057,7 @@ static u32 cik_create_bitmask(u32 bit_width)
> * Returns the disabled RB bitmask.
> */
> static u32 cik_get_rb_disabled(struct radeon_device *rdev,
> - u32 max_rb_num, u32 se_num,
> + u32 max_rb_num_per_se,
> u32 sh_per_se)
> {
> u32 data, mask;
> @@ -3071,7 +3071,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
>
> data >>= BACKEND_DISABLE_SHIFT;
>
> - mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se);
> + mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
>
> return data & mask;
> }
> @@ -3088,7 +3088,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
> */
> static void cik_setup_rb(struct radeon_device *rdev,
> u32 se_num, u32 sh_per_se,
> - u32 max_rb_num)
> + u32 max_rb_num_per_se)
> {
> int i, j;
> u32 data, mask;
> @@ -3098,7 +3098,7 @@ static void cik_setup_rb(struct radeon_device *rdev,
> for (i = 0; i < se_num; i++) {
> for (j = 0; j < sh_per_se; j++) {
> cik_select_se_sh(rdev, i, j);
> - data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
> + data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
> if (rdev->family == CHIP_HAWAII)
> disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
> else
> @@ -3108,7 +3108,7 @@ static void cik_setup_rb(struct radeon_device *rdev,
> cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
>
> mask = 1;
> - for (i = 0; i < max_rb_num; i++) {
> + for (i = 0; i < max_rb_num_per_se * se_num; i++) {
> if (!(disabled_rbs & mask))
> enabled_rbs |= mask;
> mask <<= 1;
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index a36736d..3eed9a1 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -2811,7 +2811,7 @@ static void si_setup_spi(struct radeon_device *rdev,
> }
>
> static u32 si_get_rb_disabled(struct radeon_device *rdev,
> - u32 max_rb_num, u32 se_num,
> + u32 max_rb_num_per_se,
> u32 sh_per_se)
> {
> u32 data, mask;
> @@ -2825,14 +2825,14 @@ static u32 si_get_rb_disabled(struct radeon_device *rdev,
>
> data >>= BACKEND_DISABLE_SHIFT;
>
> - mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
> + mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
>
> return data & mask;
> }
>
> static void si_setup_rb(struct radeon_device *rdev,
> u32 se_num, u32 sh_per_se,
> - u32 max_rb_num)
> + u32 max_rb_num_per_se)
> {
> int i, j;
> u32 data, mask;
> @@ -2842,14 +2842,14 @@ static void si_setup_rb(struct radeon_device *rdev,
> for (i = 0; i < se_num; i++) {
> for (j = 0; j < sh_per_se; j++) {
> si_select_se_sh(rdev, i, j);
> - data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
> + data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
> disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
> }
> }
> si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
>
> mask = 1;
> - for (i = 0; i < max_rb_num; i++) {
> + for (i = 0; i < max_rb_num_per_se * se_num; i++) {
> if (!(disabled_rbs & mask))
> enabled_rbs |= mask;
> mask <<= 1;
> --
> 1.8.3.2
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2013-12-23 15:02 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2013-12-22 1:18 [PATCH 1/2] drm/radeon: fix render backend setup for SI and CIK Marek Olšák
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2013-12-23 15:02 ` [PATCH 1/2] drm/radeon: fix render backend setup for SI and CIK Alex Deucher
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