* [PATCH 2/2] drm/radeon: set correct number of banks for CIK chips in DCE
2013-12-23 16:11 [PATCH 1/2] drm/radeon: set correct pipe config for Hawaii in DCE Marek Olšák
@ 2013-12-23 16:11 ` Marek Olšák
2013-12-23 16:33 ` [PATCH 1/2] drm/radeon: set correct pipe config for Hawaii " Alex Deucher
1 sibling, 0 replies; 3+ messages in thread
From: Marek Olšák @ 2013-12-23 16:11 UTC (permalink / raw)
To: dri-devel
From: Marek Olšák <marek.olsak@amd.com>
We don't have the NUM_BANKS parameter, so we have to calculate it
from the other parameters. NUM_BANKS is not constant on CIK.
This fixes 2D tiling for the display engine on CIK.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
drivers/gpu/drm/radeon/atombios_crtc.c | 64 +++++++++++++++++++++++-----------
1 file changed, 43 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index ec97bad..0b9621c 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1143,31 +1143,53 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
}
if (tiling_flags & RADEON_TILING_MACRO) {
- if (rdev->family >= CHIP_BONAIRE)
- tmp = rdev->config.cik.tile_config;
- else if (rdev->family >= CHIP_TAHITI)
- tmp = rdev->config.si.tile_config;
- else if (rdev->family >= CHIP_CAYMAN)
- tmp = rdev->config.cayman.tile_config;
- else
- tmp = rdev->config.evergreen.tile_config;
+ evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
- switch ((tmp & 0xf0) >> 4) {
- case 0: /* 4 banks */
- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
- break;
- case 1: /* 8 banks */
- default:
- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
- break;
- case 2: /* 16 banks */
- fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
- break;
+ /* Set NUM_BANKS. */
+ if (rdev->family >= CHIP_BONAIRE) {
+ unsigned tileb, index, num_banks, tile_split_bytes;
+
+ /* Calculate the macrotile mode index. */
+ tile_split_bytes = 64 << tile_split;
+ tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
+ tileb = min(tile_split_bytes, tileb);
+
+ for (index = 0; tileb > 64; index++) {
+ tileb >>= 1;
+ }
+
+ if (index >= 16) {
+ DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
+ target_fb->bits_per_pixel, tile_split);
+ return -EINVAL;
+ }
+
+ num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
+ fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
+ } else {
+ /* SI and older. */
+ if (rdev->family >= CHIP_TAHITI)
+ tmp = rdev->config.si.tile_config;
+ else if (rdev->family >= CHIP_CAYMAN)
+ tmp = rdev->config.cayman.tile_config;
+ else
+ tmp = rdev->config.evergreen.tile_config;
+
+ switch ((tmp & 0xf0) >> 4) {
+ case 0: /* 4 banks */
+ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
+ break;
+ case 1: /* 8 banks */
+ default:
+ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
+ break;
+ case 2: /* 16 banks */
+ fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
+ break;
+ }
}
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
-
- evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
--
1.8.3.2
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] drm/radeon: set correct pipe config for Hawaii in DCE
2013-12-23 16:11 [PATCH 1/2] drm/radeon: set correct pipe config for Hawaii in DCE Marek Olšák
2013-12-23 16:11 ` [PATCH 2/2] drm/radeon: set correct number of banks for CIK chips " Marek Olšák
@ 2013-12-23 16:33 ` Alex Deucher
1 sibling, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2013-12-23 16:33 UTC (permalink / raw)
To: Marek Olšák; +Cc: Maling list - DRI developers
On Mon, Dec 23, 2013 at 11:11 AM, Marek Olšák <maraeo@gmail.com> wrote:
> From: Marek Olšák <marek.olsak@amd.com>
>
> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Series applied to my fixes tree. Thanks!
Alex
> ---
> drivers/gpu/drm/radeon/atombios_crtc.c | 19 ++++++-------------
> 1 file changed, 6 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
> index b197059..ec97bad 100644
> --- a/drivers/gpu/drm/radeon/atombios_crtc.c
> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
> @@ -1180,19 +1180,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
> fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
>
> if (rdev->family >= CHIP_BONAIRE) {
> - u32 num_pipe_configs = rdev->config.cik.max_tile_pipes;
> - u32 num_rb = rdev->config.cik.max_backends_per_se;
> - if (num_pipe_configs > 8)
> - num_pipe_configs = 8;
> - if (num_pipe_configs == 8)
> - fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16);
> - else if (num_pipe_configs == 4) {
> - if (num_rb == 4)
> - fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16);
> - else if (num_rb < 4)
> - fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16);
> - } else if (num_pipe_configs == 2)
> - fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2);
> + /* Read the pipe config from the 2D TILED SCANOUT mode.
> + * It should be the same for the other modes too, but not all
> + * modes set the pipe config field. */
> + u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
> +
> + fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
> } else if ((rdev->family == CHIP_TAHITI) ||
> (rdev->family == CHIP_PITCAIRN))
> fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
> --
> 1.8.3.2
>
> _______________________________________________
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> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
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^ permalink raw reply [flat|nested] 3+ messages in thread