From: "Stéphane Marchesin" <marcheu@chromium.org>
To: dri-devel@lists.freedesktop.org
Cc: "Stéphane Marchesin" <marcheu@chromium.org>, treding@nvidia.com
Subject: [PATCH 3/3] drm/tegra: Fix sequencing
Date: Thu, 22 May 2014 20:32:48 -0700 [thread overview]
Message-ID: <1400815968-1084-3-git-send-email-marcheu@chromium.org> (raw)
In-Reply-To: <1400815968-1084-1-git-send-email-marcheu@chromium.org>
I suspect this is a copy/paste error.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
drivers/gpu/drm/tegra/sor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 43709ee..23fb9b1 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -740,7 +740,7 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
/* stop lane sequencer */
- value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
+ value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
--
1.9.1.423.g4596e3a
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next prev parent reply other threads:[~2014-05-23 3:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-23 3:32 [PATCH 1/3] drm/tegra: Remove pixel clock rounding Stéphane Marchesin
2014-05-23 3:32 ` [PATCH 2/3] drm/tegra: Fix copy/paste error Stéphane Marchesin
2014-05-23 3:32 ` Stéphane Marchesin [this message]
2014-06-05 9:20 ` [PATCH 3/3] drm/tegra: Fix sequencing Thierry Reding
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