Re: ast2400 woes

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Fri, 2014-06-06 at 21:31 +1000, Benjamin Herrenschmidt wrote:

> The spec is pretty tricky to read but seems to indicate that the above
> offset should also work for PIO if needed, however, it seems like the
> X driver is pretty happy to use MMIO unconditionally for them.
> 
> Any objection on me sending you a patch to send (almost) everybody to
> use the MMIO path ?
> 
> The only remaining "issues" with PIO is the EnableVGA / IsVGAEnabled
> path which still uses PIO in X.
> 
> Now, at least on the AST2400, the register in question is also on MMIO
> (3c3, aka VGA_ENABLE_PORT in the above list), but I don't know whether
> that works on all the older chipsets. (YC Chen on CC might have an opinion).

Ok, I think we need YC Chen answers here. Basically from what I can
tell those old "IO" registers and those new "MMIO" ones only differ
by that offset of 0x340.

The question thus boils down to:

 - Are the "3xx" versions only MMIO or PIO as well ?

 - Are the "3xx" version always available on all chips ?

 - Is MMIO always available on all chips ?

IE. Is there a reason why bASTIsVGAEnabled() and vASTEnableVGAMMIO
use the IO ports ? The latter reads 0x43 and writes 0x43 and 0x42,
can it be made to always use MMIO 0x3c3 and write 0x3c3 and 0x3c2 ?

On my AST2400 at least, even when MMIO is disabled, 0x3c3 still
responds so it works but is that valid for all chips ? Or do I need
to favor the PIO path if PIO is available in that case for older
chipsets ?

Thanks !

Cheers,
Ben.