From mboxrd@z Thu Jan 1 00:00:00 1970 From: Inki Dae Subject: [PATCH 2/2] drm/exynos: mipi-dsi: consider non-continuous clock mode Date: Tue, 12 Aug 2014 15:33:06 +0900 Message-ID: <1407825186-5792-3-git-send-email-inki.dae@samsung.com> References: <1407825186-5792-1-git-send-email-inki.dae@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by gabe.freedesktop.org (Postfix) with ESMTP id 7934789DFE for ; Mon, 11 Aug 2014 23:33:16 -0700 (PDT) Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NA6001HVKV9WQ60@mailout4.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 12 Aug 2014 15:33:09 +0900 (KST) In-reply-to: <1407825186-5792-1-git-send-email-inki.dae@samsung.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: a.hajda@samsung.com List-Id: dri-devel@lists.freedesktop.org This patch adds non-continuous clock mode support. Clock mode on Clock Lane is continuous clock by default. So if we want to transmit data in non-continuous clock mode to reduce power consumption, then host driver should clear DSIM_TX_REQUEST_HSCLK. For this, this patch makes the host driver set DSIM_TX_REQUEST_HSCLK only in case that dsi->mode_flags has no MIPI_DSI_CLOCK_NON_CONTINUOUS flag. Signed-off-by: Inki Dae --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 32 +++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 86aebd8..8c43c96 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -493,8 +493,17 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) | DSIM_ESC_PRESCALER(esc_div) | DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) - | DSIM_BYTE_CLK_SRC(0) - | DSIM_TX_REQUEST_HSCLK; + | DSIM_BYTE_CLK_SRC(0); + + /* + * Set DSIM_TX_REQUEST_HSCLK only in case of not requesting + * non-continous clock mode. So if MIPI_DSI_CLOCK_NON_CONTINUOUS, + * then host controller will turn off the HS clock between high-speed + * transmissions. + */ + if (!(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + reg |= DSIM_TX_REQUEST_HSCLK; + writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); return 0; @@ -701,10 +710,29 @@ static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); } +static void exynos_dsi_enable_hs_clock(struct exynos_dsi *dsi, + bool enable) +{ + u32 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); + + reg &= ~DSIM_TX_REQUEST_HSCLK; + if (enable) + reg |= DSIM_TX_REQUEST_HSCLK; + + writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); +} + static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) { u32 reg; + /* + * Set DSIM_TX_REQUEST_HSCLK. In case of video data, host controller + * will transmit the data in HS mode always. + */ + if (enable) + exynos_dsi_enable_hs_clock(dsi, true); + reg = readl(dsi->reg_base + DSIM_MDRESOL_REG); if (enable) reg |= DSIM_MAIN_STAND_BY; -- 1.7.9.5