From: Dave Airlie <airlied@gmail.com>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 06/10] drm/radeon: add some MST registers
Date: Tue, 24 Feb 2015 09:24:00 +1000 [thread overview]
Message-ID: <1424733844-20185-7-git-send-email-airlied@gmail.com> (raw)
In-Reply-To: <1424733844-20185-1-git-send-email-airlied@gmail.com>
From: Dave Airlie <airlied@redhat.com>
These registers will be used later to setup
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/radeon/ni_reg.h | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/radeon/ni_reg.h b/drivers/gpu/drm/radeon/ni_reg.h
index 5db7b7d..96c2371 100644
--- a/drivers/gpu/drm/radeon/ni_reg.h
+++ b/drivers/gpu/drm/radeon/ni_reg.h
@@ -83,4 +83,41 @@
# define NI_REGAMMA_PROG_B 4
# define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4)
+#define NI_DP_MSE_LINK_TIMING 0x73a0
+# define NI_DP_MSE_LINK_FRAME (((x) & 0x3ff) << 0)
+# define NI_DP_MSE_LINK_LINE (((x) & 0x3) << 16)
+
+#define NI_DP_MSE_MISC_CNTL 0x736c
+# define NI_DP_MSE_BLANK_CODE (((x) & 0x1) << 0)
+# define NI_DP_MSE_TIMESTAMP_MODE (((x) & 0x1) << 4)
+# define NI_DP_MSE_ZERO_ENCODER (((x) & 0x1) << 8)
+
+#define NI_DP_MSE_RATE_CNTL 0x7384
+
+#define NI_DP_MSE_RATE_UPDATE 0x738c
+
+#define NI_DP_MSE_SAT0 0x7390
+# define NI_DP_MSE_SAT_SRC0(x) (((x) & 0x7) << 0)
+# define NI_DP_MSE_SAT_SLOT_COUNT0(x) (((x) & 0x3f) << 8)
+# define NI_DP_MSE_SAT_SRC1(x) (((x) & 0x7) << 16)
+# define NI_DP_MSE_SAT_SLOT_COUNT1(x) (((x) & 0x3f) << 24)
+
+#define NI_DP_MSE_SAT1 0x7394
+
+#define NI_DP_MSE_SAT2 0x7398
+
+#define NI_DP_MSE_SAT_UPDATE 0x739c
+
+#define NI_DIG_BE_CNTL 0x7140
+# define NI_DIG_FE_SOURCE_SELECT(x) (((x) & 0x7f) << 8)
+# define NI_DIG_FE_DIG_MODE(x) (((x) & 0x7) << 16)
+# define NI_DIG_HPD_SELECT(x) (((x) & 0x7) << 28)
+
+#define NI_DIG_FE_CNTL 0x7000
+# define NI_DIG_SOURCE_SELECT(x) (((x) & 0x3) << 0)
+# define NI_DIG_STEREOSYNC_SELECT(x) (((x) & 0x3) << 4)
+# define NI_DIG_STEREOSYNC_GATE_EN(x) (((x) & 0x1) << 8)
+# define NI_DIG_DUAL_LINK_ENABLE(x) (((x) & 0x1) << 16)
+# define NI_DIG_SWAP(x) (((x) & 0x1) << 18)
+# define NI_DIG_SYMCLK_FE_ON (0x1 << 24)
#endif
--
2.1.0
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next prev parent reply other threads:[~2015-02-23 23:24 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-23 23:23 [RFC] radeon MST support - initial pieces Dave Airlie
2015-02-23 23:23 ` [PATCH 01/10] drm/dp_mst: add a function to retrieve vcpi slots Dave Airlie
2015-02-24 10:08 ` Daniel Vetter
2015-02-23 23:23 ` [PATCH 02/10] radeon: introduce a dp_work handler Dave Airlie
2015-02-23 23:23 ` [PATCH 03/10] radeon/evergreen: add support for short HPD irqs Dave Airlie
2015-02-23 23:23 ` [PATCH 04/10] radeon/si: " Dave Airlie
2015-02-23 23:23 ` [PATCH 05/10] radeon/fb: add wrapper functions around fb connector add/remove Dave Airlie
2015-02-23 23:24 ` Dave Airlie [this message]
2015-02-23 23:24 ` [PATCH 07/10] drm/radeon: add new atombios encoder/transmitter interfaces Dave Airlie
2015-02-23 23:24 ` [PATCH 08/10] drm/radeon: export max link rate calculation Dave Airlie
2015-02-23 23:24 ` [PATCH 09/10] drm/radeon: improve encoder picking functions Dave Airlie
2015-02-23 23:24 ` [PATCH 10/10] drm/radeon: add DisplayPort MST support Dave Airlie
2015-02-24 20:00 ` [RFC] radeon MST support - initial pieces Alex Deucher
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