From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mikko Perttunen Subject: [PATCH 0/5] Host1x/TegraDRM fixes/improvements Date: Wed, 8 Jul 2015 14:27:43 +0300 Message-ID: <1436354868-24309-1-git-send-email-mperttunen@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org Cc: airlied-cv59FeDIM0c@public.gmane.org, swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org, gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, amerilainen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Mikko Perttunen List-Id: dri-devel@lists.freedesktop.org Hi, this series has a few small improvements for Host1x and TegraDRM that the VIC series will build upon. 1/5 is a bug fix to host1x. 2/5 is required by VIC code to implement ->is_addr_reg(). 3/5 deduplicates handling of HOST1X class address registers and fixes the checked registers. 4/5 is required for the host1x firewall to work when bo's are mapped using IOMMU. 5/5 adds a TegraDRM allocator that allows drivers to allocate non-GEM memory that is still mapped to the TegraDRM domain. Arto Merilainen (3): host1x: Store device address to all bufs host1x: Pass register value in firewall drm/tegra: Support kernel mappings with IOMMU Mikko Perttunen (2): host1x: Handle HOST1X class address registers directly drm/tegra: Add Tegra DRM allocation API drivers/gpu/drm/tegra/drm.c | 99 +++++++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/tegra/drm.h | 13 +++++- drivers/gpu/drm/tegra/gem.c | 34 +++++++++++++-- drivers/gpu/drm/tegra/gr2d.c | 25 ++++------- drivers/gpu/drm/tegra/gr3d.c | 24 ++++------- drivers/gpu/host1x/job.c | 54 +++++++++++++++++------- include/linux/host1x.h | 4 +- 7 files changed, 193 insertions(+), 60 deletions(-) -- 2.1.4