From: Stefan Agner <stefan@agner.ch>
To: dri-devel@lists.freedesktop.org
Cc: meng.yi@nxp.com, alison.wang@freescale.com,
daniel.vetter@ffwll.ch, linux-kernel@vger.kernel.org
Subject: [PATCH 1/2] drm/fsl-dcu: fix register initialization
Date: Wed, 20 Jan 2016 18:50:26 -0800 [thread overview]
Message-ID: <1453344627-3894-1-git-send-email-stefan@agner.ch> (raw)
The layer enumeration start with 0 (0-15 for LS1021a and 0-63 for
Vybrid) whereas the register enumeration start from 1 (1-10 for
LS1021a and 1-9 for Vybrid). The loop started off from 0 for both
iterations and initialized the number of layers inclusive, which
is one layer too many.
All extensively written registers seem to be unassigned, it seems
that the write to those registers did not do any harm in practice.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
This two patches apply cleanly on top of my earlier DCU fixes
patchset:
https://lkml.org/lkml/2015/11/18/953
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index db69725..3c92889 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -169,8 +169,8 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
reg_num = LS1021A_LAYER_REG_NUM;
else
reg_num = VF610_LAYER_REG_NUM;
- for (i = 0; i <= fsl_dev->soc->total_layer; i++) {
- for (j = 0; j < reg_num; j++)
+ for (i = 0; i < fsl_dev->soc->total_layer; i++) {
+ for (j = 1; j <= reg_num; j++)
regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
}
regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
--
2.7.0
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next reply other threads:[~2016-01-21 2:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-21 2:50 Stefan Agner [this message]
2016-01-21 2:50 ` [PATCH 2/2] drm/fsl-dcu: use flat regmap cache Stefan Agner
2016-02-03 0:39 ` Stefan Agner
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