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From: Tiago Vignatti <tiago.vignatti@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: daniel.vetter@ffwll.ch
Subject: [PATCH] prime_mmap_coherency: Add return error tests for prime sync ioctl
Date: Thu, 17 Mar 2016 15:18:03 -0300	[thread overview]
Message-ID: <1458238683-11093-1-git-send-email-tiago.vignatti@intel.com> (raw)
In-Reply-To: <56E71D36.1060205@intel.com>

This patch adds ioctl-errors subtest to be used for exercising prime sync ioctl
errors.

The subtest constantly interrupts via signals a function doing concurrent blit
to stress out the right usage of prime_sync_*, making sure these ioctl errors
are handled accordingly. Important to note that in case of failure (e.g. in a
case where the ioctl wouldn't try again in a return error) this test does not
reliably catch the problem with 100% of accuracy.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tiago Vignatti <tiago.vignatti@intel.com>
---

Chris, your unpolished dma-buf patch for adding return error into the ioctl
calls lgtm. Let me know if you think this kind of test is useful now in igt.

Thanks

Tiago

 tests/prime_mmap_coherency.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 87 insertions(+)

diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c
index 180d8a4..bae2144 100644
--- a/tests/prime_mmap_coherency.c
+++ b/tests/prime_mmap_coherency.c
@@ -180,6 +180,88 @@ static void test_write_flush(bool expect_stale_cache)
 	munmap(ptr_cpu, width * height);
 }
 
+static void blit_and_cmp(void)
+{
+	drm_intel_bo *bo_1;
+	drm_intel_bo *bo_2;
+	uint32_t *ptr_cpu;
+	uint32_t *ptr2_cpu;
+	int dma_buf_fd, dma_buf2_fd, i;
+	int local_fd;
+	drm_intel_bufmgr *local_bufmgr;
+	struct intel_batchbuffer *local_batch;
+
+	/* recreate process local variables */
+	local_fd = drm_open_driver(DRIVER_INTEL);
+	local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096);
+	igt_assert(local_bufmgr);
+
+	local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd));
+	igt_assert(local_batch);
+
+	bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096);
+	dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle);
+	igt_skip_on(errno == EINVAL);
+
+	ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
+			MAP_SHARED, dma_buf_fd, 0);
+	igt_assert(ptr_cpu != MAP_FAILED);
+
+	bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096);
+	dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle);
+
+	ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE,
+			MAP_SHARED, dma_buf2_fd, 0);
+	igt_assert(ptr2_cpu != MAP_FAILED);
+
+	/* Fill up BO 1 with '1's and BO 2 with '0's */
+	prime_sync_start(dma_buf_fd, true);
+	memset(ptr_cpu, 0x11, width * height);
+	prime_sync_end(dma_buf_fd, true);
+
+	prime_sync_start(dma_buf2_fd, true);
+	memset(ptr2_cpu, 0x00, width * height);
+	prime_sync_end(dma_buf2_fd, true);
+
+	/* Copy BO 1 into BO 2, using blitter. */
+	intel_copy_bo(local_batch, bo_2, bo_1, width * height);
+	usleep(0); /* let someone else claim the mutex */
+
+	/* Compare BOs. If prime_sync_* were executed properly, the caches
+	 * should be synced. */
+	prime_sync_start(dma_buf2_fd, true);
+	for (i = 0; i < (width * height) / 4; i++)
+		igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i);
+	prime_sync_end(dma_buf2_fd, true);
+
+	drm_intel_bo_unreference(bo_1);
+	drm_intel_bo_unreference(bo_2);
+	munmap(ptr_cpu, width * height);
+	munmap(ptr2_cpu, width * height);
+}
+
+/*
+ * Constantly interrupt concurrent blits to stress out prime_sync_* and make
+ * sure these ioctl errors are handled accordingly.
+ *
+ * Important to note that in case of failure (e.g. in a case where the ioctl
+ * wouldn't try again in a return error) this test does not reliably catch the
+ * problem with 100% of accuracy.
+ */
+static void test_ioctl_errors(void)
+{
+	int i;
+	int num_children = 8*sysconf(_SC_NPROCESSORS_ONLN);
+
+	igt_fork_signal_helper();
+	igt_fork(child, num_children) {
+		for (i = 0; i < ROUNDS; i++)
+			blit_and_cmp();
+	}
+	igt_waitchildren();
+	igt_stop_signal_helper();
+}
+
 int main(int argc, char **argv)
 {
 	int i;
@@ -235,6 +317,11 @@ int main(int argc, char **argv)
 		igt_fail_on_f(!stale, "couldn't find any stale cache lines\n");
 	}
 
+	igt_subtest("ioctl-errors") {
+		igt_info("exercising concurrent blit to get ioctl errors\n");
+		test_ioctl_errors();
+	}
+
 	igt_fixture {
 		intel_batchbuffer_free(batch);
 		drm_intel_bufmgr_destroy(bufmgr);
-- 
2.1.4

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  parent reply	other threads:[~2016-03-17 18:18 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-22 21:36 Direct userspace dma-buf mmap (v7) Tiago Vignatti
2015-12-22 21:36 ` [PATCH v7 1/5] drm: prime: Honour O_RDWR during prime-handle-to-fd Tiago Vignatti
2015-12-22 21:36 ` [PATCH v7 2/5] dma-buf: Remove range-based flush Tiago Vignatti
2015-12-22 21:36 ` [PATCH v7 3/5] dma-buf: Add ioctls to allow userspace to flush Tiago Vignatti
2016-02-09  9:26   ` David Herrmann
2016-02-09 10:20     ` Daniel Vetter
2016-02-09 10:52       ` Daniel Vetter
2016-02-11 17:54     ` Tiago Vignatti
2016-02-11 18:00       ` Alex Deucher
2016-02-11 18:08       ` David Herrmann
2016-02-11 18:08       ` Ville Syrjälä
2016-02-11 18:19         ` David Herrmann
2016-02-11 19:10           ` Ville Syrjälä
2016-02-11 22:04             ` [PATCH v9] " Tiago Vignatti
2016-02-12 14:50               ` David Herrmann
2016-02-12 15:02                 ` Daniel Vetter
2016-02-25 18:01               ` Chris Wilson
2016-02-29 14:54                 ` Daniel Vetter
2016-02-29 15:02                   ` Chris Wilson
2016-03-05  9:34                     ` Daniel Vetter
2016-03-14 20:21                       ` Tiago Vignatti
2016-03-15  8:51                         ` Chris Wilson
2016-03-17 18:18                         ` Tiago Vignatti [this message]
2016-03-17 21:01                           ` [PATCH] prime_mmap_coherency: Add return error tests for prime sync ioctl Chris Wilson
2016-03-17 21:15                             ` Tiago Vignatti
2016-03-17 21:18                             ` [PATCH v2] " Tiago Vignatti
2016-03-18  9:44                               ` Chris Wilson
2016-03-18  9:53                                 ` [Intel-gfx] " Chris Wilson
2016-03-18 18:08                                 ` [PATCH v3] " Tiago Vignatti
2016-03-18 18:11                                   ` Daniel Vetter
2016-03-18 18:17                                     ` Tiago Vignatti
2016-03-18 20:43                                   ` Chris Wilson
2015-12-22 21:36 ` [PATCH v7 4/5] drm/i915: Implement end_cpu_access Tiago Vignatti
2015-12-22 21:36 ` [PATCH v7 5/5] drm/i915: Use CPU mapping for userspace dma-buf mmap() Tiago Vignatti
2015-12-22 21:36 ` [PATCH igt v7 1/6] lib: Add gem_userptr and __gem_userptr helpers Tiago Vignatti
2015-12-22 21:36 ` [PATCH igt v7 2/6] prime_mmap: Add new test for calling mmap() on dma-buf fds Tiago Vignatti
2015-12-22 21:36 ` [PATCH igt v7 3/6] prime_mmap: Add basic tests to write in a bo using CPU Tiago Vignatti
2015-12-22 21:36 ` [PATCH igt v7 4/6] lib: Add prime_sync_start and prime_sync_end helpers Tiago Vignatti
2015-12-22 21:36 ` [PATCH igt v7 5/6] tests: Add kms_mmap_write_crc for cache coherency tests Tiago Vignatti
2015-12-22 21:36 ` [PATCH igt v7 6/6] tests: Add prime_mmap_coherency " Tiago Vignatti
2016-02-04 20:55 ` Direct userspace dma-buf mmap (v7) Stéphane Marchesin
2016-02-05 13:53   ` Tiago Vignatti
2016-02-09  8:47     ` Daniel Vetter

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