[PATCH 0/5] drm/i915: Additional PSR stuff

[PATCH 0/5] drm/i915: Additional PSR stuff

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Some more PSR stuff. Some of this depends on Daniel's PSR fixes [1].

The most important thing here for my HSW HSB machine is the
drm_dp_psr_need_train_on_exit() check, since apparently the VBT on that
thing is no good.

[1] https://lists.freedesktop.org/archives/intel-gfx/2016-May/096048.html

Ville Syrjälä (5):
  drm/dp: Add drm_dp_psr_setup_time()
  drm/i915: Check PSR setup time vs. vblank length
  drm/dp: Add drm_dp_psr_need_train_on_exit()
  drm/i915: Ask the sink whether training is required when exiting PSR
    main-link off mode
  drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()

 drivers/gpu/drm/drm_dp_helper.c     | 42 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h    |  2 ++
 drivers/gpu/drm/i915/intel_psr.c    | 63 ++++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c |  6 ++--
 include/drm/drm_dp_helper.h         |  3 ++
 5 files changed, 91 insertions(+), 25 deletions(-)

-- 
2.7.4

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[PATCH 1/5] drm/dp: Add drm_dp_psr_setup_time()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a small helper to parse the PSR setup time from the DPCD PSR
capabilities and return the value in microseconds.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 28 ++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |  2 ++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eeaf5a7c3aa7..71309778f3d3 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -822,3 +822,31 @@ void drm_dp_aux_unregister(struct drm_dp_aux *aux)
 	i2c_del_adapter(&aux->ddc);
 }
 EXPORT_SYMBOL(drm_dp_aux_unregister);
+
+/**
+ * drm_dp_psr_setup_time() - PSR setup in time usec
+ * @psr_cap: PSR capabilities from DPCD
+ *
+ * Returns:
+ * PSR setup time for the panel in microseconds,  negative
+ * error code on failure.
+ */
+int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
+{
+	static const u16 psr_setup_time_us[] = {
+		[DP_PSR_SETUP_TIME_330] = 330,
+		[DP_PSR_SETUP_TIME_275] = 275,
+		[DP_PSR_SETUP_TIME_165] = 165,
+		[DP_PSR_SETUP_TIME_110] = 110,
+		[DP_PSR_SETUP_TIME_55] = 55,
+		[DP_PSR_SETUP_TIME_0] = 0,
+	};
+	int i;
+
+	i = psr_cap[1] & DP_PSR_SETUP_TIME_MASK;
+	if (i >= ARRAY_SIZE(psr_setup_time_us))
+		return -EINVAL;
+
+	return psr_setup_time_us[i];
+}
+EXPORT_SYMBOL(drm_dp_psr_setup_time);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5a848e734422..6aa74f7d45b4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -657,6 +657,8 @@ struct edp_vsc_psr {
 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
 
+int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
+
 static inline int
 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 {
-- 
2.7.4

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[PATCH v2 1/5] drm/dp: Add drm_dp_psr_setup_time()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a small helper to parse the PSR setup time from the DPCD PSR
capabilities and return the value in microseconds.

v2: Don't waste so many bytes on the psr_setup_time_us[] table

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 32 ++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h     |  2 ++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eeaf5a7c3aa7..1f914629031e 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -822,3 +822,35 @@ void drm_dp_aux_unregister(struct drm_dp_aux *aux)
 	i2c_del_adapter(&aux->ddc);
 }
 EXPORT_SYMBOL(drm_dp_aux_unregister);
+
+#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
+
+/**
+ * drm_dp_psr_setup_time() - PSR setup in time usec
+ * @psr_cap: PSR capabilities from DPCD
+ *
+ * Returns:
+ * PSR setup time for the panel in microseconds,  negative
+ * error code on failure.
+ */
+int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
+{
+	static const u16 psr_setup_time_us[] = {
+		PSR_SETUP_TIME(330),
+		PSR_SETUP_TIME(275),
+		PSR_SETUP_TIME(165),
+		PSR_SETUP_TIME(110),
+		PSR_SETUP_TIME(55),
+		PSR_SETUP_TIME(0),
+	};
+	int i;
+
+	i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
+	if (i >= ARRAY_SIZE(psr_setup_time_us))
+		return -EINVAL;
+
+	return psr_setup_time_us[i];
+}
+EXPORT_SYMBOL(drm_dp_psr_setup_time);
+
+#undef PSR_SETUP_TIME
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5a848e734422..6aa74f7d45b4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -657,6 +657,8 @@ struct edp_vsc_psr {
 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
 
+int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
+
 static inline int
 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 {
-- 
2.7.4

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[PATCH 2/5] drm/i915: Check PSR setup time vs. vblank length

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bspec says:
"Restriction : SRD must not be enabled when the PSR Setup time from DPCD
00071h is greater than the time for vertical blank minus one line."

Let's check for that and disallow PSR if we exceed the limit.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h    |  2 ++
 drivers/gpu/drm/i915/intel_psr.c    | 19 ++++++++++++++++++-
 drivers/gpu/drm/i915/intel_sprite.c |  6 +++---
 3 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3536292babe0..35c3c0d57f1b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1676,6 +1676,8 @@ bool intel_sdvo_init(struct drm_device *dev,
 
 
 /* intel_sprite.c */
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+			     int usecs);
 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 			      struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bebad90bea1f..3d172b91a469 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -330,6 +330,9 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_crtc *crtc = dig_port->base.base.crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	const struct drm_display_mode *adjusted_mode =
+		&intel_crtc->config->base.adjusted_mode;
+	int psr_setup_time;
 
 	lockdep_assert_held(&dev_priv->psr.lock);
 	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
@@ -368,11 +371,25 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 	}
 
 	if (IS_HASWELL(dev) &&
-	    intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 		return false;
 	}
 
+	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+	if (psr_setup_time < 0) {
+		DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",
+			      intel_dp->psr_dpcd[1]);
+		return false;
+	}
+
+	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
+	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
+		DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",
+			      psr_setup_time);
+		return false;
+	}
+
 	dev_priv->psr.source_ok = true;
 	return true;
 }
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 57eef129c597..22ebccb64065 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -53,8 +53,8 @@ format_is_yuv(uint32_t format)
 	}
 }
 
-static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
-			      int usecs)
+int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
+			     int usecs)
 {
 	/* paranoia */
 	if (!adjusted_mode->crtc_htotal)
@@ -93,7 +93,7 @@ void intel_pipe_update_start(struct intel_crtc *crtc)
 		vblank_start = DIV_ROUND_UP(vblank_start, 2);
 
 	/* FIXME needs to be calibrated sensibly */
-	min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
+	min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
 	max = vblank_start - 1;
 
 	local_irq_disable();
-- 
2.7.4

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[PATCH 3/5] drm/dp: Add drm_dp_psr_need_train_on_exit()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a small helper to parse from the DPCD whether link training
is required when exiting PSR main-link off mode.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++
 include/drm/drm_dp_helper.h     |  1 +
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 71309778f3d3..9c0a3e966d0d 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -850,3 +850,17 @@ int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
 	return psr_setup_time_us[i];
 }
 EXPORT_SYMBOL(drm_dp_psr_setup_time);
+
+/**
+ * drm_dp_psr_need_train_on_exit() - Indicate whether link training is needed on PSR exit
+ * @psr_cap: PSR capabilities from DPCD
+ *
+ * Returns:
+ * Whether link training is required when exiting PSR main-link off mode.
+ */
+bool drm_dp_psr_need_train_on_exit(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
+{
+	/* DP_PSR_NO_TRAIN_ON_EXIT is "don't care" for PSR2 capable devices */
+	return psr_cap[0] < 0x2 && (psr_cap[1] & DP_PSR_NO_TRAIN_ON_EXIT) == 0;
+}
+EXPORT_SYMBOL(drm_dp_psr_need_train_on_exit);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6aa74f7d45b4..2437f1b6e776 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -658,6 +658,7 @@ struct edp_vsc_psr {
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
 
 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
+bool drm_dp_psr_need_train_on_exit(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
 
 static inline int
 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
-- 
2.7.4

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[PATCH 4/5] drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The sink can tell us if link training needs to be performed when
exiting PSR main-link off mode. Currently we get that information
from the VBT, but at least on my HSW the VBT says one thing, the sink
another. And in practice the sink doesn't seem to notice any screen
updates unless we do the training.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 3d172b91a469..6cab66b1b26a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -298,7 +298,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 	else
 		val |= EDP_PSR_TP1_TP2_SEL;
 
-	if (!dev_priv->vbt.psr.require_aux_wakeup)
+	if (!dev_priv->vbt.psr.require_aux_wakeup &&
+	    !drm_dp_psr_need_train_on_exit(intel_dp->psr_dpcd))
 		val |= EDP_PSR_SKIP_AUX_EXIT;
 
 	I915_WRITE(EDP_PSR_CTL, val);
-- 
2.7.4

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Re: [PATCH 4/5] drm/i915: Ask the sink whether training is required when exiting PSR main-link off mode

[Daniel Vetter]

On Wed, May 18, 2016 at 09:34:21PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The sink can tell us if link training needs to be performed when
> exiting PSR main-link off mode. Currently we get that information
> from the VBT, but at least on my HSW the VBT says one thing, the sink
> another. And in practice the sink doesn't seem to notice any screen
> updates unless we do the training.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

For 3&4: Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Need to make sure we merge this one together with mine, or just squash.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_psr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 3d172b91a469..6cab66b1b26a 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -298,7 +298,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>  	else
>  		val |= EDP_PSR_TP1_TP2_SEL;
>  
> -	if (!dev_priv->vbt.psr.require_aux_wakeup)
> +	if (!dev_priv->vbt.psr.require_aux_wakeup &&
> +	    !drm_dp_psr_need_train_on_exit(intel_dp->psr_dpcd))
>  		val |= EDP_PSR_SKIP_AUX_EXIT;
>  
>  	I915_WRITE(EDP_PSR_CTL, val);
> -- 
> 2.7.4
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[PATCH 5/5] drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Determine the value of psr.link_standby at runtime rather than at init
time. This helps in testing since you can change between link-off and
link-standby at runtime.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 41 ++++++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6cab66b1b26a..c814a4443749 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -339,6 +339,27 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
 
+	/* Set link_standby x link_off defaults */
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		/* HSW and BDW require workarounds that we don't implement. */
+		dev_priv->psr.link_standby = false;
+	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+		/* On VLV and CHV only standby mode is supported. */
+		dev_priv->psr.link_standby = true;
+	else
+		/* For new platforms let's respect VBT back again */
+		dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
+
+	/* Override link_standby x link_off defaults */
+	if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
+		DRM_DEBUG_KMS("PSR: Forcing link standby\n");
+		dev_priv->psr.link_standby = true;
+	}
+	if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
+		DRM_DEBUG_KMS("PSR: Forcing main link off\n");
+		dev_priv->psr.link_standby = false;
+	}
+
 	dev_priv->psr.source_ok = false;
 
 	/*
@@ -831,26 +852,6 @@ void intel_psr_init(struct drm_device *dev)
 			i915.enable_psr = 0;
 	}
 
-	/* Set link_standby x link_off defaults */
-	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
-		/* HSW and BDW require workarounds that we don't implement. */
-		dev_priv->psr.link_standby = false;
-	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
-		/* On VLV and CHV only standby mode is supported. */
-		dev_priv->psr.link_standby = true;
-	else
-		/* For new platforms let's respect VBT back again */
-		dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
-
-	/* Override link_standby x link_off defaults */
-	if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
-		DRM_DEBUG_KMS("PSR: Forcing link standby\n");
-		dev_priv->psr.link_standby = true;
-	}
-	if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
-		DRM_DEBUG_KMS("PSR: Forcing main link off\n");
-		dev_priv->psr.link_standby = false;
-	}
 
 	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
 	mutex_init(&dev_priv->psr.lock);
-- 
2.7.4

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Re: [PATCH 5/5] drm/i915: Move psr.link_standby setup to intel_psr_match_conditions()

[Daniel Vetter]

On Wed, May 18, 2016 at 09:34:22PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Determine the value of psr.link_standby at runtime rather than at init
> time. This helps in testing since you can change between link-off and
> link-standby at runtime.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 41 ++++++++++++++++++++--------------------
>  1 file changed, 21 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6cab66b1b26a..c814a4443749 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -339,6 +339,27 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>  	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>  	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
>  
> +	/* Set link_standby x link_off defaults */
> +	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +		/* HSW and BDW require workarounds that we don't implement. */
> +		dev_priv->psr.link_standby = false;
> +	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> +		/* On VLV and CHV only standby mode is supported. */
> +		dev_priv->psr.link_standby = true;
> +	else
> +		/* For new platforms let's respect VBT back again */
> +		dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;

One thing we discussed here (well Rodrigo raised it) that by default we
shouldn't override the platform wa settings, in case the vbt is broken.
Instead when they're incompatible we should just disable PSR.

But that's definitely for another patch, and has a good chance to break
working setups. On this one:

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> +
> +	/* Override link_standby x link_off defaults */
> +	if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
> +		DRM_DEBUG_KMS("PSR: Forcing link standby\n");
> +		dev_priv->psr.link_standby = true;
> +	}
> +	if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
> +		DRM_DEBUG_KMS("PSR: Forcing main link off\n");
> +		dev_priv->psr.link_standby = false;
> +	}
> +
>  	dev_priv->psr.source_ok = false;
>  
>  	/*
> @@ -831,26 +852,6 @@ void intel_psr_init(struct drm_device *dev)
>  			i915.enable_psr = 0;
>  	}
>  
> -	/* Set link_standby x link_off defaults */
> -	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -		/* HSW and BDW require workarounds that we don't implement. */
> -		dev_priv->psr.link_standby = false;
> -	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> -		/* On VLV and CHV only standby mode is supported. */
> -		dev_priv->psr.link_standby = true;
> -	else
> -		/* For new platforms let's respect VBT back again */
> -		dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;
> -
> -	/* Override link_standby x link_off defaults */
> -	if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) {
> -		DRM_DEBUG_KMS("PSR: Forcing link standby\n");
> -		dev_priv->psr.link_standby = true;
> -	}
> -	if (i915.enable_psr == 3 && dev_priv->psr.link_standby) {
> -		DRM_DEBUG_KMS("PSR: Forcing main link off\n");
> -		dev_priv->psr.link_standby = false;
> -	}
>  
>  	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
>  	mutex_init(&dev_priv->psr.lock);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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