From: Meng Yi <meng.yi@nxp.com>
To: stefan@agner.ch, airlied@linux.ie
Cc: dri-devel@lists.freedesktop.org, Meng Yi <meng.yi@nxp.com>
Subject: [PATCH v2] drm/fsl-dcu: Fix endian issue when using clk_register_divider
Date: Fri, 26 Aug 2016 17:53:32 +0800 [thread overview]
Message-ID: <1472205212-35718-1-git-send-email-meng.yi@nxp.com> (raw)
While clk_register_divider will write register as little endian,
Modified the param "shift" from 0 to 24 since DCU is big endian.
Or reg "DCU_DIV_RATIO" will be seted as a incorrect value which
will cause vblank timing issue etc.
Signed-off-by: Meng Yi <meng.yi@nxp.com>
---
Changes in V2:
-check the soc name to decide the "shift" value
since vf610's divider reg is little endian while
ls1021a's divider reg is big endian
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 7882387..a590ce8 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -386,7 +386,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
pix_clk_in_name, 0, base + DCU_DIV_RATIO,
- 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
+ !strcmp(fsl_dev->soc->name, "ls1021a")?24:0, 8,
+ CLK_DIVIDER_ROUND_CLOSEST, NULL);
if (IS_ERR(fsl_dev->pix_clk)) {
dev_err(dev, "failed to register pix clk\n");
ret = PTR_ERR(fsl_dev->pix_clk);
--
2.1.0.27.g96db324
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next reply other threads:[~2016-08-26 10:05 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-26 9:53 Meng Yi [this message]
2016-08-30 2:33 ` [PATCH v2] drm/fsl-dcu: Fix endian issue when using clk_register_divider Meng Yi
2016-08-30 2:35 ` Meng Yi
2016-09-01 6:42 ` Meng Yi
2016-09-02 17:56 ` Stefan Agner
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